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1. 发明申请

US20040262264A1 IMPROVED CD UNIFORMITY OF CHROME ETCH TO PHOTOMASK PROCESS 失效
标题翻译：改进CD对光刻胶工艺的均匀性
公开(公告)号：US20040262264A1
公开(公告)日：2004-12-30
申请号：US10605801
申请日：2003-10-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Shaun B. Crawford , Timothy J. Dalton , Thomas B. Faure , Cuc K. Huynh , Michelle L. Steen , Thomas M. Wagner
IPC分类号： B44C001/22 , C23F001/00 , G03F009/00 , C23F003/00
CPC分类号： C23F4/00 , G03F1/80 , H01L21/0332 , H01L21/32136
摘要： A photomask is formed by depositing an opaque layer on a transparent substrate. A resist is formed on the opaque layer and selectively patterned to expose the portions of the opaque layer that are to be etched out. During the dry etching step, the photomask is exposed to an etchant gas mixture which exhibits a selectivity equal to or higher than 1.2:1 between the opaque layer and the resist layer. Due to the selectivity of the gas mixture, a thinner resist film can be used, thereby increasing resolution and accuracy of the opaque layer pattern. Also, due to reduced susceptibility to both a macro-loading effect and a pattern density effect, overetching of the resist and underetching of the opaque layer are significantly reduced, thereby achieving improved etching uniformity and consequently improved CD uniformity.
摘要翻译：通过在透明基底上沉积不透明层而形成光掩模。抗蚀剂形成在不透明层上并选择性地图案化以暴露待被蚀刻出的不透明层的部分。在干蚀刻步骤期间，光掩模暴露于在不透明层和抗蚀剂层之间具有等于或高于1.2:1的选择性的蚀刻剂气体混合物。由于气体混合物的选择性，可以使用更薄的抗蚀剂膜，从而提高不透明层图案的分辨率和精度。此外，由于对宏观负载效应和图案密度效应的敏感性降低，抗蚀剂的过蚀刻和不透明层的去抛光显着降低，从而实现了改进的蚀刻均匀性并因此改善了CD均匀性。

2. 发明申请

US20040262263A1 Etching methods and apparatus and substrate assemblies produced therewith 有权
标题翻译：蚀刻方法及其制造的装置和基板组件
公开(公告)号：US20040262263A1
公开(公告)日：2004-12-30
申请号：US10895502
申请日：2004-07-20
申请人： Micron Technology, Inc.
发明人： Kevin G. Donohoe , Rich Stocks
IPC分类号： C23F001/00
CPC分类号： H01J37/321 , H01J2237/3345 , H01J2237/3347 , H01L21/3085 , H01L21/31116 , H01L21/31144 , H01L21/32137 , H01L21/32139 , H01L21/76232 , Y10S428/901 , Y10T428/24479 , Y10T428/2457
摘要： Methods and apparatus for etching substrates such as silicon wafers are provided. In one specific approach, a surface of the substrate assembly is covered with a resist that is patterned to define features to be etched. In this approach, the surface is then exposed to a plasma in a plasma etcher so that surface areas not covered with the resist are etched, while the thickness of the resist increases or etches at a rate that is at least ten times slower than that of the exposed areas of the surface. This etching process can be followed with a conventional plasma etch. By combining the etching that increases the resist thickness with the conventional etching of resist in which the resist thins during etching, features having high-aspect-ratios can be etched.
摘要翻译：提供了用于蚀刻诸如硅晶片的基板的方法和装置。在一种具体方法中，衬底组件的表面被图案化的抗蚀剂覆盖以限定待蚀刻的特征。在这种方法中，然后将表面暴露于等离子体蚀刻器中的等离子体，使得未被抗蚀剂覆盖的表面区域被蚀刻，同时抗蚀剂的厚度增加或蚀刻速率至少比表面的暴露区域。该蚀刻工艺可以用常规等离子体蚀刻来进行。通过将蚀刻加强抗蚀剂厚度的蚀刻与蚀刻时的抗蚀剂凹陷的抗蚀剂的常规蚀刻相结合，可以蚀刻具有高纵横比的特征。

3. 发明申请

US20040256358A1 Method for releasing resist 审中-公开
标题翻译：释放抗蚀剂的方法
公开(公告)号：US20040256358A1
公开(公告)日：2004-12-23
申请号：US10493700
申请日：2004-04-27
发明人： Hidetaka Shimizu , Hiroshi Matsunaga , Masaru Ohto , Kazuto Ikemoto
IPC分类号： C23F001/00
CPC分类号： H01L21/02052 , G03F7/425 , H01L21/31133 , H01L21/31138
摘要： In the resist stripping method of the present invention, a wiring substrate having a remaining resist layer is brought into contact with a resist stripping composition in an atmosphere containing oxygen in a proportion of 2% by volume or less. Preferably, the resist is removed after pretreating the remaining resist layer with hydrogen peroxide. A resist stripping composition comprising an amine compound, a solvent, a strong alkali, and water is preferably used in the resist stripping method of the present invention.
摘要翻译：在本发明的抗蚀剂剥离方法中，具有剩余抗蚀剂层的布线基板在含氧量为2体积％以下的气氛中与抗蚀剂剥离组合物接触。优选地，在用过氧化氢预处理剩余的抗蚀剂层之后去除抗蚀剂。在本发明的抗蚀剂剥离方法中优选使用包含胺化合物，溶剂，强碱和水的抗蚀剂剥离组合物。

4. 发明申请

US20040256357A1 Methods of etching photoresist on substrates 有权
标题翻译：在基板上蚀刻光刻胶的方法
公开(公告)号：US20040256357A1
公开(公告)日：2004-12-23
申请号：US10462830
申请日：2003-06-17
发明人： Erik A. Edelberg , Robert P. Chebi , Gladys Sowan Lo
IPC分类号： C23F001/00
CPC分类号： H01L21/31138 , G03F7/427
摘要： Methods of etching a carbon-rich layer on organic photoresist overlying an inorganic layer can utilize a process gas including CxHyFz, where ynullx and znull0, and one or more optional components to generate a plasma effective to etch the carbon-rich layer with low removal of the inorganic layer. The carbon-rich layer can be removed in the same processing chamber, or alternatively can be removed in a different processing chamber, as used to remove the bulk photoresist.
摘要翻译：在覆盖无机层的有机光刻胶上蚀刻富碳层的方法可以利用包括C x H y F z的工艺气体，其中y> = x和z> = 0，以及一种或多种任选组分以产生有效蚀刻碳 - 富层，无机层去除率低。富碳层可以在相同的处理室中除去，或者可以在不同的处理室中除去，以用于去除体光致抗蚀剂。

5. 发明申请

US20040250954A1 Plasma chamber 审中-公开
标题翻译：等离子室
公开(公告)号：US20040250954A1
公开(公告)日：2004-12-16
申请号：US10829136
申请日：2004-04-21
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Hee-hwan Choe , Sang-gab Kim , Sung-chul Kang , In-ho Song
IPC分类号： C23F001/00
CPC分类号： H01J37/32174 , H01J37/32082
摘要： A plasma chamber comprising a lower electrode and an upper electrode, and used for dry-etching an LCD, comprises a main power supply comprising a main power source to generate a main voltage having a predetermined main frequency, and a first impedance matching circuit to impedance-match the main voltage; a bias power supply comprising a bias power source to generate a bias voltage having a predetermined bias frequency, and a second impedance matching circuit to impedance-match the bias voltage; and a mixer connected to both the first impedance matching circuit and the second impedance matching circuit, receiving and mixing the main voltage and the bias voltage, and outputting the mixed voltage to one of the lower electrode and the upper electrode. With this configuration, the present invention provides a plasma chamber in which etching conditions such as an etching rate, an etching profile, a selection ratio, etc. are precisely adjusted.
摘要翻译：包括下电极和上电极并用于干蚀刻LCD的等离子体室包括主电源，其包括主电源以产生具有预定主频率的主电压，以及第一阻抗匹配电路以阻抗 - 匹配主电压; 偏置电源，其包括偏置电源以产生具有预定偏置频率的偏置电压;以及第二阻抗匹配电路，用于阻抗匹配偏置电压; 以及连接到第一阻抗匹配电路和第二阻抗匹配电路两者的混频器，接收和混合主电压和偏置电压，并将混合电压输出到下电极和上电极之一。利用这种结构，本发明提供了一种等离子体室，其中蚀刻速率，蚀刻轮廓，选择比等蚀刻条件被精确地调节。

6. 发明申请

US20040248424A1 Compositions for dissolution of low-k dielectric film, and methods of use 有权
公开(公告)号：US20040248424A1
公开(公告)日：2004-12-09
申请号：US10889280
申请日：2004-07-12
申请人： Micron Technology, Inc.
发明人： Donald L. Yates
IPC分类号： H01L021/302 , H01L021/461 , C23F001/00 , C03C015/00
CPC分类号： C09K13/08 , B08B3/08 , C09K13/00 , C09K13/04 , C09K13/06 , C11D7/08 , C11D7/10 , C11D7/50 , C11D11/0047 , C23G1/02 , G03F7/423 , H01L21/31111 , H01L21/31133 , Y10S438/948
摘要： An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute. The composition can also be formulated to selectively remove a photoresist layer, leaving the underlying low-k dielectric layer essentially intact.

7. 发明申请

US20040245217A1 Conductive etch stop for etching a sacrificial layer 审中-公开
标题翻译：用于蚀刻牺牲层的导电蚀刻停止
公开(公告)号：US20040245217A1
公开(公告)日：2004-12-09
申请号：US10891916
申请日：2004-07-15
发明人： James A. Hunter
IPC分类号： C23F001/00
CPC分类号： G02B26/0833 , B81B2201/045 , B81C1/00531 , B81C2201/0132 , G02B26/0841
摘要： In one embodiment, a micro device is formed by depositing a sacrificial layer over a metallic electrode, forming a moveable structure over the sacrificial layer, and then etching the sacrificial layer with a noble gas fluoride. Because the metallic electrode is comprised of a metallic material that also serves as an etch stop in the sacrificial layer etch, charge does not appreciably build up in the metallic electrode. This helps stabilize the driving characteristic of the moveable structure. In one embodiment, the moveable structure is a ribbon in a light modulator.
摘要翻译：在一个实施例中，通过在金属电极上沉积牺牲层来形成微器件，在牺牲层上形成可移动结构，然后用惰性气体氟化物蚀刻牺牲层。因为金属电极由在牺牲层蚀刻中也用作蚀刻停止层的金属材料组成，所以电荷在金属电极中不会明显地积聚。这有助于稳定可移动结构的驱动特性。在一个实施例中，可移动结构是光调制器中的带状物。

8. 发明申请

US20040238124A1 Plasma treatment apparatus 有权
标题翻译：等离子体处理装置
公开(公告)号：US20040238124A1
公开(公告)日：2004-12-02
申请号：US10807472
申请日：2004-03-24
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Osamu Nakamura
IPC分类号： C23F001/00
CPC分类号： C23C16/45595 , C23C16/515 , C23C16/54 , H01J37/32009 , H01J37/32366 , H01J37/32541
摘要： In the case of generating plasma under atmospheric pressure, the particle generated due to generation of high-density plasma is to be a cause of a defect such as a point defect or a line defect of a display portion in a display device. The present invention is offered in view of the above situation, and provides a plasma treatment apparatus for suppressing generation of a particle. According to the present invention, plasma is generated in a limited minimum region to be treated by a plasma treatment over a substrate to be treated. Generation of a particle is suppressed to a minimum by providing a plurality of plasma generation units generating minimum plasma having a similar size as the limited minimum region, changing a relative position of the plurality of plasma generation units and the substrate to be treated, and performing a plasma treatment to a limited predetermined region.
摘要翻译：在大气压下产生等离子体的情况下，由于产生高密度等离子体而产生的粒子将成为显示装置中显示部的点缺陷或线缺陷等缺陷的原因。鉴于上述情况提供本发明，并且提供了一种用于抑制颗粒产生的等离子体处理装置。根据本发明，通过在待处理的基板上进行等离子体处理，在有限的最小区域中产生等离子体。通过提供多个等离子体产生单元来产生颗粒的产生，产生具有与限制的最小区域相似尺寸的最小等离子体，改变多个等离子体产生单元和待处理的基板的相对位置，并执行等离子体处理到有限的预定区域。

9. 发明申请

US20040237888A1 Optical monitoring system for plasma enhanced chemical vapor deposition 审中-公开
标题翻译：用于等离子体增强化学气相沉积的光学监测系统
公开(公告)号：US20040237888A1
公开(公告)日：2004-12-02
申请号：US10449975
申请日：2003-05-30
申请人： General Electric Company
发明人： Peter Joseph Codella , Manisha Tinani , George Theodore Dalakos , Eric Michael Breitung
IPC分类号： C23C016/00 , C23F001/00
CPC分类号： H01L21/67253 , C23C16/50 , C23C16/52 , H01J37/32935 , H01J37/32972
摘要： An optical monitoring system for a plasma enhanced chemical vapor deposition (PECVD) apparatus includes a light source for generating an input light beam, and a first port configured within the PECVD apparatus for receiving the input light beam from the light source. The first port is configured to direct the input beam upon a workpiece within the PECVD apparatus. A second port is configured within the PECVD apparatus for receiving an output light beam passed through the workpiece, and a comparing mechanism for comparing the output light beam with the input light beam is configured to determine a deposited layer thickness upon the workpiece.
摘要翻译：用于等离子体增强化学气相沉积（PECVD）装置的光学监测系统包括用于产生输入光束的光源和在PECVD装置内配置的用于接收来自光源的输入光束的第一端口。第一端口被配置为将输入光束引导到PECVD装置内的工件上。第二端口被配置在PECVD装置内用于接收通过工件的输出光束，并且用于将输出光束与输入光束进行比较的比较机构被配置为确定工件上的沉积层厚度。

10. 发明申请

US20040226912A1 Methods of etching insulative materials, of forming electrical devices, and of forming capacitors 失效
标题翻译：蚀刻绝缘材料，形成电器件和形成电容器的方法
公开(公告)号：US20040226912A1
公开(公告)日：2004-11-18
申请号：US10871291
申请日：2004-06-17
发明人： Daryl C. New
IPC分类号： C23F001/00
CPC分类号： H01L28/55 , H01L21/31105 , H01L21/31122 , H01L21/32131 , H01L21/32136
摘要： In one aspect, the invention encompasses a method of etching insulative materials which comprise complexes of metal and oxygen. The insulative materials are exposed to physical etching conditions within a reaction chamber and in the presence of at least one oxygen-containing gas. In another aspect, the invention encompasses a method of forming a capacitor. An electrically conductive first layer is formed over a substrate, and a second layer is formed over the first layer. The second layer is a dielectric layer and comprises a complex of metal and oxygen. A conductive third layer is formed over the second layer. The first, second and third layers are patterned into a capacitor construction. The patterning of the second layer comprises exposing the second layer to at least one oxygen-containing gas while also exposing the second layer to physical etching conditions.
摘要翻译：一方面，本发明包括蚀刻包含金属和氧的络合物的绝缘材料的方法。绝缘材料暴露于反应室内的物理蚀刻条件下，并在至少一种含氧气体存在下进行。另一方面，本发明包括形成电容器的方法。在衬底上形成导电的第一层，并且在第一层上形成第二层。第二层是介电层并且包含金属和氧的络合物。在第二层上形成导电的第三层。将第一，第二和第三层图案化成电容器结构。第二层的图案化包括将第二层暴露于至少一种含氧气体，同时将第二层暴露于物理蚀刻条件。

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