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    • 2. 发明授权
    • Method and apparatus for removing particulates from semiconductor substrates in plasma processing chambers
    • 用于从等离子体处理室中的半导体衬底去除微粒的方法和装置
    • US06214160B1
    • 2001-04-10
    • US09074562
    • 1998-05-07
    • Charles DornfestAnand GuptaGerald Girard
    • Charles DornfestAnand GuptaGerald Girard
    • C23F102
    • H01L21/67028B08B6/00B08B7/0035C23C16/4401H01J37/32082H01J2237/022
    • An electrostatic technique for removing particulate matter from a semiconductor wafer in a plasma processing chamber, such as a plasma-enhanced chemical vapor deposition (PECVD) chamber. During a particulate removal phase of operation, a normally grounded electrode that supports the wafer is temporarily isolated from ground and a bias voltage generator is simultaneously connected to the electrode, supplying sufficient bias voltage to electrostatically launch particulates from the surface of the wafer. A plasma formed above the normally grounded electrode is maintained during the particulate removal phase, and particulates launched from the wafer become suspended in a sheath region surrounding the plasma, from where they can be later removed by a purging flow of gas. Preferably, the bias voltage generator provides a bias voltage that alternates in polarity, to ensure removal of both positively-charged and negatively charged particles from the wafer surface.
    • 一种用于在诸如等离子体增强化学气相沉积(PECVD)室的等离子体处理室中从半导体晶片去除颗粒物质的静电技术。 在微粒去除操作阶段期间,支撑晶片的正常接地电极暂时与地离开,并且偏置电压发生器同时连接到电极,提供足够的偏压以从晶片的表面静电发射微粒。 在微粒去除阶段期间维持在正常接地电极上方形成的等离子体,并且从晶片发射的微粒悬浮在围绕等离子体的护套区域中,从那里可以通过气体的吹扫流将其去除。 优选地,偏置电压发生器提供极性交替的偏置电压,以确保从晶片表面去除带正电荷和带负电荷的颗粒。
    • 3. 发明授权
    • Method for superior step coverage and interface control for high K dielectric capacitors and related electrodes
    • 用于高K介质电容器和相关电极的优越的步距覆盖和接口控制的方法
    • US06358810B1
    • 2002-03-19
    • US09123690
    • 1998-07-28
    • Charles DornfestJohn EgermeierNitin Khurana
    • Charles DornfestJohn EgermeierNitin Khurana
    • H01L2120
    • H01L28/55H01L28/60
    • The present invention provides a multi-layer semiconductor memory device comprising: a bottom electrode having a bottom layer, an upper interface layer and an intermediate tuning layer disposed between the bottom layer and the upper interface layer; a top electrode; and a high dielectric constant dielectric layer disposed between the bottom electrode and the top electrode. The present invention further provides an apparatus and a method for manufacturing high density DRAMs having capacitors having high quality HDC materials and low leakage currents. Another aspect of the present invention provides an electrode-dielectric interface that nucleates high quality HDC films. The present invention further provides an apparatus and a method for manufacturing capacitors within a high aspect ratio aperture.
    • 本发明提供一种多层半导体存储器件,包括:底层电极,其具有底层,上界面层和设置在底层和上界面层之间的中间调谐层; 顶电极 以及设置在底部电极和顶部电极之间的高介电常数电介质层。 本发明还提供一种用于制造具有高质量HDC材料和低漏电流的电容器的高密度DRAM的装置和方法。 本发明的另一方面提供了一种使高质量HDC膜成核的电极 - 电介质界面。 本发明还提供了一种在高纵横比孔径内制造电容器的装置和方法。