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1. 发明授权

US06674807B1 Communication apparatus and method for a CDMA communication system 有权
标题翻译： CDMA通信系统的通信装置和方法
公开(公告)号：US06674807B1
公开(公告)日：2004-01-06
申请号：US09489235
申请日：2000-01-21
申请人： Chang-Soo Park , Jun-Jin Kong , Hee-Won Kang , Jae-Yoel Kim , Jong-Seon No , Kyeong-Cheol Yang
发明人： Chang-Soo Park , Jun-Jin Kong , Hee-Won Kang , Jae-Yoel Kim , Jong-Seon No , Kyeong-Cheol Yang
IPC分类号： H04L2302
CPC分类号： H04L1/0059 , H03M13/09 , H03M13/23 , H03M13/27 , H03M13/356 , H03M13/37 , H03M13/6356 , H03M13/6362 , H04L1/0041
摘要： A communication device for a direct sequence code division multiple access (DS-CDMA) communication system is disclosed. The communication device comprises a CRC (Cyclic Redundancy Code) generator for generating CRC bits according to input data bits and adding the generated CRC bits to the input data bits; a channel encoder for encoding the CRC-added data bits using a coding rate R=1/6 convolutional code of a generator polynomial of (457, 755, 551, 637, 625, 727); and an interleaver for interleaving the coded data bits.
摘要翻译：公开了一种用于直接序列码分多址（DS-CDMA）通信系统的通信设备。通信设备包括CRC（循环冗余码）发生器，用于根据输入数据位产生CRC比特，并将所生成的CRC比特加到输入数据比特; 使用（457,755,551,637,675,727）的生成多项式的编码率R = 1/6卷积码对CRC相加数据比特进行编码的信道编码器; 以及用于交织编码数据位的交织器。

2. 发明授权

US06437714B1 Channel encoding device and method for communication system 有权
标题翻译：通道编码装置及通讯方式
公开(公告)号：US06437714B1
公开(公告)日：2002-08-20
申请号：US09294658
申请日：1999-04-19
申请人： Jae-Yoel Kim , Chang-Soo Park , Hee-Won Kang , Jun-Jin Kong , Jong-Seon No , Kyeong-Cheol Yang
发明人： Jae-Yoel Kim , Chang-Soo Park , Hee-Won Kang , Jun-Jin Kong , Jong-Seon No , Kyeong-Cheol Yang
IPC分类号： H03M700
CPC分类号： H04W52/30 , H03M7/4006 , H03M13/23 , H03M13/2903 , H03M13/2993 , H03M13/6356 , H03M13/6362 , H04B7/2628 , H04B10/25754 , H04J13/0077 , H04J13/16 , H04L1/0066 , H04L1/0068 , H04L51/04 , H04L51/28 , H04L51/38 , H04L65/1006 , H04L65/1016 , H04N19/109 , H04N19/139 , H04N19/625 , H04N19/91 , H04W4/12 , H04W4/14 , H04W8/26 , H04W72/042 , H04W76/12 , H04W88/085 , Y10S370/906 , Y10S370/907
摘要： A device and method for performing channel encoding using a frame structure having a termination effect in a recursive systemic encoder for a communication system. The channel encoding device having: an inserter for inserting at least one predefined bit in an input data bit stream at a predetermined position; and a channel encoder for encoding the bit-inserted data bit stream.
摘要翻译：一种用于在通信系统的递归系统编码器中使用具有终止效应的帧结构来执行信道编码的装置和方法。信道编码装置具有：插入器，用于在预定位置插入输入数据比特流中的至少一个预定义比特; 以及用于编码位插入数据比特流的信道编码器。

3. 发明授权

US06400703B1 Device and method for generating and distributing coded symbols in a CDMA communication system 有权
标题翻译：用于在CDMA通信系统中生成和分配编码符号的装置和方法
公开(公告)号：US06400703B1
公开(公告)日：2002-06-04
申请号：US09324423
申请日：1999-06-01
申请人： Chang-Soo Park , Jun-Jin Kong , Hee-Won Kang , Jae-Yoel Kim , Jong-Seon No , Kyeong-Cheol Yang
发明人： Chang-Soo Park , Jun-Jin Kong , Hee-Won Kang , Jae-Yoel Kim , Jong-Seon No , Kyeong-Cheol Yang
IPC分类号： H04B7208
CPC分类号： H04L1/0041 , H03M13/23 , H03M13/635 , H04J13/10 , H04J13/16 , H04L1/0059 , H04L1/0068 , H04L1/0071
摘要： A device and method for generating and distributing convolutional codes such that performance degradation due to a bad link environment may be minimized during channel decoding in a CDMA communication system. The convolutional encoder encodes transmission data at a coding rate of R=1/6 and can be used for a channel encoder. Such a channel encoder can be used in both a DS-CDMA communication system and a multicarrier CDMA communication system. When the channel encoder is used in the multicarrier CDMA communication system, the symbols outputted from multiple constituent encoders for the channel encoder are distributed to multiple carrier channels according to a predetermined rule, and the constituent encoders for the channel encoder can minimize the performance degradation of the overall channel encoder even though an output of a particular constituent encoder is completely off at the transmission channel.
摘要翻译：用于生成和分配卷积码的装置和方法，使得在CDMA通信系统中的信道解码期间，由于不良链路环境导致的性能下降可能被最小化。卷积编码器以R = 1/6的编码速率对传输数据进行编码，并可用于信道编码器。这样的信道编码器可以在DS-CDMA通信系统和多载波CDMA通信系统中使用。当在多载波CDMA通信系统中使用信道编码器时，从用于信道编码器的多个组成编码器输出的符号根据预定规则分配到多个载波信道，并且信道编码器的组成编码器可以最小化性能下降即使特定构成编码器的输出在传输信道处完全关闭，整个信道编码器也是如此。

4. 发明授权

US06487693B1 Channel encoding/decoding in communication system 有权
标题翻译：通信系统中的信道编码/解码
公开(公告)号：US06487693B1
公开(公告)日：2002-11-26
申请号：US09369626
申请日：1999-08-06
申请人： Jae-Yeol Kim , Chang-Soo Park , Hee-Won Kang , Jun-Jin Kong , Jong-Seon No , Kyeong-Cheol Yang
发明人： Jae-Yeol Kim , Chang-Soo Park , Hee-Won Kang , Jun-Jin Kong , Jong-Seon No , Kyeong-Cheol Yang
IPC分类号： H03M1327
CPC分类号： H03M13/2993 , H03M13/299 , H03M13/356 , H03M13/3994
摘要： A channel decoding device for a receiver which receives symbols coded by inserting at least one specific bit in a data frame at a predetermined position. In the channel decoding device, a symbol inserter receives the symbols, inserts a symbol having a specific value at a predetermined specific bit insert position and outputs the received symbols at other positions. A decoder decodes symbols output from the symbol inserter.
摘要翻译：一种用于接收器的信道解码装置，其接收通过在预定位置插入数据帧中的至少一个特定位而被编码的符号。在信道解码装置中，符号插入器接收符号，在预定的特定位插入位置插入具有特定值的符号，并将接收的符号输出到其他位置。解码器解码从符号插入器输出的符号。

5. 发明授权

US09069714B2 Device including an external memory connection unit capable of adopting an external memory 有权
标题翻译：装置包括能够采用外部存储器的外部存储器连接单元
公开(公告)号：US09069714B2
公开(公告)日：2015-06-30
申请号：US13606551
申请日：2012-09-07
申请人： Hak-Soo Yu , Jun-Jin Kong , Hyoung-Joon Kim , Joo-Young Hwang , In-Su Choi
发明人： Hak-Soo Yu , Jun-Jin Kong , Hyoung-Joon Kim , Joo-Young Hwang , In-Su Choi
IPC分类号： G06F13/14 , G06F13/16 , G06F13/38
CPC分类号： G06F13/16 , G06F13/1694 , G06F13/385
摘要： A device includes a memory controller, a memory bus coupled to the memory controller, an internal memory and an external memory connection unit. The internal memory may be directly connected to the memory controller through the memory bus. The external memory connection unit may connect an external memory directly to the memory controller through a portion of signal lines in the memory bus, and may generate a flag signal indicating whether the external memory is connected to the external memory connection unit.
摘要翻译：设备包括存储器控制器，耦合到存储器控制器的存储器总线，内部存储器和外部存储器连接单元。内部存储器可以通过存储器总线直接连接到存储器控制器。外部存储器连接单元可以通过存储器总线中的一部分信号线将外部存储器直接连接到存储器控制器，并且可以产生指示外部存储器是否连接到外部存储器连接单元的标志信号。

6. 发明授权

US08522124B2 Semiconductor device and decoding method thereof 有权
标题翻译：半导体器件及其解码方法
公开(公告)号：US08522124B2
公开(公告)日：2013-08-27
申请号：US13069834
申请日：2011-03-23
申请人： Yong-June Kim , Jun-Jin Kong , Young-Hwan Lee , Jae-Hong Kim
发明人： Yong-June Kim , Jun-Jin Kong , Young-Hwan Lee , Jae-Hong Kim
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： G06F11/1048
摘要： An error control coding (ECC) circuit includes a first decoder, a second decoder, and a controller. The first decoder receives encoded data comprising a first parity and a second parity. The first decoder decodes the encoded data to a first code by using the first parity. The second decoder is connected to the first decoder. The second decoder is configured to decode the encoded data when the first decoder is deactivated and decode the first code using the second parity when the first decoder is deactivated. The controller transmits a control signal to the first decoder and the second decoder to control the first decoder and the second decoder.
摘要翻译：错误控制编码（ECC）电路包括第一解码器，第二解码器和控制器。第一解码器接收包括第一奇偶校验和第二奇偶校验的编码数据。第一解码器通过使用第一奇偶校验将编码数据解码为第一代码。第二解码器连接到第一解码器。第二解码器被配置为当第一解码器被去激活时解码编码数据，并且当第一解码器被去激活时使用第二奇偶校验解码第一代码。控制器向第一解码器和第二解码器发送控制信号以控制第一解码器和第二解码器。

7. 发明申请

US20100277979A1 MSB-BASED ERROR CORRECTION FOR FLASH MEMORY SYSTEM 有权
标题翻译：用于闪存存储器系统的基于MSB的错误校正
公开(公告)号：US20100277979A1
公开(公告)日：2010-11-04
申请号：US12836249
申请日：2010-07-14
申请人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
发明人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5642 , G06F11/1068 , G11C16/0483 , G11C16/26 , G11C16/3418 , G11C2029/0411
摘要： A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data from a selected memory cell and adjacent memory cells to the selected memory cell in response to a request for a read operation with respect to MSB data stored in the selected memory cell. A compare circuit is configured to compare data read from the adjacent memory cells to the selected memory cell provided from the multi-bit flash memory device and to correct data read from the selected memory cells based upon the comparison result.
摘要翻译：闪存系统包括具有存储单元阵列的多位闪存器件，该存储器单元阵列包括以行和列排列的存储器单元; 读取电路，被配置为从存储单元阵列读取数据; 以及控制逻辑，被配置为控制所述读取电路，以便响应于对存储在所选择的存储器单元中的MSB数据的读取操作的请求，连续地将数据从所选择的存储器单元和相邻存储器单元读取到所选择的存储器单元。比较电路被配置为将从相邻存储器单元读取的数据与从多位闪存器件提供的所选择的存储器单元进行比较，并且基于比较结果校正从所选存储器单元读取的数据。

8. 发明申请

US20080163023A1 ECC controller for use in flash memory device and memory system including the same 有权
标题翻译：用于闪存器件的ECC控制器和包括其的存储器系统
公开(公告)号：US20080163023A1
公开(公告)日：2008-07-03
申请号：US11785719
申请日：2007-04-19
申请人： Si-Hoon Hong , Yun-Tae Lee , Jun-Jin Kong
发明人： Si-Hoon Hong , Yun-Tae Lee , Jun-Jin Kong
IPC分类号： H03M13/00
CPC分类号： H03M13/2945 , G06F11/1072 , H03M13/09 , H03M13/136 , H03M13/1505 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/29 , H03M13/2906
摘要： An ECC (error correction code) controller of a flash memory device which stores an M-bit data (M being a positive integer equal to or greater than 2) comprises a first ECC block which generates a first ECC data from a program data to be stored in the flash memory device according to a first error correcting method and a second ECC block which generates a second ECC data from the first ECC data and the program data output from the first ECC block according to a second error correcting method, the program data, the first ECC data, and the second ECC data being stored in the flash memory device.
摘要翻译：存储M位数据（M为等于或大于2的正整数）的闪速存储器件的ECC（纠错码）控制器包括从程序数据生成第一ECC数据的第一ECC块，根据第一纠错方法存储在闪速存储装置中的第二ECC数据和根据第二纠错方法从第一ECC数据和从第一ECC块输出的程序数据生成第二ECC数据的第二ECC块，，第一ECC数据和第二ECC数据被存储在闪存设备中。

9. 发明申请

US20160299813A1 METHOD FOR OPERATING NON-VOLATILE MEMORY CONTROLLER 有权
标题翻译：操作非易失性存储器控制器的方法
公开(公告)号：US20160299813A1
公开(公告)日：2016-10-13
申请号：US15065915
申请日：2016-03-10
申请人： Chang-Kyu Seol , Jun-Jin Kong , Hye-Jeong So , Hong-Rak Son , Young-Geon Yoo , Dong-Whan Lee , Dong-Sup Jin
发明人： Chang-Kyu Seol , Jun-Jin Kong , Hye-Jeong So , Hong-Rak Son , Young-Geon Yoo , Dong-Whan Lee , Dong-Sup Jin
IPC分类号： G06F11/10 , G06F3/06 , G11C29/52
CPC分类号： G06F3/0679 , G06F3/0619 , G06F3/064 , G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C2029/0411
摘要： Provided are methods for operating a non-volatile memory controller. A method for operating a non-volatile memory controller includes dividing data provided from a host into first unit data and second unit data, encoding the first unit data into first codewords including n number of bits (n is an integer equal to or more than 1), encoding the second unit data into second codewords including n-w number of bits (w is an integer less than n and equal to or more than 1) corresponding to a bit having a value of 0 among the n number of bits of the first codewords, performing bit-to-state mapping on the first codewords and the second codewords using a predetermined bitmap, and programming the first codewords and the second codewords to a first page and a second page of a non-volatile memory, respectively.
摘要翻译：提供了用于操作非易失性存储器控制器的方法。用于操作非易失性存储器控制器的方法包括将从主机提供的数据划分为第一单元数据和第二单元数据，将第一单元数据编码为包括n个位数的第一码字（n是等于或大于1的整数）），将第二单位数据编码为第二码字，其包括与第一码字的n个比特中的具有值0的比特相对应的nw个比特数（w是小于n且等于或大于1的整数）使用预定位图对所述第一码字和所述第二码字执行比特到状态映射，以及将所述第一码字和所述第二码字分别编程到非易失性存储器的第一页和第二页。

10. 发明授权

US08830743B2 Method of operating memory controller, memory controller, memory device and memory system 有权
标题翻译：操作内存控制器，内存控制器，内存设备和内存系统的方法
公开(公告)号：US08830743B2
公开(公告)日：2014-09-09
申请号：US13445048
申请日：2012-04-12
申请人： Kyoung-Lae Cho , Jun-Jin Kong , Jae-Hong Kim
发明人： Kyoung-Lae Cho , Jun-Jin Kong , Jae-Hong Kim
IPC分类号： G11C16/04 , G11C29/56 , G11C11/56 , G11C16/34 , G11C29/12 , G11C29/44
CPC分类号： G11C11/5642 , G11C16/3418 , G11C29/44 , G11C29/56008 , G11C2029/1208 , G11C2029/4402
摘要： A method of operating a memory controller, a memory controller, a memory device and a memory system are provided. The method includes reading first data from a nonvolatile memory device using a first read voltage, the first data includes a uncorrectable error bit, reading second data from a nonvolatile memory device using a second read voltage different from the first read voltage, the second data includes an correctable error bit, and reprogramming the nonvolatile memory device according to the comparison result of the first read voltage and the second read voltage.
摘要翻译：提供了一种操作存储器控制器，存储器控制器，存储器件和存储器系统的方法。该方法包括使用第一读取电压从非易失性存储器件读取第一数据，第一数据包括不可校正的误差位，使用不同于第一读取电压的第二读取电压从非易失性存储器件读取第二数据，第二数据包括可校正错误位，并根据第一读取电压和第二读取电压的比较结果重新编程非易失性存储器件。

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