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1. 发明申请

US20090164710A1 SEMICONDUCTOR MEMORY SYSTEM AND ACCESS METHOD THEREOF 审中-公开
标题翻译：半导体存储器系统及其访问方法
公开(公告)号：US20090164710A1
公开(公告)日：2009-06-25
申请号：US12340846
申请日：2008-12-22
申请人： Jin-Hyeok Choi , Duck-Hyun Chang , Jun-Jin Kong , Dong-Hyuk Chae , Seung-Jae Lee , Dong-Ku Kang
发明人： Jin-Hyeok Choi , Duck-Hyun Chang , Jun-Jin Kong , Dong-Hyuk Chae , Seung-Jae Lee , Dong-Ku Kang
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G11C16/20 , G11C16/10
摘要： A semiconductor memory system and access method thereof. The semiconductor memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory stores monitoring data in one or more of plural memory cells. The memory controller controls the nonvolatile memory. The memory controller detects the monitoring data and adjusts a bias voltage, which is provided to the plural memory cells, in accordance with a result of the detection.
摘要翻译：半导体存储器系统及其访问方法。半导体存储器系统包括非易失性存储器和存储器控制器。非易失性存储器将监视数据存储在多个存储单元中的一个或多个中。存储器控制器控制非易失性存储器。存储器控制器根据检测结果检测监视数据并调整提供给多个存储单元的偏置电压。

2. 发明申请

US20100277979A1 MSB-BASED ERROR CORRECTION FOR FLASH MEMORY SYSTEM 有权
标题翻译：用于闪存存储器系统的基于MSB的错误校正
公开(公告)号：US20100277979A1
公开(公告)日：2010-11-04
申请号：US12836249
申请日：2010-07-14
申请人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
发明人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5642 , G06F11/1068 , G11C16/0483 , G11C16/26 , G11C16/3418 , G11C2029/0411
摘要： A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data from a selected memory cell and adjacent memory cells to the selected memory cell in response to a request for a read operation with respect to MSB data stored in the selected memory cell. A compare circuit is configured to compare data read from the adjacent memory cells to the selected memory cell provided from the multi-bit flash memory device and to correct data read from the selected memory cells based upon the comparison result.
摘要翻译：闪存系统包括具有存储单元阵列的多位闪存器件，该存储器单元阵列包括以行和列排列的存储器单元; 读取电路，被配置为从存储单元阵列读取数据; 以及控制逻辑，被配置为控制所述读取电路，以便响应于对存储在所选择的存储器单元中的MSB数据的读取操作的请求，连续地将数据从所选择的存储器单元和相邻存储器单元读取到所选择的存储器单元。比较电路被配置为将从相邻存储器单元读取的数据与从多位闪存器件提供的所选择的存储器单元进行比较，并且基于比较结果校正从所选存储器单元读取的数据。

3. 发明授权

US07791938B2 MSB-based error correction for flash memory system 有权
标题翻译：基于MSB的闪存系统的纠错
公开(公告)号：US07791938B2
公开(公告)日：2010-09-07
申请号：US12169109
申请日：2008-07-08
申请人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
发明人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5642 , G06F11/1068 , G11C16/0483 , G11C16/26 , G11C16/3418 , G11C2029/0411
摘要： A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data from a selected memory cell and adjacent memory cells to the selected memory cell in response to a request for a read operation with respect to MSB data stored in the selected memory cell. A compare circuit is configured to compare data read from the adjacent memory cells to the selected memory cell provided from the multi-bit flash memory device and to correct data read from the selected memory cells based upon the comparison result.
摘要翻译：闪存系统包括具有存储单元阵列的多位闪存器件，该存储器单元阵列包括以行和列排列的存储器单元; 读取电路，被配置为从存储单元阵列读取数据; 以及控制逻辑，被配置为控制所述读取电路，以便响应于对存储在所选择的存储器单元中的MSB数据的读取操作的请求，连续地将数据从所选择的存储器单元和相邻存储器单元读取到所选择的存储器单元。比较电路被配置为将从相邻存储器单元读取的数据与从多位闪存器件提供的所选择的存储器单元进行比较，并且基于比较结果校正从所选存储器单元读取的数据。

4. 发明授权

US08208298B2 MSB-based error correction for flash memory system 有权
标题翻译：基于MSB的闪存系统的纠错
公开(公告)号：US08208298B2
公开(公告)日：2012-06-26
申请号：US12836249
申请日：2010-07-14
申请人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
发明人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5642 , G06F11/1068 , G11C16/0483 , G11C16/26 , G11C16/3418 , G11C2029/0411
摘要： A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data from a selected memory cell and adjacent memory cells to the selected memory cell in response to a request for a read operation with respect to MSB data stored in the selected memory cell. A compare circuit is configured to compare data read from the adjacent memory cells to the selected memory cell provided from the multi-bit flash memory device and to correct data read from the selected memory cells based upon the comparison result.
摘要翻译：闪存系统包括具有存储单元阵列的多位闪存器件，该存储器单元阵列包括以行和列排列的存储器单元; 读取电路，被配置为从存储单元阵列读取数据; 以及控制逻辑，被配置为控制所述读取电路，以便响应于对存储在所选择的存储器单元中的MSB数据的读取操作的请求，连续地将数据从所选择的存储器单元和相邻存储器单元读取到所选择的存储器单元。比较电路被配置为将从相邻存储器单元读取的数据与从多位闪存器件提供的所选择的存储器单元进行比较，并且基于比较结果校正从所选存储器单元读取的数据。

5. 发明授权

US07898853B2 Multi-bit data memory system and read operation 有权
标题翻译：多位数据存储系统和读操作
公开(公告)号：US07898853B2
公开(公告)日：2011-03-01
申请号：US12204860
申请日：2008-09-05
申请人： Seung-Jae Lee , Dong-Ku Kang , Seung-Hwan Song , Jun-Jin Kong , Dong-Hyuk Chae , Sung-Chung Park
发明人： Seung-Jae Lee , Dong-Ku Kang , Seung-Hwan Song , Jun-Jin Kong , Dong-Hyuk Chae , Sung-Chung Park
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C16/3418
摘要： Provided is a read operation for a N-bit data non-volatile memory system. The method includes determining in relation to data states of adjacent memory cells associated with a selected memory cell in the plurality of memory cells whether read data obtained from the selected memory cell requires compensation, and if the read data requires compensation, replacing the read data with compensated read data.
摘要翻译：提供了一种用于N位数据非易失性存储器系统的读取操作。该方法包括：确定与多个存储器单元中的所选存储单元相关联的相邻存储器单元的数据状态，从所选择的存储器单元获得的读取数据是否需要补偿，以及如果读取的数据需要补偿，则用补偿读数据。

6. 发明申请

US20090016103A1 MSB-BASED ERROR CORRECTION FOR FLASH MEMORY SYSTEM 有权
标题翻译：用于闪存存储器系统的基于MSB的错误校正
公开(公告)号：US20090016103A1
公开(公告)日：2009-01-15
申请号：US12169109
申请日：2008-07-08
申请人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
发明人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5642 , G06F11/1068 , G11C16/0483 , G11C16/26 , G11C16/3418 , G11C2029/0411
摘要： A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data from a selected memory cell and adjacent memory cells to the selected memory cell in response to a request for a read operation with respect to MSB data stored in the selected memory cell. A compare circuit is configured to compare data read from the adjacent memory cells to the selected memory cell provided from the multi-bit flash memory device and to correct data read from the selected memory cells based upon the comparison result.
摘要翻译：闪存系统包括具有存储单元阵列的多位闪存器件，该存储器单元阵列包括以行和列排列的存储器单元; 读取电路，被配置为从存储单元阵列读取数据; 以及控制逻辑，被配置为控制所述读取电路，以便响应于对存储在所选择的存储器单元中的MSB数据的读取操作的请求，连续地将数据从所选择的存储器单元和相邻存储器单元读取到所选择的存储器单元。比较电路被配置为将从相邻存储器单元读取的数据与从多位闪存器件提供的所选择的存储器单元进行比较，并且基于比较结果校正从所选存储器单元读取的数据。

7. 发明授权

US07876614B2 Multi-bit flash memory device and program and read methods thereof 有权
标题翻译：多位闪存设备及其程序和读取方法
公开(公告)号：US07876614B2
公开(公告)日：2011-01-25
申请号：US12255211
申请日：2008-10-21
申请人： Dong-Ku Kang , Dong-Hyuk Chae , Seung-Jae Lee
发明人： Dong-Ku Kang , Dong-Hyuk Chae , Seung-Jae Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C2211/5646
摘要： The flash memory device of the present invention is configured to program a plurality of bits per unit cell, wherein a program condition of a selected bit is set according to whether a program for the most previous bit to the selected bit for programming is skipped or not skipped. As a result, an accurate programming and reading operation is possible even in case a program for a middle bit is skipped.
摘要翻译：本发明的闪速存储器件被配置为对每个单位单元的多个位进行编程，其中根据用于编程的选择位的最前一位的程序是否被跳过来设置所选位的程序状态跳过因此，即使在中间位的程序被跳过的情况下也可以进行准确的编程和读取操作。

8. 发明授权

US07545677B2 Nonvolatile memory device and methods of programming and reading the same 有权
标题翻译：非易失性存储器件和编程和读取方法
公开(公告)号：US07545677B2
公开(公告)日：2009-06-09
申请号：US12136150
申请日：2008-06-10
申请人： Seung-Jae Lee , Dong-Hyuk Chae , Dong-Ku Kang
发明人： Seung-Jae Lee , Dong-Hyuk Chae , Dong-Ku Kang
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/26 , G11C2216/14
摘要： A read method of a non-volatile memory device includes reading an initial threshold voltage value of an index cell from threshold voltage information cells that store information indicating the initial threshold voltage, determining a current threshold voltage value from the index cell, and comparing the initial threshold voltage value and the current threshold voltage value to calculate a shifted threshold voltage level of the index cell. A read voltage is changed by the shifted threshold voltage level to read user data using the changed read voltage.
摘要翻译：非易失性存储器件的读取方法包括从存储指示初始阈值电压的信息的阈值电压信息单元读取索引单元的初始阈值电压值，从索引单元确定当前阈值电压值，以及比较初始值阈值电压值和电流阈值电压值，以计算索引单元的偏移阈值电压电平。读取电压由偏移的阈值电压电平改变，以便使用改变的读取电压来读取用户数据。

9. 发明申请

US20090103360A1 Multi-Bit Flash Memory Device and Program and Read Methods Thereof 有权
标题翻译：多位闪存设备及其编程和读取方法
公开(公告)号：US20090103360A1
公开(公告)日：2009-04-23
申请号：US12255211
申请日：2008-10-21
申请人： Dong Ku Kang , Dong-Hyuk Chae , Seung-Jae Lee
发明人： Dong Ku Kang , Dong-Hyuk Chae , Seung-Jae Lee
IPC分类号： G11C16/06 , G11C16/00
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C2211/5646
摘要： The flash memory device of the present invention is configured to program a plurality of bits per unit cell, wherein a program condition of a selected bit is set according to whether a program for the most previous bit to the selected bit for programming is skipped or not skipped. As a result, an accurate programming and reading operation is possible even in case a program for a middle bit is skipped.
摘要翻译：本发明的闪速存储器件被配置为对每个单位单元的多个位进行编程，其中根据用于编程的选择位的最前一位的程序是否被跳过来设置所选位的程序状态跳过因此，即使在中间位的程序被跳过的情况下也可以进行准确的编程和读取操作。

10. 发明授权

US08835020B2 Blue fluorescent composition and organic electroluminescent device using the same 有权
标题翻译：蓝色荧光组合物和使用其的有机电致发光器件
公开(公告)号：US08835020B2
公开(公告)日：2014-09-16
申请号：US12591796
申请日：2009-12-01
申请人： Seung-Jae Lee , In-Bum Song , Jung-Keun Kim , Do-Han Kim , Chun-Gun Park , Hyoung-Yun Oh , Jong-Kwan Bin , Kyung-Hoon Lee , Hyun-Cheol Jeong , Dong-Hee Yoo , Nam-Sung Cho , Jong-Hyun Park , In-Sun Yoo , Tae-Han Park , Soon-Wook Cha
发明人： Seung-Jae Lee , In-Bum Song , Jung-Keun Kim , Do-Han Kim , Chun-Gun Park , Hyoung-Yun Oh , Jong-Kwan Bin , Kyung-Hoon Lee , Hyun-Cheol Jeong , Dong-Hee Yoo , Nam-Sung Cho , Jong-Hyun Park , In-Sun Yoo , Tae-Han Park , Soon-Wook Cha
IPC分类号： H01L51/54 , C09K11/06 , H01L51/00 , H05B33/14 , C07C211/61 , C07C255/58 , H01L51/50
CPC分类号： C09K11/06 , C07C211/61 , C07C255/58 , C07C2603/50 , C09K2211/1011 , C09K2211/1014 , H01L51/0054 , H01L51/0058 , H01L51/006 , H01L51/5012 , H05B33/14 , Y10S428/917
摘要： A blue fluorescent compound includes a host material being capable of transporting an electron or a hole; and a dopant material represented by following Formula 1: wherein at least two of the R1, the R2, the R3, and the R4 are selected from substituted or non-substituted aromatic group or substituted or non-substituted heterocyclic group, and the R5 is selected from substituted or non-substituted aromatic group or substituted or non-substituted heterocyclic group.
摘要翻译：蓝色荧光化合物包括能够输送电子或孔的主体材料; 和由下式1表示的掺杂剂材料：其中R1，R2，R3和R4中的至少两个选自取代或未取代的芳族基团或取代或未取代的杂环基，R5是选自取代或未取代的芳族基团或取代或未取代的杂环基团。

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