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1. 发明申请

US20130060985A1 DEVICE CAPABLE OF ADOPTING AN EXTERNAL MEMORY 有权
标题翻译：能够采用外部存储器的设备
公开(公告)号：US20130060985A1
公开(公告)日：2013-03-07
申请号：US13606551
申请日：2012-09-07
申请人： Hak-Soo Yu , Jun-Jin Kong , Hyoung-Joon Kim , Joo-Young Hwang , In-Su Choi
发明人： Hak-Soo Yu , Jun-Jin Kong , Hyoung-Joon Kim , Joo-Young Hwang , In-Su Choi
IPC分类号： G06F13/16
CPC分类号： G06F13/16 , G06F13/1694 , G06F13/385
摘要： A device includes a memory controller, a memory bus coupled to the memory controller, an internal memory and an external memory connection unit. The internal memory may be directly connected to the memory controller through the memory bus. The external memory connection unit may connect an external memory directly to the memory controller through a portion of signal lines in the memory bus, and may generate a flag signal indicating whether the external memory is connected to the external memory connection unit.
摘要翻译：设备包括存储器控制器，耦合到存储器控制器的存储器总线，内部存储器和外部存储器连接单元。内部存储器可以通过存储器总线直接连接到存储器控制器。外部存储器连接单元可以通过存储器总线中的一部分信号线将外部存储器直接连接到存储器控制器，并且可以产生指示外部存储器是否连接到外部存储器连接单元的标志信号。

2. 发明授权

US09069714B2 Device including an external memory connection unit capable of adopting an external memory 有权
标题翻译：装置包括能够采用外部存储器的外部存储器连接单元
公开(公告)号：US09069714B2
公开(公告)日：2015-06-30
申请号：US13606551
申请日：2012-09-07
申请人： Hak-Soo Yu , Jun-Jin Kong , Hyoung-Joon Kim , Joo-Young Hwang , In-Su Choi
发明人： Hak-Soo Yu , Jun-Jin Kong , Hyoung-Joon Kim , Joo-Young Hwang , In-Su Choi
IPC分类号： G06F13/14 , G06F13/16 , G06F13/38
CPC分类号： G06F13/16 , G06F13/1694 , G06F13/385
摘要： A device includes a memory controller, a memory bus coupled to the memory controller, an internal memory and an external memory connection unit. The internal memory may be directly connected to the memory controller through the memory bus. The external memory connection unit may connect an external memory directly to the memory controller through a portion of signal lines in the memory bus, and may generate a flag signal indicating whether the external memory is connected to the external memory connection unit.
摘要翻译：设备包括存储器控制器，耦合到存储器控制器的存储器总线，内部存储器和外部存储器连接单元。内部存储器可以通过存储器总线直接连接到存储器控制器。外部存储器连接单元可以通过存储器总线中的一部分信号线将外部存储器直接连接到存储器控制器，并且可以产生指示外部存储器是否连接到外部存储器连接单元的标志信号。

3. 发明授权

US09058897B2 Semiconductor memory device storing memory characteristic information, memory module and memory system having the same, and operating method thereof 有权
标题翻译：存储存储器特性信息的半导体存储器件，具有该存储器特性信息的存储器模块和存储器系统及其操作方法
公开(公告)号：US09058897B2
公开(公告)日：2015-06-16
申请号：US13670065
申请日：2012-11-06
申请人： Hak-Soo Yu , Joo-Sun Choi , Hong-Sun Hwan
发明人： Hak-Soo Yu , Joo-Sun Choi , Hong-Sun Hwan
IPC分类号： G11C5/02 , G11C11/4063 , G11C14/00 , G11C16/06 , G11C11/406
CPC分类号： G11C11/4063 , G11C11/406 , G11C14/00 , G11C14/0018 , G11C16/06 , G11C29/783 , G11C2211/4061
摘要： A semiconductor memory device includes a cell array including a plurality of regions accessed by first addresses, where the plurality of regions including at least two groups of regions having respectively different memory characteristics. The device further includes a nonvolatile array for nonvolatile storage of group information indicative of which of the least two groups each of the plurality of regions belongs.
摘要翻译：半导体存储器件包括一个单元阵列，该单元阵列包括由第一地址访问的多个区域，其中多个区域包括具有不同存储特性的至少两组区域。该装置还包括用于非易失性存储指示多个区域中的至少两个组中的哪一个属于哪个组的非易失性阵列。

4. 发明申请

US20120087177A1 SEMICONDUCTOR MEMORY DEVICE FOR DATA SENSING 有权
标题翻译：用于数据传感的半导体存储器件
公开(公告)号：US20120087177A1
公开(公告)日：2012-04-12
申请号：US13238553
申请日：2011-09-21
申请人： Sua KIM , Chul-Woo Park , Hong-Sun Hwang , Hak-Soo Yu
发明人： Sua KIM , Chul-Woo Park , Hong-Sun Hwang , Hak-Soo Yu
IPC分类号： G11C11/24
CPC分类号： G11C11/4091 , G11C11/4099
摘要： A semiconductor memory device includes a memory cell and a first reference memory cell. The memory cell includes a first switching element and a first capacitor for storing data. The first switching element is controlled by a first wordline, and has a first terminal connected to a first terminal of the first capacitor and a second terminal connected to a first bitline. The first capacitor has a second terminal for receiving a first plate voltage. The first reference memory cell includes a first reference switching element and a first capacitor. The first switching element is controlled by a first reference wordline, and has a first terminal connected to a first terminal of the first reference capacitor and a second terminal connected to a second bitline. The first reference capacitor has a second terminal receiving a first reference plate voltage different from the first plate voltage.
摘要翻译：半导体存储器件包括存储单元和第一参考存储单元。存储单元包括第一开关元件和用于存储数据的第一电容器。第一开关元件由第一字线控制，并且具有连接到第一电容器的第一端子的第一端子和连接到第一位线的第二端子。第一电容器具有用于接收第一板电压的第二端子。第一参考存储单元包括第一参考开关元件和第一电容器。第一开关元件由第一参考字线控制，并且具有连接到第一参考电容器的第一端子的第一端子和连接到第二位线的第二端子。第一参考电容器具有接收与第一板电压不同的第一参考板电压的第二端子。

5. 发明授权

US06366149B1 Delay circuit having variable slope control and threshold detect 有权
标题翻译：具有可变斜率控制和阈值检测的延迟电路
公开(公告)号：US06366149B1
公开(公告)日：2002-04-02
申请号：US09649389
申请日：2000-08-28
申请人： Jong-Cheol Lee , Hak-Soo Yu
发明人： Jong-Cheol Lee , Hak-Soo Yu
IPC分类号： H03H1126
CPC分类号： H03K5/13
摘要： A delay circuit in accordance with the present invention provides high-resolution changes in the time delay by utilizing a slope controller that generates an intermediate signal having sloping edges in response to edges in an input signal. A delay time controller generates an output signal having edges that begin when the level of the intermediate signal reaches a certain level. The overall time delay of the delay circuit can be varied by varying the slope of the edges of the intermediate signal, or by varying the level of the intermediate signal at which the delay time controller begins generating an edge in the output signal, or by varying both parameters. The slope controller and delay time controller can be realized with a plurality of tri-state inverters coupled in parallel for operating responsive to one or more select signals. By implementing the inverters with pull-up and pull-down transistors having different sizes, the overall time delay can be varied with very high resolution.
摘要翻译：根据本发明的延迟电路通过利用产生具有响应于输入信号中的边缘的倾斜边缘的中间信号的斜率控制器来提供时间延迟中的高分辨率变化。延迟时间控制器产生具有当中间信号的电平达到一定水平时开始的边沿的输出信号。可以通过改变中间信号的边沿的斜率，或通过改变延迟时间控制器开始在输出信号中产生边沿的中间信号的电平，或者通过改变延迟电路的整个时间延迟两个参数。斜率控制器和延迟时间控制器可以通过多个并联耦合的三态反相器来实现，以响应于一个或多个选择信号进行操作。通过用具有不同尺寸的上拉和下拉晶体管实现逆变器，总体时间延迟可以以非常高的分辨率变化。

6. 发明授权

US06304495B1 Logic interface circuit and semiconductor memory device using this circuit 有权
标题翻译：逻辑接口电路和使用该电路的半导体存储器件
公开(公告)号：US06304495B1
公开(公告)日：2001-10-16
申请号：US09576936
申请日：2000-05-22
申请人： Suk-San Kim , Hak-Soo Yu
发明人： Suk-San Kim , Hak-Soo Yu
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C7/1048
摘要： A logic interface circuit and a semiconductor memory device to which the logic interface circuit is applied, the circuit comprising: logic gate means having pull up means and pull down means which respectively responds to one or more input signals to pull up and pull down an output terminal; reverse current preventing means connected between a first supply voltage and the pull up means for preventing current from reversing from the pull up means to the first supply voltage; pre-charging means connected in parallel to the reverse current preventing means for responding to the output signal generated from the output terminal to pre-charge a common point of the reverse current preventing means and the pull up means to the first supply voltage; and reverse current preventing and voltage boosting means connected between the second supply voltage and the output terminal for responding to the first supply voltage to turn off to prevent current from reversing from the output terminal to the second supply voltage if the first supply voltage is higher than the second supply voltage, and for responding to one or more input signals to turn on to set up the output terminal to the second supply voltage if the first supply voltage is lower than the second supply voltage, thereby enabling to shift levels of the supply voltage by adding a simple circuit to logic gates like inverter, NAND gate or NOR gate.
摘要翻译：逻辑接口电路和应用逻辑接口电路的半导体存储器件，该电路包括：具有上拉装置和下拉装置的逻辑门装置，其分别响应于一个或多个输入信号以上拉和下拉输出终奌站; 连接在第一电源电压和上拉装置之间的反向电流防止装置，用于防止电流从上拉装置反转到第一电源电压; 预充电装置并联连接到反向电流防止装置，用于响应从输出端产生的输出信号，以将反向电流防止装置和上拉装置的公共点预充电到第一电源电压; 以及连接在所述第二电源电压和所述输出端子之间的反向电流防止和升压装置，用于响应于所述第一电源电压以关闭以防止电流从所述输出端子反转到所述第二电源电压，如果所述第一电源电压高于第二电源电压，并且如果第一电源电压低于第二电源电压，则响应于一个或多个输入信号而导通以将输出端子设置为第二电源电压，从而使电源电压的电平通过向逻辑门添加一个简单的电路，如反相器，NAND门或NOR门。

7. 发明授权

US6147913A Data transmission circuitry of a synchronous semiconductor memory device 有权
标题翻译：同步半导体存储器件的数据传输电路
公开(公告)号：US6147913A
公开(公告)日：2000-11-14
申请号：US513621
申请日：2000-02-25
申请人： Hak-Soo Yu , Su-Chul Kim
发明人： Hak-Soo Yu , Su-Chul Kim
IPC分类号： G11C11/413 , G11C7/10 , G11C7/22 , G11C11/407 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C11/417 , G11C7/00
CPC分类号： G11C11/4093 , G11C11/4076 , G11C11/4096 , G11C7/1006 , G11C7/1072 , G11C7/22
摘要： A synchronous memory comprises a memory cell array having a plurality of memory cells; a clock control circuit for receiving a first clock signal, a second clock signal, and a third clock signal, and for generating an internal clock signal, a plurality of control signals, and a plurality of flag signals. The memory includes a first register circuit for storing a plurality of input data bits in response to the internal clock signal and to the control signals; a second register circuit for storing the flag signals in response to the internal clock signal and the control signals; a write drive circuit for writing the input data bits passing through the first register circuit into the memory cell array in response to the flag signals during a write cycle; a sense amplifier circuit coupled to the memory cell array, an address comparator circuit for receiving read and write address signals and for generating a first, a second, and a third combination signals; and a switching circuit for transferring the input data bits passing through the first register circuit and the flag signals passing through the second register circuit to output terminals of the device.
摘要翻译：同步存储器包括具有多个存储器单元的存储单元阵列; 时钟控制电路，用于接收第一时钟信号，第二时钟信号和第三时钟信号，并用于产生内部时钟信号，多个控制信号和多个标志信号。存储器包括用于响应于内部时钟信号和控制信号而存储多个输入数据位的第一寄存器电路; 第二寄存器电路，用于响应于内部时钟信号和控制信号而存储标志信号; 写入驱动电路，用于在写入周期期间响应于标志信号，将通过第一寄存器电路的输入数据位写入存储单元阵列; 耦合到存储单元阵列的读出放大器电路，用于接收读和写地址信号并用于产生第一，第二和第三组合信号的地址比较器电路; 以及用于将通过第一寄存器电路的输入数据位和通过第二寄存器电路的标志信号传送到器件的输出端的开关电路。

8. 发明授权

US09268636B2 Semiconductor memory devices including error correction circuits and methods of operating the semiconductor memory devices 有权
标题翻译：半导体存储器件包括纠错电路和操作半导体存储器件的方法
公开(公告)号：US09268636B2
公开(公告)日：2016-02-23
申请号：US13910591
申请日：2013-06-05
申请人： Hoi-ju Chung , Su-A Kim , Mu-Jin Seo , Hak-Soo Yu , Jae-Youn Youn , Hyo-Jin Choi
发明人： Hoi-ju Chung , Su-A Kim , Mu-Jin Seo , Hak-Soo Yu , Jae-Youn Youn , Hyo-Jin Choi
IPC分类号： G11C29/00 , G06F11/10
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0679 , G06F11/073 , G06F11/076 , G06F11/079 , G06F11/0793 , G06F11/1008 , G06F11/1048 , G06F11/1068 , G06F11/1076 , G11C11/409 , G11C29/52 , G11C29/783
摘要： A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.
摘要翻译：存储器控制器包括：控制器输入/输出电路，被配置为输出第一命令以读取第一数据，并输出第二命令以读取第一数据的纠错部分。存储装置包括：误差检测器，数据存储电路和纠错电路。错误检测器被配置为响应于第一命令来检测从存储器单元读取的数据中的错误位数。如果检测到的错误比特数大于或等于第一阈值，则数据存储电路被配置为存储读取数据。误差校正电路被配置为校正存储的数据。

9. 发明授权

US08553484B2 Semiconductor memory device for data sensing 有权
标题翻译：用于数据传感的半导体存储器件
公开(公告)号：US08553484B2
公开(公告)日：2013-10-08
申请号：US13238553
申请日：2011-09-21
申请人： Sua Kim , Chul-Woo Park , Hong-Sun Hwang , Hak-Soo Yu
发明人： Sua Kim , Chul-Woo Park , Hong-Sun Hwang , Hak-Soo Yu
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C11/4099
摘要： A semiconductor memory device includes a memory cell and a first reference memory cell. The memory cell includes a first switching element and a first capacitor for storing data. The first switching element is controlled by a first wordline, and has a first terminal connected to a first terminal of the first capacitor and a second terminal connected to a first bitline. The first capacitor has a second terminal for receiving a first plate voltage. The first reference memory cell includes a first reference switching element and a first capacitor. The first switching element is controlled by a first reference wordline, and has a first terminal connected to a first terminal of the first reference capacitor and a second terminal connected to a second bitline. The first reference capacitor has a second terminal receiving a first reference plate voltage different from the first plate voltage.
摘要翻译：半导体存储器件包括存储单元和第一参考存储单元。存储单元包括第一开关元件和用于存储数据的第一电容器。第一开关元件由第一字线控制，并且具有连接到第一电容器的第一端子的第一端子和连接到第一位线的第二端子。第一电容器具有用于接收第一板电压的第二端子。第一参考存储单元包括第一参考开关元件和第一电容器。第一开关元件由第一参考字线控制，并且具有连接到第一参考电容器的第一端子的第一端子和连接到第二位线的第二端子。第一参考电容器具有接收与第一板电压不同的第一参考板电压的第二端子。

10. 发明授权

US08547766B2 Area-efficient data line layouts to suppress the degradation of electrical characteristics 有权
标题翻译：区域高效的数据线布局，以抑制电气特性的恶化
公开(公告)号：US08547766B2
公开(公告)日：2013-10-01
申请号：US12659883
申请日：2010-03-24
申请人： Jong-Hak Won , Hyang-Ja Yang , Choong-Sun Shin , Hak-Soo Yu , Young-Soo An , Jung-Hyeon Kim
发明人： Jong-Hak Won , Hyang-Ja Yang , Choong-Sun Shin , Hak-Soo Yu , Young-Soo An , Jung-Hyeon Kim
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , G11C11/4097
摘要： A data line layout includes column selection lines arranged in a first direction at a layer on a memory cell array region, and data lines arranged in the first direction at the layer, the data lines being connected between I/O sense amplifiers and I/O pads.
摘要翻译：数据线布局包括在存储单元阵列区域上的层上沿着第一方向布置的列选择线以及沿着该层的第一方向布置的数据线，数据线连接在I / O读出放大器和I / O之间垫

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