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1. 发明授权

US08830743B2 Method of operating memory controller, memory controller, memory device and memory system 有权
标题翻译：操作内存控制器，内存控制器，内存设备和内存系统的方法
公开(公告)号：US08830743B2
公开(公告)日：2014-09-09
申请号：US13445048
申请日：2012-04-12
申请人： Kyoung-Lae Cho , Jun-Jin Kong , Jae-Hong Kim
发明人： Kyoung-Lae Cho , Jun-Jin Kong , Jae-Hong Kim
IPC分类号： G11C16/04 , G11C29/56 , G11C11/56 , G11C16/34 , G11C29/12 , G11C29/44
CPC分类号： G11C11/5642 , G11C16/3418 , G11C29/44 , G11C29/56008 , G11C2029/1208 , G11C2029/4402
摘要： A method of operating a memory controller, a memory controller, a memory device and a memory system are provided. The method includes reading first data from a nonvolatile memory device using a first read voltage, the first data includes a uncorrectable error bit, reading second data from a nonvolatile memory device using a second read voltage different from the first read voltage, the second data includes an correctable error bit, and reprogramming the nonvolatile memory device according to the comparison result of the first read voltage and the second read voltage.
摘要翻译：提供了一种操作存储器控制器，存储器控制器，存储器件和存储器系统的方法。该方法包括使用第一读取电压从非易失性存储器件读取第一数据，第一数据包括不可校正的误差位，使用不同于第一读取电压的第二读取电压从非易失性存储器件读取第二数据，第二数据包括可校正错误位，并根据第一读取电压和第二读取电压的比较结果重新编程非易失性存储器件。

2. 发明授权

US08274840B2 Nonvolatile memory devices having built-in memory cell recovery during block erase and methods of operating same 有权
标题翻译：在块擦除期间具有内置存储器单元恢复的非易失性存储器件及其操作方法
公开(公告)号：US08274840B2
公开(公告)日：2012-09-25
申请号：US12498508
申请日：2009-07-07
申请人： Yong-June Kim , Jae-Hong Kim , Kyoung-Lae Cho , Seung-Hwan Song , Jun-Jin Kong
发明人： Yong-June Kim , Jae-Hong Kim , Kyoung-Lae Cho , Seung-Hwan Song , Jun-Jin Kong
IPC分类号： G11C11/34
CPC分类号： G11C16/16
摘要： Nonvolatile memory devices include support memory cell recovery during operations to erase blocks of nonvolatile (e.g., flash) memory cells. A nonvolatile memory system includes a flash memory device and a memory controller electrically coupled to the flash memory device. The memory controller is configured to control memory cell recovery operations within the flash memory device by issuing a first instruction(s) to the flash memory device that causes erased memory cells in the block of memory to become at least partially programmed memory cells and then issuing a second instruction(s) to the flash memory device that causes the at least partially programmed memory cells become fully erased.
摘要翻译：非易失性存储器件包括在擦除非易失性（例如闪存）存储器单元块的操作期间的支持存储器单元恢复。非易失性存储器系统包括闪存器件和电耦合到闪速存储器件的存储器控制器。存储器控制器被配置为通过向闪存器件发出第一指令来控制闪存器件内的存储器单元恢复操作，该第一指令使存储器块中的擦除存储器单元变成至少部分被编程的存储器单元，然后发出使闪存器件的至少部分编程的存储器单元完全被擦除的第二指令。

3. 发明申请

US20100091578A1 Nonvolatile Memory Devices Having Built-in Memory Cell Recovery During Block Erase and Methods of Operating Same 有权
标题翻译：在块擦除期间具有内置存储器单元恢复的非易失性存储器件和操作方法相同
公开(公告)号：US20100091578A1
公开(公告)日：2010-04-15
申请号：US12498508
申请日：2009-07-07
申请人： Yong-June Kim , Jae-Hong Kim , Kyoung-Lae Cho , Seung-Hwan Song , Jun-Jin Kong
发明人： Yong-June Kim , Jae-Hong Kim , Kyoung-Lae Cho , Seung-Hwan Song , Jun-Jin Kong
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/16
摘要： Nonvolatile memory devices include support memory cell recovery during operations to erase blocks of nonvolatile (e.g., flash) memory cells. A nonvolatile memory system includes a flash memory device and a memory controller electrically coupled to the flash memory device. The memory controller is configured to control memory cell recovery operations within the flash memory device by issuing a first instruction(s) to the flash memory device that causes erased memory cells in the block of memory to become at least partially programmed memory cells and then issuing a second instruction(s) to the flash memory device that causes the at least partially programmed memory cells become fully erased.
摘要翻译：非易失性存储器件包括在擦除非易失性（例如闪存）存储器单元块的操作期间的支持存储器单元恢复。非易失性存储器系统包括闪存器件和电耦合到闪速存储器件的存储器控制器。存储器控制器被配置为通过向闪存器件发出第一指令来控制闪存器件内的存储器单元恢复操作，该第一指令使存储器块中的擦除存储器单元变成至少部分被编程的存储器单元，然后发出使闪存器件的至少部分编程的存储器单元完全被擦除的第二指令。

4. 发明申请

US20120265927A1 METHOD OF OPERATING MEMORY CONTROLLER, MEMORY CONTROLLER, MEMORY DEVICE AND MEMORY SYSTEM 有权
标题翻译：操作存储器控制器，存储器控制器，存储器件和存储器系统的方法
公开(公告)号：US20120265927A1
公开(公告)日：2012-10-18
申请号：US13445048
申请日：2012-04-12
申请人： Kyoung-Lae Cho , Jun-Jin Kong , Jae-Hong Kim
发明人： Kyoung-Lae Cho , Jun-Jin Kong , Jae-Hong Kim
IPC分类号： G06F12/00
CPC分类号： G11C11/5642 , G11C16/3418 , G11C29/44 , G11C29/56008 , G11C2029/1208 , G11C2029/4402
摘要： A method of operating a memory controller, a memory controller, a memory device and a memory system are provided. The method includes reading first data from a nonvolatile memory device using a first read voltage, the first data includes a uncorrectable error bit, reading second data from a nonvolatile memory device using a second read voltage different from the first read voltage, the second data includes an correctable error bit, and reprogramming the nonvolatile memory device according to the comparison result of the first read voltage and the second read voltage.
摘要翻译：提供了一种操作存储器控制器，存储器控制器，存储器件和存储器系统的方法。该方法包括使用第一读取电压从非易失性存储器件读取第一数据，第一数据包括不可校正的误差位，使用不同于第一读取电压的第二读取电压从非易失性存储器件读取第二数据，第二数据包括可校正错误位，并根据第一读取电压和第二读取电压的比较结果重新编程非易失性存储器件。

5. 发明授权

US08522124B2 Semiconductor device and decoding method thereof 有权
标题翻译：半导体器件及其解码方法
公开(公告)号：US08522124B2
公开(公告)日：2013-08-27
申请号：US13069834
申请日：2011-03-23
申请人： Yong-June Kim , Jun-Jin Kong , Young-Hwan Lee , Jae-Hong Kim
发明人： Yong-June Kim , Jun-Jin Kong , Young-Hwan Lee , Jae-Hong Kim
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： G06F11/1048
摘要： An error control coding (ECC) circuit includes a first decoder, a second decoder, and a controller. The first decoder receives encoded data comprising a first parity and a second parity. The first decoder decodes the encoded data to a first code by using the first parity. The second decoder is connected to the first decoder. The second decoder is configured to decode the encoded data when the first decoder is deactivated and decode the first code using the second parity when the first decoder is deactivated. The controller transmits a control signal to the first decoder and the second decoder to control the first decoder and the second decoder.
摘要翻译：错误控制编码（ECC）电路包括第一解码器，第二解码器和控制器。第一解码器接收包括第一奇偶校验和第二奇偶校验的编码数据。第一解码器通过使用第一奇偶校验将编码数据解码为第一代码。第二解码器连接到第一解码器。第二解码器被配置为当第一解码器被去激活时解码编码数据，并且当第一解码器被去激活时使用第二奇偶校验解码第一代码。控制器向第一解码器和第二解码器发送控制信号以控制第一解码器和第二解码器。

6. 发明授权

US08689082B2 Method of operating memory controller, and memory system, memory card and portable electronic device including the memory controller 有权
标题翻译：操作存储器控制器，存储器系统，存储卡和包括存储器控制器的便携式电子设备的方法
公开(公告)号：US08689082B2
公开(公告)日：2014-04-01
申请号：US13550133
申请日：2012-07-16
申请人： Eun-Chu Oh , Jae-Hong Kim , Yong-June Kim , Jun-Jin Kong
发明人： Eun-Chu Oh , Jae-Hong Kim , Yong-June Kim , Jun-Jin Kong
IPC分类号： H03M13/00
CPC分类号： G11C16/3418 , G06F11/1048 , G06F12/0246 , G06F2212/7205 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/349 , G11C2211/5644
摘要： A method of operating a memory controller includes reading data from a first block of a memory device; detecting degraded pages from a plurality of pages of the first block and counting a number of the degraded pages in the first block; and recharging or reclaiming the first block, which includes the degraded pages, based on the counted number of the degraded pages.
摘要翻译：操作存储器控制器的方法包括从存储器件的第一块读取数据; 从所述第一块的多个页面检测退化的页面，并对所述第一块中的所述劣化页面的数量进行计数; 并且基于所计算的劣化页面的数量来对包括退化页面的第一块进行再充电或回收。

7. 发明申请

US20110246853A1 SEMICONDUCTOR DEVICE AND DECODING METHOD THEREOF 有权
标题翻译：半导体器件及其解码方法
公开(公告)号：US20110246853A1
公开(公告)日：2011-10-06
申请号：US13069834
申请日：2011-03-23
申请人： Yong-June KIM , Jun-Jin Kong , Young-Hwan Lee , Jae-Hong Kim
发明人： Yong-June KIM , Jun-Jin Kong , Young-Hwan Lee , Jae-Hong Kim
IPC分类号： G06F11/08
CPC分类号： G06F11/1048
摘要： An error control coding (ECC) circuit includes a first decoder, a second decoder, and a controller. The first decoder receives encoded data comprising a first parity and a second parity. The first decoder decodes the encoded data to a first code by using the first parity. The second decoder is connected to the first decoder. The second decoder is configured to decode the encoded data when the first decoder is deactivated and decode the first code using the second parity when the first decoder is deactivated. The controller transmits a control signal to the first decoder and the second decoder to control the first decoder and the second decoder.
摘要翻译：错误控制编码（ECC）电路包括第一解码器，第二解码器和控制器。第一解码器接收包括第一奇偶校验和第二奇偶校验的编码数据。第一解码器通过使用第一奇偶校验将编码数据解码为第一代码。第二解码器连接到第一解码器。第二解码器被配置为当第一解码器被去激活时解码编码数据，并且当第一解码器被去激活时使用第二奇偶校验解码第一代码。控制器向第一解码器和第二解码器发送控制信号以控制第一解码器和第二解码器。

8. 发明申请

US20130031443A1 METHOD OF OPERATING MEMORY CONTROLLER, AND MEMORY SYSTEM, MEMORY CARD AND PORTABLE ELECTRONIC DEVICE INCLUDING THE MEMORY CONTROLLER 有权
标题翻译：操作存储器控制器的方法和存储器系统，包括存储器控制器的存储卡和便携式电子设备
公开(公告)号：US20130031443A1
公开(公告)日：2013-01-31
申请号：US13550133
申请日：2012-07-16
申请人： Eun-Chu Oh , Jae-Hong Kim , Yong-June Kim , Jun-Jin Kong
发明人： Eun-Chu Oh , Jae-Hong Kim , Yong-June Kim , Jun-Jin Kong
IPC分类号： G06F11/16 , G06F12/00
CPC分类号： G11C16/3418 , G06F11/1048 , G06F12/0246 , G06F2212/7205 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/349 , G11C2211/5644
摘要： A method of operating a memory controller includes reading data from a first block of a memory device; detecting degraded pages from a plurality of pages of the first block and counting a number of the degraded pages in the first block; and recharging or reclaiming the first block, which includes the degraded pages, based on the counted number of the degraded pages.
摘要翻译：操作存储器控制器的方法包括从存储器件的第一块读取数据; 从所述第一块的多个页面检测退化的页面，并对所述第一块中的所述劣化页面的数量进行计数; 并且基于所计算的劣化页面的数量来对包括退化页面的第一块进行再充电或回收。

9. 发明授权

US07450667B2 Apparatus and method for decoding data of unknown frame length 失效
标题翻译：用于解码未知帧长度的数据的装置和方法
公开(公告)号：US07450667B2
公开(公告)日：2008-11-11
申请号：US09897732
申请日：2001-07-03
申请人： Jae-Hong Kim , Jun-Jin Kong , Sung-Han Choi
发明人： Jae-Hong Kim , Jun-Jin Kong , Sung-Han Choi
IPC分类号： H03D1/00 , H03M13/03
CPC分类号： H03M13/3961 , H03M13/4107 , H03M13/4169
摘要： An apparatus decodes data of unknown frame length. The decoding apparatus includes a preliminary decoding part and a decoded data outputting part. The preliminary decoding part decodes data into preliminarily decoded data according to each of the possible frame lengths. The decoded data outputting part selectively outputs data among the preliminary decoding data that correspond to a detected frame length. Accordingly, memory can be efficiently utilized, and decoding efficiency deterioration is prevented.
摘要翻译：装置解码未知帧长度的数据。解码装置包括初步解码部分和解码数据输出部分。初步解码部分根据每个可能的帧长度将数据解码为预先解码的数据。解码数据输出部分选择性地输出与检测到的帧长度对应的初步解码数据中的数据。因此，可以有效地利用存储器，并且防止解码效率劣化。

10. 发明授权

US09069714B2 Device including an external memory connection unit capable of adopting an external memory 有权
标题翻译：装置包括能够采用外部存储器的外部存储器连接单元
公开(公告)号：US09069714B2
公开(公告)日：2015-06-30
申请号：US13606551
申请日：2012-09-07
申请人： Hak-Soo Yu , Jun-Jin Kong , Hyoung-Joon Kim , Joo-Young Hwang , In-Su Choi
发明人： Hak-Soo Yu , Jun-Jin Kong , Hyoung-Joon Kim , Joo-Young Hwang , In-Su Choi
IPC分类号： G06F13/14 , G06F13/16 , G06F13/38
CPC分类号： G06F13/16 , G06F13/1694 , G06F13/385
摘要： A device includes a memory controller, a memory bus coupled to the memory controller, an internal memory and an external memory connection unit. The internal memory may be directly connected to the memory controller through the memory bus. The external memory connection unit may connect an external memory directly to the memory controller through a portion of signal lines in the memory bus, and may generate a flag signal indicating whether the external memory is connected to the external memory connection unit.
摘要翻译：设备包括存储器控制器，耦合到存储器控制器的存储器总线，内部存储器和外部存储器连接单元。内部存储器可以通过存储器总线直接连接到存储器控制器。外部存储器连接单元可以通过存储器总线中的一部分信号线将外部存储器直接连接到存储器控制器，并且可以产生指示外部存储器是否连接到外部存储器连接单元的标志信号。

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