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1. 发明申请

US20040153931A1 Built-in self-test for multi-channel transceivers without data alignment 有权
公开(公告)号：US20040153931A1
公开(公告)日：2004-08-05
申请号：US10764093
申请日：2004-01-23
申请人： Broadcom Corporation
发明人： Jun Cao , Afshin Momtaz
IPC分类号： G06F011/00 , G01R031/28
CPC分类号： G01R31/31715 , H04B17/19 , H04B17/20
摘要： A method and device for testing multi-channel transceivers in an integrated circuit is provided. More specifically, the present invention relates to a method and device for implementing a built-in self-test for multi-channel transceivers. An exemplary embodiment of the present invention includes a test pattern generator, a multiplexer, a demultiplexer, and a test result evaluator. The test pattern generator generates a test pattern which is fed into each of the input channels of the multiplexer. The multiplexer multiplexes the data from all its input channels and then relays the data to the demultiplexer. The test result evaluator then individually checks the data at each of the output channels of the demultiplexer to determine whether the data received at each output channel is the same as the test pattern. In order to facilitate the checking process, signature analysis is utilized.

2. 发明申请

US20030080815A1 Current-controlled CMOS wideband data amplifier circuits 有权
标题翻译：电流控制CMOS宽带数据放大电路
公开(公告)号：US20030080815A1
公开(公告)日：2003-05-01
申请号：US10028806
申请日：2001-10-25
申请人： Broadcom Corporation
发明人： Guangming Yin , Jun Cao
IPC分类号： H03F003/45
CPC分类号： H03F1/14 , H03F1/483 , H03F2203/45018 , H03F2203/45512 , H03F2203/45554 , H03F2203/45714
摘要： Expansion of the bandwidth of a wideband CMOS data amplifier is accomplished using various combinations of shunt peaking, series peaking, and miller capacitance cancellation. These various combinations are employed in any of the amplifier input stage, in intermediate stages, or in the last stage.
摘要翻译：宽带CMOS数据放大器的带宽扩展使用并联峰值，串联峰值和铣削电容消除的各种组合来实现。这些各种组合用于任何放大器输入级，中间级或最后阶段。

3. 发明申请

US20040091064A1 Phase detector with delay elements for improved data regeneration 审中-公开
标题翻译：具有延迟元件的相位检测器，用于改进数据再生
公开(公告)号：US20040091064A1
公开(公告)日：2004-05-13
申请号：US10293624
申请日：2002-11-12
申请人： Broadcom Corporation
发明人： Jun Cao , Afshin Momtaz
IPC分类号： H03K009/00 , H04L027/06 , H03D003/24
CPC分类号： H03L7/085 , H03D13/003 , H03K3/356043 , H03K3/3562 , H03L7/087 , H03L7/091 , H03L7/113 , H03L7/14 , H04L7/033
摘要： Circuits and methods for simplifying clock and data recovery circuits by including a data regeneration circuit as part of a phase detector circuit. Delay elements are added such that the timing of the data recovery is optimized or improved with little or no effect on the clock recovery operation. This allows die area and power supply savings, while retaining the ability to adjust data recovery timing.
摘要翻译：通过将数据再生电路作为相位检测器电路的一部分来简化时钟和数据恢复电路的电路和方法。添加延迟元素，使得数据恢复的时序被优化或改进，而对时钟恢复操作几乎没有影响。这样可以节省模具面积和电源，同时保留调整数据恢复时间的能力。

4. 发明申请

US20040208273A1 CMOS lock detect with double protection 有权
公开(公告)号：US20040208273A1
公开(公告)日：2004-10-21
申请号：US10843181
申请日：2004-05-11
申请人： Broadcom Corporation
发明人： Jun Cao , Afshin Momtaz
IPC分类号： H03D003/24
CPC分类号： H03L7/10 , H03L7/095 , Y10S331/02
摘要： Method and circuitry for improving the accuracy and efficiency of a phase-locked loop. More specifically, the present invention relates to a method and device for monitoring the frequency discrepancy between two signals in conjunction with at least one data signal so as to improve the accuracy and efficiency of a phase-locked loop. In one embodiment of the present invention, two counters are used to check the frequency differential between a VCO signal and an external reference or input signal. An adjustable threshold is provided to determine whether the frequencies of the two signals are considered to be in a frequency-locked mode. A pair of flip-flops is used to minimize any erroneous detection of frequency discrepancy by validating two consecutive results of the frequency differential check. In addition, a data present signal is used to control the transition between the phase-locked mode and the frequency-locked mode to minimize the potential data loss.

5. 发明申请

US20040153681A1 Phase detector for extended linear response and high-speed data regeneration 审中-公开
标题翻译：相位检测器用于扩展线性响应和高速数据再生
公开(公告)号：US20040153681A1
公开(公告)日：2004-08-05
申请号：US10293163
申请日：2002-11-12
申请人： Broadcom Corporation
发明人： Jun Cao
IPC分类号： H04L005/00
CPC分类号： H03L7/14 , H03D13/003 , H03F3/08 , H03L7/087 , H03L7/091 , H03L7/113 , H04L7/033
摘要： Methods and circuits for phase detectors having extended linear and monotonic ranges of operation. Phase detectors consistent with the present invention include a REFERENCE output that has improved immunity to the timing relationship between data input and clock signals. This improved immunity results in extended linear and monotonic ranges of operations.
摘要翻译：具有延长的线性和单调操作范围的相位检测器的方法和电路。与本发明一致的相位检测器包括对数据输入和时钟信号之间的定时关系具有改进的抗扰性的参考输出。这种改善的免疫力导致延长的线性和单调的操作范围。

6. 发明申请

US20030052708A1 Methods and circuitry for implementing first-in first-out structure 失效
标题翻译：实现先进先出结构的方法和电路
公开(公告)号：US20030052708A1
公开(公告)日：2003-03-20
申请号：US09956374
申请日：2001-09-17
申请人： Broadcom Corporation
发明人： Afshin Momtaz , Xin Wang , Jun Cao , Armond Hairapetian , David Chung
IPC分类号： G06F007/38
CPC分类号： G06F5/10 , G06F2205/106
摘要： Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.
摘要翻译：用于实现高速先进先出（FIFO）结构的方法和电路。在一个实施例中，公开了允许一个时钟（例如写时钟）的频率与另一（读取）时钟的频率不同的（例如，一半）的FIFO。在另一个实施例中，呈现可以异步地设置和/或复位的FIFO。公开了其他实施例，其中有效地监视读取和写入指针，以确保正确的时序关系，以检测时钟损耗以及检测其他异常FIFO条件。

7. 发明申请

US20020099883A1 Overflow detector for FIFO 有权
标题翻译： FIFO溢出检测器
公开(公告)号：US20020099883A1
公开(公告)日：2002-07-25
申请号：US10104870
申请日：2002-03-21
申请人： Broadcom Corporation
发明人： Jun Cao
IPC分类号： G06F003/00
CPC分类号： G11C19/287 , G11C19/28
摘要： The present invention provides an overflow detector for a FIFO. The FIFO includes a plurality of registers each having an input and an output, a plurality of write signals each respectively coupled to a clock, one of the plurality of registers, and a plurality of read switches each respectively coupled to an output of one of the plurality of registers, each of the plurality of read switches being controlled by a respective read signal. The overflow detector includes a plurality of clocked registers each of which is coupled to receive a write signal and its corresponding read signal, wherein each clocked register records a read signal and is clocked by the corresponding write signal.
摘要翻译：本发明提供了一种用于FIFO的溢出检测器。 FIFO包括多个寄存器，每个寄存器具有输入和输出，多个写入信号分别耦合到时钟，多个寄存器之一和多个读取开关，每个读取开关分别耦合到多个寄存器，多个读取开关中的每一个由相应的读取信号控制。溢出检测器包括多个时钟寄存器，每个寄存器被耦合以接收写入信号及其对应的读取信号，其中每个时钟控制寄存器记录读取信号并由对应的写入信号计时。

8. 发明申请

US20040170245A1 Fully differential CMOS phase-locked loop 有权
标题翻译：全差分CMOS锁相环
公开(公告)号：US20040170245A1
公开(公告)日：2004-09-02
申请号：US10797770
申请日：2004-03-10
申请人： Broadcom Corporation
发明人： Armond Hairapetian , Jun Cao , Afshin Momtaz
IPC分类号： H03L007/06 , H04L027/10
CPC分类号： H03L7/18 , H03L7/089 , H03L7/099
摘要： The present invention relates in general to integrated circuits, and in particular to method and circuitry for implementing an improved phase-locked loop (PLL) in complementary metal-oxide-semiconductor (CMOS)technology using current-controlled CMOS (C3MOS) logic. In an exemplary embodiment, a phase-locked loop includes a phase-frequency detector, a Gm cell block, a low pass filter and a voltage controlled oscillator. These various elements of the phase-locked loop are connected to one another in a fully differential manner, i.e., each element has an input and/or an output each having at least a differential signal. In one embodiment, each of these various elements of the phase-locked loop is implemented using C3MOS logic.
摘要翻译：本发明一般涉及集成电路，特别涉及使用电流控制CMOS（C 3 MOS）的互补金属氧化物半导体（CMOS）技术中实现改进的锁相环（PLL）技术的方法和电路）逻辑。在示例性实施例中，锁相环包括相位频率检测器，Gm单元块，低通滤波器和压控振荡器。锁相环的这些各种元件以完全差分的方式相互连接，即每个元件具有至少具有差分信号的输入和/或输出。在一个实施例中，使用C 3 MOS逻辑来实现锁相环的这些各种元件中的每一个。

9. 发明申请

US20040156323A1 Bit slice arbiter 失效
公开(公告)号：US20040156323A1
公开(公告)日：2004-08-12
申请号：US10759454
申请日：2004-01-20
申请人： Broadcom Corporation
发明人： Jun Cao
IPC分类号： H04L012/28
CPC分类号： H04L12/433
摘要： An arbiter circuit is provided for resolving a plurality of N request signals received from a plurality of agents requesting access to a resource. The arbiter circuit includes: a token distribution circuit responsive to a first clock signal defining a grant cycle, and providing a plurality of token priority signals each corresponding with one of the agents, the distribution circuit being operative to prioritize one of the agents at the beginning of each grant cycle by asserting the token priority signal corresponding with the prioritized agent; means forming a token ring; and a plurality of N grant devices coupled together by the token ring, each of the grant devices corresponding with an associated one of the agents and being responsive to the corresponding request signal provided by the associated agent, and also being responsive to the token priority signal corresponding with the associated agent, and being further responsive to a corresponding token carry signal, each of the devices being operative to provide a grant signal to its associated agent if the corresponding request signal is asserted and either the corresponding token priority signal or the corresponding token carry signal is asserted. The token ring means may include a token look ahead device providing enhanced performance characteristics. The token look ahead device is operative to generate the token carry signals in a predictive manner to eliminate a ripple effect.

10. 发明申请

US20030053585A1 Overflow detector for FIFO 有权
公开(公告)号：US20030053585A1
公开(公告)日：2003-03-20
申请号：US10286597
申请日：2002-11-01
申请人： Broadcom Corporation
发明人： Jun Cao
IPC分类号： G06M003/00
CPC分类号： G11C19/287 , G11C19/28
摘要： The present invention provides an overflow detector for a FIFO. The FIFO includes a plurality of registers each having an input and an output, a plurality of write signals each respectively coupled to a clock, one of the plurality of registers, and a plurality of read switches each respectively coupled to an output of one of the plurality of registers, each of the plurality of read switches being controlled by a respective read signal. The overflow detector includes a plurality of clocked registers each of which is coupled to receive a write signal and its corresponding read signal, wherein each clocked register records a read signal and is clocked by the corresponding write signal.

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