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1. 发明申请

US20180224503A1 TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT 审中-公开
公开(公告)号：US20180224503A1
公开(公告)日：2018-08-09
申请号：US15945414
申请日：2018-04-04
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177 , G01R31/317 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/31715 , G01R31/3172 , G01R31/31725 , G01R31/318547
摘要： The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.

2. 发明申请

US20180053738A1 INTEGRATED CIRCUIT DIE HAVING A SPLIT SOLDER PAD 审中-公开
公开(公告)号：US20180053738A1
公开(公告)日：2018-02-22
申请号：US15678201
申请日：2017-08-16
申请人： EM Microelectronic-Marin SA
发明人： Christoph KURATLI , Yves DUPRAZ
IPC分类号： H01L23/00 , H01L23/528 , H01L23/31
CPC分类号： H01L22/32 , G01R31/31715 , G01R31/31937 , H01L23/3114 , H01L23/525 , H01L23/528 , H01L23/5286 , H01L24/05 , H01L24/06 , H01L24/09 , H01L24/16 , H01L24/17 , H01L24/48 , H01L24/49 , H01L2224/02371 , H01L2224/02375 , H01L2224/02377 , H01L2224/0401 , H01L2224/04042 , H01L2224/05015 , H01L2224/05548 , H01L2224/05551 , H01L2224/05552 , H01L2224/05554 , H01L2224/0603 , H01L2224/06051 , H01L2224/06167 , H01L2224/13028 , H01L2224/131 , H01L2224/16106 , H01L2224/1613 , H01L2224/16227 , H01L2224/48227 , H01L2224/49113 , H01L2224/49175 , H01L2924/00014 , H01L2224/05599 , H01L2924/014
摘要： An integrated circuit die having at least two bond pads, a redistribution layer, the redistribution layer including at least one solder pad including comprising two portions arranged to enable an electrical connection between each other by a same solder ball placed on the solder pad, but electrically isolated of each other in the absence of a solder ball on the solder pad at least two redistribution wires, each one connecting one of the two portions to one of the two bond pads, a first bond pad connected via a first redistribution wire to a first portion of the solder pad being dedicated to digital ground and a second bond pad connected via a second redistribution wire to a second portion of the solder pad being dedicated to analog ground.

3. 发明授权

US09810735B2 Core testing machine 有权
公开(公告)号：US09810735B2
公开(公告)日：2017-11-07
申请号：US14866720
申请日：2015-09-25
申请人： Contec, LLC
发明人： Samant Kumar , Dinesh Kumar , Shivashankar Diddimani , Gunjan Samaiya
IPC分类号： G06F11/00 , G01R31/317 , G01R31/3177
CPC分类号： G01R31/31715 , G01R31/3177 , G06F11/00 , G06F11/22
摘要： A core testing executor/processor for testing a plurality of devices simultaneously using virtualization containers to connect to interfaces of corresponding devices under test is disclosed.

4. 发明授权

US09746878B2 Semiconductor device and method of testing semiconductor device 有权
公开(公告)号：US09746878B2
公开(公告)日：2017-08-29
申请号：US14953942
申请日：2015-11-30
申请人： FUJITSU LIMITED
发明人： Gen Oshiyama , Takahiro Shikibu , Osamu Moriyama
IPC分类号： G01R31/30 , G06F1/10 , H01L21/66 , G01R31/3185 , G01R31/317 , H01L25/065
CPC分类号： G06F1/10 , G01R31/31715 , G01R31/318513 , H01L22/22 , H01L22/32 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes chips, wherein a first chip: an internal circuit; first selectors to output signals from one of first outputs; second selectors to output signals from one of second outputs; first output buffer units to relay/interrupt signals output from one of the first outputs; second output buffer units to relay/interrupt signals output from one of the second outputs; first terminals to output a signal from the respective first output buffer units and belong to a first group in which the first terminals are placed at positions distant by first distances; and second terminals to output a signal from the respective second output buffer units and belong to a second group in which the second terminals are placed at positions distant by second distances and each of the second terminals is placed at a position distant from an adjacent first terminal of the first terminals by third distances.

5. 发明申请

US20170053712A1 TEST DEVICES AND TEST SYSTEMS 审中-公开
标题翻译：测试设备和测试系统
公开(公告)号：US20170053712A1
公开(公告)日：2017-02-23
申请号：US15157799
申请日：2016-05-18
申请人： Samsung Electronics Co., Ltd.
发明人： Dong-Gun KIM , Je-Young PARK , Byung-Soo MOON
IPC分类号： G11C29/38 , G11C29/44 , G11C29/12
CPC分类号： G11C29/56008 , G01R17/00 , G01R19/0084 , G01R31/2884 , G01R31/31715 , G01R31/31908 , G06F11/26 , G06F11/263 , G06F11/277 , G11C5/147 , G11C29/08 , G11C29/10 , G11C29/12 , G11C29/12005 , G11C29/50 , G11C29/50004 , G11C29/56004
摘要： A test device includes a data driver and a controller. The controller is configured to generate a test code by dividing a test sequence in a unit of n-bits. The data driver is configured to receive the generated test code and output one of input voltages to a device under test as a test signal based on the generated test code. A storage device stores a test sequence.
摘要翻译：测试设备包括数据驱动器和控制器。控制器被配置为通过以n位为单位划分测试序列来生成测试代码。数据驱动器被配置为接收生成的测试代码，并且基于所生成的测试代码将输入电压中的一个输出到被测器件作为测试信号。存储设备存储测试序列。

6. 发明申请

US20150377967A1 DUTY CYCLE BASED TIMING MARGINING FOR I/O AC TIMING 有权
标题翻译：用于I / O交流时序的基于周期的时序计时
公开(公告)号：US20150377967A1
公开(公告)日：2015-12-31
申请号：US14319528
申请日：2014-06-30
申请人： BHARANI THIRUVENGADAM , CHRISTOPHER NELSON
发明人： BHARANI THIRUVENGADAM , CHRISTOPHER NELSON
IPC分类号： G01R31/317 , G01R31/3177
CPC分类号： G01R31/31715 , G01R31/3171
摘要： Testing I/O (input/output) eye width for an interface with an inverted modulated strobe or clock signal. An I/O interface includes multiple signal lines, each with a hardware I/O buffer with timing characteristics. A system generates a strobe signal with a triggering edge that triggers a write, and a trailing edge that is modulated by adjusting the duty cycle of the strobe signal. The system inverts the modulated strobe signal to generate an inverted strobe signal, wherein the inverted strobe signal has a modulated triggering edge generated from inverting the modulated trailing edge. The device under test writes test data based on the triggering edge of the original strobe signal and reads test data based on the triggering edge of the inverted strobe signal.
摘要翻译：测试具有反相调制选通脉冲或时钟信号的接口的I / O（输入/输出）眼宽。 I / O接口包括多条信号线，每条信号线都带有具有定时特性的硬件I / O缓冲器。系统产生具有触发写入的触发边缘的选通信号，以及通过调整选通信号的占空比来调制的后沿。系统将调制的选通信号反相以产生反相选通信号，其中反相选通信号具有从调制的后沿反相产生的调制触发沿。被测器件根据原始选通信号的触发边沿写入测试数据，并根据反相选通信号的触发沿读取测试数据。

7. 发明授权

US09081056B2 Method for detecting working state of I/O pins of electronic components using charges from human body 有权
标题翻译：使用人体的电荷检测电子元件的I / O引脚的工作状态的方法
公开(公告)号：US09081056B2
公开(公告)日：2015-07-14
申请号：US13871162
申请日：2013-04-26
申请人： Fu Tai Hua Industry (Shenzhen) Co., Ltd. , HON HAI PRECISION INDUSTRY CO., LTD.
发明人： Ren-Wen Huang
IPC分类号： G01R31/20 , G01R19/00 , G01R31/28 , G01R31/317
CPC分类号： G01R31/2886 , G01R31/31715
摘要： In a method for detecting working states of I/O pins of electronic components, a signal is transmitted between at least two of the I/O pins. A probe of an oscilloscope is connected to an I/O pin. A waveform of the signal through the I/O pin is detected. Charges are transmitted to the probe. A working state of the I/O pin is determined by detecting whether the waveform of the signal through the I/O pin is changed when the charges are transmitted to the probe.
摘要翻译：在用于检测电子部件的I / O引脚的工作状态的方法中，在至少两个I / O引脚之间传输信号。示波器的探头连接到I / O引脚。检测到通过I / O引脚的信号波形。充电被传送到探头。 I / O引脚的工作状态是通过检测当电荷传输到探头时是否改变通过I / O引脚的信号的波形而改变的。

8. 发明授权

US09046571B2 Tap with test compression architecture and start bit detector circuit 有权
标题翻译：点击测试压缩架构和起始位检测器电路
公开(公告)号：US09046571B2
公开(公告)日：2015-06-02
申请号：US13948801
申请日：2013-07-23
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/31715 , G01R31/3172 , G01R31/31725 , G01R31/318547
摘要： The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.
摘要翻译：本公开描述了当设备以与其他设备的JTAG菊花链配置存在时用于控制设备的TCA电路的新颖的方法和设备。当设备与其他设备（例如在使用该设备的客户系统中）放置在JTAG菊花链配置中时，这些方法和设备允许在设备制造期间使用的TCA测试模式集被重用。在本公开中还提供和描述了另外的实施例。

9. 发明授权

US09021322B2 Probeless testing of pad buffers on wafer 有权
公开(公告)号：US09021322B2
公开(公告)日：2015-04-28
申请号：US14089069
申请日：2013-11-25
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/28 , G01R31/3177 , G01R31/317 , G01R31/3185 , G11C29/00 , G11C29/02 , G11C29/48 , G11C29/32
CPC分类号： G01R31/3177 , G01R31/31715 , G01R31/318505 , G01R31/318511 , G01R31/318533 , G01R31/318558 , G01R31/318572 , G01R31/318594 , G11C29/006 , G11C29/022 , G11C29/48 , G11C2029/3202
摘要： The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.

10. 发明申请

US20140246705A1 Programmable Leakage Test For Interconnects In Stacked Designs 审中-公开
标题翻译：堆叠设计中互连的可编程泄漏测试
公开(公告)号：US20140246705A1
公开(公告)日：2014-09-04
申请号：US14195639
申请日：2014-03-03
申请人： Mentor Graphics Corporation
发明人： Shi-Yu Huang , Kun-Han Tsai , Wu-Tung Cheng , Yu-Hsiang Lin , Li-Ren Huang
IPC分类号： G06F17/50
CPC分类号： G01R31/318513 , G01R31/31715 , G11C29/025 , G11C2029/5006
摘要： Aspects of the invention relate to techniques of testing interconnects in stacked designs for leakage defects. Logic “1” or “0” is first applied to one end of an interconnect during a first pulse. Then, logic value at the one end is captured, which triggered by an edge of a second pulse. The first pulse precedes the second pulse by a time period being selected from a plurality of delay periods. The plurality of delay periods is generated by a device shared by a plurality of interconnects.
摘要翻译：本发明的方面涉及在堆叠设计中测试用于泄漏缺陷的互连的技术。逻辑“1”或“0”首先在第一脉冲期间施加到互连的一端。然后，捕获一端的逻辑值，由第二个脉冲的边沿触发。第一脉冲在第二脉冲之前在从多个延迟周期中选择的时间周期之前。多个延迟周期由多个互连共享的设备产生。

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