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1. 发明申请

US20040019816A1 Three wire communication protocol 失效
标题翻译：三线通信协议
公开(公告)号：US20040019816A1
公开(公告)日：2004-01-29
申请号：US10205679
申请日：2002-07-25
发明人： Robert B. Smith , Gary E. Long
IPC分类号： G06F013/42 , H04L005/00 , G06F001/12
CPC分类号： H04L12/40039 , H04L7/0008 , H04L7/0054 , H04L12/403 , H04L12/44
摘要： Disclosed is a serial communications protocol for connecting a master and a plurality of slaves using three communication lines. The protocol establishes a method for communication between the master and any slave. Any device on the communication bus may initiate the communication. A method of arbitrating any bus collisions is also given.
摘要翻译：公开了一种用于使用三条通信线路连接主机和多个从机的串行通信协议。该协议建立了主机和任何从机之间的通信方法。通信总线上的任何设备可以启动通信。还给出了一种仲裁任何总线冲突的方法。

2. 发明申请

US20030221137A1 Wide instruction word graphics processor 有权
公开(公告)号：US20030221137A1
公开(公告)日：2003-11-27
申请号：US10411405
申请日：2003-04-10
发明人： Vernon Brethour , Dale Kirkland , William Lazenby , Gary al Shelton
IPC分类号： G06F001/12 , H04L005/00 , H04L007/00 , G06F013/42
CPC分类号： G09G5/363 , G06F9/3806 , G06F9/3885 , G06T1/20 , G09G5/00
摘要： A graphics accelerator includes a vertex input for receiving vertex data, an output for forwarding processed data, and a processor coupled with the vertex input and output. The graphics accelerator also includes an instruction input that receives instructions for processing the vertex data received from the vertex input. The processor is responsive to wide word instructions.

3. 发明申请

US20030221044A1 Memory system, module and register 有权
标题翻译：内存系统，模块和寄存器
公开(公告)号：US20030221044A1
公开(公告)日：2003-11-27
申请号：US10427090
申请日：2003-04-30
申请人： Elpida Memory, Inc.
发明人： Yoji Nishio , Kayoko Shibata , Seiji Funaba
IPC分类号： H04L005/00
CPC分类号： G11C7/109 , G11C7/1078 , G11C7/1093
摘要： Disclosed are a memory command address system and a memory module that can be operated not only for 266 MHzCLK but also for 200 MHzCLK, in which clock timings in the input sections of a PLL, a register, and a DRAM are matched to one another, a DLL (delay locked loop) is provided in the register, the output timing of CA signal from the register is controlled so that the setup time margin and the hold time margin of the CA signal with respect to the clock signal with the additional latency in the DRAMnull1.5 or 2.0 are equated to each other, such that clock operation of 266 MHz, for example, is made possible. If both 266 MHz and 200 MHz are used, by taking account of the timing budget, control is made for retarding the timing of the CA signal input to the flip-flop which receives an internal clock signal (intCLK) supplied to the flip-flop for determining the CA signal output timing from the register. Alternatively, control is made for switching between the replica (replica 1) provided in the register and an output unit associated with the replica, depending on the frequency being used, so as to cope with both frequencies simply by providing one sort of the module and one sort of the register.
摘要翻译：公开了一种存储器命令地址系统和存储器模块，其不仅可以用于266MHzCLK，而且可以用于200MHzCLK，其中PLL，寄存器和DRAM的输入部分中的时钟定时彼此匹配，在寄存器中提供DLL（延迟锁定环），控制来自寄存器的CA信号的输出定时，使得CA信号的建立时间余量和保持时间裕度相对于时钟信号具有额外的等待时间 DRAM = 1.5或2.0彼此相等，使得例如266MHz的时钟操作成为可能。如果使用266MHz和200MHz，通过考虑时序预算，进行控制以延迟输入到触发器的CA信号的定时，该触发器接收提供给触发器的内部时钟信号（intCLK）用于确定来自寄存器的CA信号输出定时。或者，根据所使用的频率，进行控制，用于在寄存器中提供的副本（副本1）和与副本相关联的输出单元之间进行切换，从而简单地通过提供一种模块和一种登记册。

4. 发明申请

US20030093703A1 Multiple dataport clock synchronization 审中-公开
标题翻译：多个数据端口时钟同步
公开(公告)号：US20030093703A1
公开(公告)日：2003-05-15
申请号：US10007775
申请日：2001-11-09
申请人： ADC DSL Systems, Inc.
发明人： Jeffrey Oliver , Craig Evensen
IPC分类号： G06F013/42 , H04L007/00 , H04L005/00 , G06F001/12
CPC分类号： H04J3/0688 , H04J3/0691 , H04L27/2662
摘要： A communications device apparatus and method is detailed that allows for improved operation and reduced costs of network communication links and datastreams with an improved ability to merge and synchronize multiple WAN and LAN dataport datastreams. The improved communications device apparatus and method allows for a master data clock selection, a clock recovery, a derivate data clock division and a dataport data clock selection that allows for the generation of one or more synchronous derivative data clocks and the merging of multiple dataport datastreams for data transceiving. The improved communications device apparatus and method also allows for a master data clock to be recovered from a selected dataport and the other differing data rate dataports to be synchronized to it for the merging of multiple dataport datastreams for data transceiving.
摘要翻译：详细描述了一种通信设备装置和方法，其允许改进的操作和降低网络通信链路和数据流的成本，具有改进的能够合并和同步多个WAN和LAN数据端口数据流的能力。改进的通信设备装置和方法允许主数据时钟选择，时钟恢复，导出数据时钟分割和数据端口数据时钟选择，其允许生成一个或多个同步导数数据时钟并且合并多个数据端口数据流用于数据收发。改进的通信设备装置和方法还允许从选定的数据端口恢复主数据时钟，并且允许与其同步的其他不同的数据速率数据端口用于合并用于数据收发的多个数据端口数据流。

5. 发明申请

US20030074593A1 Apparatus and method for asynchronously interfacing high-speed clock domain and low-speed clock domain 失效
标题翻译：用于异步连接高速时钟域和低速时钟域的装置和方法
公开(公告)号：US20030074593A1
公开(公告)日：2003-04-17
申请号：US09978357
申请日：2001-10-16
申请人： International Business Machines Corporation
发明人： Gary Dale Carpenter , Tung Nguyen Pham
IPC分类号： G06F001/04 , G06F005/06 , G06F013/42 , H04L007/00 , H04L005/00 , G06F001/12
CPC分类号： G06F5/06 , H04L7/02
摘要： Interfacing circuitry for asynchronously transferring data between a high-speed clock domain and a low-speed clock domain is provided. The interfacing circuitry is divided into halves, with one half being synchronized to a first clock and the second half being synchronized to a second clock. The first half and the second half are mirror images of each other. Each half has at least one storage component, such as a register and a flip-flop, for storing a valid bit as well as data, and at least one multiplexer component for gating the storage component. The valid bit is used to control the multiplexer at a receiving half. When transferring from a high-speed clock domain to a low-speed clock domain, the high-speed clock domain may probe the received data and/or the valid bit stored in the low-speed clock domain before the high-speed clock domain sends additional data.
摘要翻译：提供了在高速时钟域和低速时钟域之间异步传输数据的接口电路。接口电路被分成两半，其中一半与第一时钟同步，而后半部分与第二时钟同步。上半场和下半场是彼此的镜像。每一半具有用于存储有效位和数据的至少一个存储组件，例如寄存器和触发器，以及用于门控存储组件的至少一个多路复用器组件。有效位用于在接收端控制多路复用器。当从高速时钟域传输到低速时钟域时，高速时钟域可以在高速时钟域发送之前探测存储在低速时钟域中的接收数据和/或有效位附加数据。

6. 发明申请

US20020118199A1 Swap buffer synchronization in a distributed rendering system 失效
标题翻译：在分布式渲染系统中交换缓冲区同步
公开(公告)号：US20020118199A1
公开(公告)日：2002-08-29
申请号：US09993889
申请日：2001-11-27
发明人： Shrijeet Mukherjee , Kanoj Sarcar , James Tornes
IPC分类号： G06F015/16 , G06F001/12 , H04L005/00 , H04L007/00 , G06F013/42
CPC分类号： G09G5/12 , G06F3/1438 , G09G5/399 , G09G2300/026
摘要： A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.
摘要翻译：一种用于在多处理器多显示环境中同步图像显示和缓冲器交换的系统和方法。在主从二分法中，一个处理器或系统被认为是主机，另一个处理器或系统作为从机。主机产生用于控制自身和从站的垂直回扫和缓冲区交换的信号。另外，同步信号发生器被提供以同步主系统和从系统之间的定时信号。

7. 发明申请

US20020019951A1 Timer adjusting system 失效
标题翻译：定时调整系统
公开(公告)号：US20020019951A1
公开(公告)日：2002-02-14
申请号：US09808343
申请日：2001-03-15
发明人： Masahito Kubo , Haruhiko Ueno , Akikazu Nakagawa
IPC分类号： G06F001/12 , H04L005/00 , H04L007/00 , G06F013/42
CPC分类号： G06F1/14
摘要： In a multi-processor system, each processor transmits a system time synchronous signal to another processor using hardware, and measures the propagation delay time of the signal. Then, the timer value of each processor is adjusted with the measured propagation delay time.
摘要翻译：在多处理器系统中，每个处理器使用硬件向另一个处理器发送系统时间同步信号，并测量信号的传播延迟时间。然后，用测量的传播延迟时间调整每个处理器的定时器值。

8. 发明申请

US20040153681A1 Phase detector for extended linear response and high-speed data regeneration 审中-公开
标题翻译：相位检测器用于扩展线性响应和高速数据再生
公开(公告)号：US20040153681A1
公开(公告)日：2004-08-05
申请号：US10293163
申请日：2002-11-12
申请人： Broadcom Corporation
发明人： Jun Cao
IPC分类号： H04L005/00
CPC分类号： H03L7/14 , H03D13/003 , H03F3/08 , H03L7/087 , H03L7/091 , H03L7/113 , H04L7/033
摘要： Methods and circuits for phase detectors having extended linear and monotonic ranges of operation. Phase detectors consistent with the present invention include a REFERENCE output that has improved immunity to the timing relationship between data input and clock signals. This improved immunity results in extended linear and monotonic ranges of operations.
摘要翻译：具有延长的线性和单调操作范围的相位检测器的方法和电路。与本发明一致的相位检测器包括对数据输入和时钟信号之间的定时关系具有改进的抗扰性的参考输出。这种改善的免疫力导致延长的线性和单调的操作范围。

9. 发明申请

US20040095497A1 Timing generator for electronic image sensor with tables that control line and frame timing 有权
标题翻译：具有控制线和帧时序的表的电子图像传感器的定时发生器
公开(公告)号：US20040095497A1
公开(公告)日：2004-05-20
申请号：US10635332
申请日：2003-08-06
发明人： John T. Compton , David M. Charneski , Wayne W. Hintz , Edward P. Lawler , William F. DesJardin , Richard B. Brolly , Herbert J. Erhardt
IPC分类号： H04N003/14 , H04N005/335 , G06F001/12 , H04L005/00 , H04L007/00 , G06F003/00 , G06F003/023
CPC分类号： H04N5/335
摘要： A timing generator for an electronic image sensor includes one or more memory based tables for controlling timing events that occur within one or more different types of image sensor lines, and one or more memory based tables for controlling timing events that occur within one or more different types of image sensor frames.
摘要翻译：电子图像传感器的定时发生器包括用于控制在一个或多个不同类型的图像传感器线路内发生的定时事件的一个或多个基于存储器的表，以及一个或多个基于存储器的表，用于控制在一个或多个不同类型图像传感器帧类型。

10. 发明申请

US20020184549A1 Parallel data communication having multiple sync codes 有权
标题翻译：具有多个同步码的并行数据通信
公开(公告)号：US20020184549A1
公开(公告)日：2002-12-05
申请号：US09871117
申请日：2001-05-31
申请人： Philips Semiconductor, Inc.
发明人： Gregory E. Ehmann
IPC分类号： G06F001/12 , H04L005/00 , G06F013/42
CPC分类号： H04L25/14 , H04L7/0008 , H04L7/04 , H04L25/4908
摘要： A high-speed parallel-data communication approach overcomes skewing problems by transferring digital data with automatic realignment. In one example embodiment, a parallel bus has parallel bus lines adapted to transfer digital data from a data file, along with a synchronizing clock signal. To calibrate the synchronization, the sending module transfers synchronization codes which are sampled and validated according to an edge of the clock signal by a receiving module and then used to time-adjust the edge of the clock signal relative to the synchronization codes. The synchronization codes are implemented to toggle the bus lines with each of the synchronization codes transferred.
摘要翻译：高速并行数据通信方法通过自动对准传输数字数据来克服偏斜问题。在一个示例实施例中，并行总线具有适于从数据文件传送数字数据的并行总线以及同步时钟信号。为了校准同步，发送模块通过接收模块传输根据时钟信号的边沿进行采样和验证的同步码，然后用于相对于同步码对时钟信号的边沿进行时间调整。执行同步代码以在传送了每个同步码的情况下切换总线。

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