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1. 发明授权

US08940634B2 Overlapping contacts for semiconductor device 有权
标题翻译：半导体器件重叠触点
公开(公告)号：US08940634B2
公开(公告)日：2015-01-27
申请号：US13171657
申请日：2011-06-29
申请人： Brett H. Engel , Lindsey Hall , David F. Hilscher , Randolph F. Knarr , Steven R. Soss , Jin Z. Wallner
发明人： Brett H. Engel , Lindsey Hall , David F. Hilscher , Randolph F. Knarr , Steven R. Soss , Jin Z. Wallner
IPC分类号： H01L23/528 , H01L21/768 , H01L23/522
CPC分类号： H01L23/528 , H01L21/76816 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.
摘要翻译：在半导体器件中形成重叠触点的方法包括在电介质层中形成第一触点; 蚀刻电介质层以形成与第一接触相邻的凹部，并且在蚀刻介电层的同时去除第一接触的顶部，其中在电介质层中形成凹部之后第一接触的底部保留在电介质层中 ; 以及在与所述第一接触件的底部相邻的所述凹部中形成第二触点，并且在所述第一接触件的底部的顶表面的顶部上形成第二接触。

2. 发明申请

US20130001786A1 OVERLAPPING CONTACTS FOR SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的重叠接触
公开(公告)号：US20130001786A1
公开(公告)日：2013-01-03
申请号：US13171657
申请日：2011-06-29
申请人： Brett H. Engel , Lindsey Hall , David F. Hilscher , Randolph F. Knarr , Steven R. Soss , Jin Z. Wallner
发明人： Brett H. Engel , Lindsey Hall , David F. Hilscher , Randolph F. Knarr , Steven R. Soss , Jin Z. Wallner
IPC分类号： H01L21/28 , H01L23/48
CPC分类号： H01L23/528 , H01L21/76816 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.
摘要翻译：在半导体器件中形成重叠触点的方法包括在电介质层中形成第一触点; 蚀刻电介质层以形成与第一接触相邻的凹部，并且在蚀刻介电层的同时去除第一接触的顶部，其中在电介质层中形成凹部之后第一接触的底部保留在电介质层中 ; 以及在与所述第一接触件的底部相邻的所述凹部中形成第二触点，并且在所述第一接触件的底部的顶表面的顶部上形成第二接触。

3. 发明授权

US08119470B2 Mitigation of gate to contact capacitance in CMOS flow 有权
标题翻译：栅极接触电容在CMOS流中的缓解
公开(公告)号：US08119470B2
公开(公告)日：2012-02-21
申请号：US11726253
申请日：2007-03-21
申请人： Shashank Sureshchandra Ekbote , Borna Obradovic , Lindsey Hall , Craig Huffman , Ajith Varghese
发明人： Shashank Sureshchandra Ekbote , Borna Obradovic , Lindsey Hall , Craig Huffman , Ajith Varghese
IPC分类号： H01L21/338 , H01L21/336 , H01L21/4763
CPC分类号： H01L29/7833 , H01L21/76804 , H01L21/76897 , H01L29/6656 , H01L29/6659 , Y02P80/30
摘要： Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics.
摘要翻译：主要是氧化物而不是氮化物的侧壁间隔物邻近CMOS晶体管的栅极叠层形成。单独的侧壁间隔物位于栅极堆叠的导电栅电极和晶体管的导电接触之间。因此，取决于插入的侧壁间隔物的介电常数，可以在栅电极和接触之间产生电容。因此，从具有比氮化物更低的介电常数的氧化物形成侧壁间隔物减轻了另外可能在这些特征之间产生的电容。这种电容至少是不利的，因为它可以抑制晶体管的切换速度。因此，如本文所述的形成侧壁间隔件可以通过减少具有不令人满意的切换速度和/或其它不期望的性能特征的设备的数量来减轻产量损失。

4. 发明申请

US20080076191A1 GCIB smoothing of the contact level to improve PZT films 审中-公开
标题翻译： GCIB平滑接触电平以改善PZT薄膜
公开(公告)号：US20080076191A1
公开(公告)日：2008-03-27
申请号：US11525475
申请日：2006-09-22
申请人： Lindsey Hall , Sanjeev Aggarwal , Satyavolu Srinivas Papa Rao
发明人： Lindsey Hall , Sanjeev Aggarwal , Satyavolu Srinivas Papa Rao
IPC分类号： H01L21/8242
CPC分类号： H01L27/11507 , H01L27/11502 , H01L28/55
摘要： A ferroelectric capacitor stack is formed over a metal-dielectric interconnect layer. After forming the interconnect layer, the surface of the interconnect layer is treated with gas cluster ion beam (GCIB) processing. Prior to this processing, the surface typically includes metal recesses. The GCIB processing smoothes these recesses and provides a more level surface on which to form the ferroelectric capacitor stack. When the ferroelectric capacitor stack is formed on this leveled surface, leakage is reduced and yields increased as compared to the case where GCIB processing is not used.
摘要翻译：在金属 - 电介质互连层上形成铁电电容器堆叠。在形成互连层之后，用气体簇离子束（GCIB）处理处理互连层的表面。在此处理之前，表面通常包括金属凹槽。 GCIB处理平滑了这些凹槽，并提供了一个更高水平的表面，在其上形成铁电电容器叠层。当在该平坦化表面上形成铁电电容器堆叠时，与不使用GCIB处理的情况相比，泄漏降低并且产量增加。

5. 发明申请

US20060134808A1 Ferroelectric capacitor stack etch cleaning methods 有权
标题翻译：铁电电容堆栈蚀刻清洗方法
公开(公告)号：US20060134808A1
公开(公告)日：2006-06-22
申请号：US11016400
申请日：2004-12-17
申请人： Scott Summerfelt , Lindsey Hall , K. Udayakumar , Theodore Moise
发明人： Scott Summerfelt , Lindsey Hall , K. Udayakumar , Theodore Moise
IPC分类号： H01L21/00
CPC分类号： H01L21/0206 , H01L21/02071 , H01L28/55 , H01L28/57 , H01L28/65 , H01L28/75
摘要： Methods (100) are provided for fabricating a ferroelectric capacitor structure including methods (128) for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The methods comprise etching (140, 200) portions of an upper electrode, etching (141, 201) ferroelectric material, and etching (142, 202) a lower electrode to define a patterned ferroelectric capacitor structure, and etching (143, 206) a portion of a lower electrode diffusion barrier structure. The methods further comprise ashing (144, 203) the patterned ferroelectric capacitor structure using a first ashing process, performing (145, 204) a wet clean process after the first ashing process, and ashing (146, 205) the patterned ferroelectric capacitor structure using a second ashing process directly after the wet clean process at a high temperature in an oxidizing ambient.
摘要翻译：提供了用于制造铁电电容器结构的方法（100），其包括用于在半导体器件中蚀刻和清洁图案化的铁电电容器结构的方法（128）。所述方法包括：上电极的蚀刻（140,200）部分，蚀刻（141,201）铁电材料和蚀刻（142,202）下电极以限定图案化的铁电电容器结构，以及蚀刻（143,206）a 部分下部电极扩散阻挡结构。所述方法还包括使用第一灰化处理灰化（144,203）所述图案化的铁电电容器结构，在第一灰化过程之后执行（145,204）湿式清洁处理，以及使用所述图案化铁电电容器结构灰化（146,205）在氧化环境中的高温下在湿式清洁工艺之后直接进行第二次灰化处理。

6. 发明申请

US20060024898A1 Increased drive current by isotropic recess etch 有权
标题翻译：通过各向同性凹槽蚀刻增加驱动电流
公开(公告)号：US20060024898A1
公开(公告)日：2006-02-02
申请号：US10902360
申请日：2004-07-29
申请人： PR Chidambaram , Lindsey Hall , Haowen Bu
发明人： PR Chidambaram , Lindsey Hall , Haowen Bu
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636
摘要： A method (100) of forming a transistor includes forming a gate structure (108) over a semiconductor body and forming recesses (112) using an isotropic etch using the gate structure as an etch mask. The isotropic etch forms a recess in the semiconductor body that extends laterally in the semiconductor body toward a channel portion of the semiconductor body underlying the gate structure. The method further includes epitaxially growing silicon (114) comprising stress-inducing species in the recesses. The source and drain regions are then implanted (120) in the semiconductor body on opposing sides of the gate structure.
摘要翻译：形成晶体管的方法（100）包括在半导体主体上形成栅极结构（108）并使用栅极结构作为蚀刻掩模使用各向同性蚀刻形成凹陷（112）。各向同性蚀刻在半导体本体中形成凹槽，其在半导体本体中横向延伸到栅极结构下方的半导体主体的沟道部分。该方法还包括在凹槽中外延生长包含应力诱导物质的硅（114）。然后将源极和漏极区域（120）注入到栅极结构的相对侧上的半导体本体中。

7. 发明申请

US20060134844A1 Method for fabricating dual work function metal gates 有权
标题翻译：双功能金属门制造方法
公开(公告)号：US20060134844A1
公开(公告)日：2006-06-22
申请号：US11017469
申请日：2004-12-20
申请人： Jiong-Ping Lu , Shaofeng Yu , Haowen Bu , Lindsey Hall , Mark Visokay
发明人： Jiong-Ping Lu , Shaofeng Yu , Haowen Bu , Lindsey Hall , Mark Visokay
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28097 , H01L21/28518 , H01L29/4975 , H01L29/51 , H01L29/6659 , H01L29/7833
摘要： A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate 20 that includes having a gate protection layer 210 over the gate electrode layer 110 during the formation of source/drain silicides 120. The method may include implanting dopants into a gate polysilicon layer 115 before forming the protection layer 215.
摘要翻译：一种用于在半导体衬底20上制造PMOS和NMOS晶体管60,70的方法，其包括在源/漏硅化物120形成期间在栅电极层110上方具有栅极保护层210。该方法可以包括在形成保护层215之前将掺杂剂注入到栅极多晶硅层115中。

8. 发明申请

US20060121713A1 Method for manufacturing a silicided gate electrode using a buffer layer 有权
标题翻译：使用缓冲层制造硅化栅电极的方法
公开(公告)号：US20060121713A1
公开(公告)日：2006-06-08
申请号：US11007569
申请日：2004-12-08
申请人： Shaofeng Yu , Haowen Bu , Jiong-Ping Lu , Lindsey Hall
发明人： Shaofeng Yu , Haowen Bu , Jiong-Ping Lu , Lindsey Hall
IPC分类号： H01L21/4763 , H01L21/3205
CPC分类号： H01L29/66545 , H01L29/51 , H01L29/66507 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes providing a capped polysilicon gate electrode (290) over a substrate (210), the capped polysilicon gate electrode (290) including a buffer layer (260) located between a polysilicon gate electrode layer (250) and a protective layer (270). The method further includes forming source/drain regions (710) in the substrate (210) proximate the capped polysilicon gate electrode (290), removing the protective layer (270) and the buffer layer (260), and siliciding the polysilicon gate electrode layer (250) to form a silicided gate electrode (1110).
摘要翻译：本发明提供一种制造半导体器件的方法和集成电路的制造方法。制造半导体器件的方法以及其他步骤包括在衬底（210）上提供封盖的多晶硅栅电极（290），封装的多晶硅栅电极（290）包括位于多晶硅栅电极层（250）和保护层（270）。该方法还包括在靠近封盖的多晶硅栅极（290）的基板（210）中形成源/漏区（710），去除保护层（270）和缓冲层（260），并且将多晶硅栅电极层（250），以形成硅化物栅电极（1110）。

9. 发明授权

US06995088B2 Surface treatment of copper to improve interconnect formation 有权
标题翻译：铜的表面处理以改善互连形成
公开(公告)号：US06995088B2
公开(公告)日：2006-02-07
申请号：US10848219
申请日：2004-05-18
申请人： Sanjeev Aggarwal , Lindsey Hall , Trace Q. Hurd
发明人： Sanjeev Aggarwal , Lindsey Hall , Trace Q. Hurd
IPC分类号： H01L21/44
CPC分类号： H01L21/2885 , H01L21/76843 , H01L21/76855 , H01L21/76861 , H01L21/76873
摘要： The present invention provides, in one embodiment, a method of forming a copper layer (100) over a semiconductor substrate (105). The method comprises coating a copper seed layer (110) located over a semiconductor substrate with a protective agent (120) to form a protective layer (125). The method also includes placing the semiconductor substrate in an acid bath (145) to remove the protective layer. The method further includes electrochemically depositing a second copper layer (155) on the copper seed layer. Such methods and resulting conductive structures thereof may be advantageously used in methods to manufacture integrated circuits comprising copper interconnects.
摘要翻译：在一个实施例中，本发明提供了一种在半导体衬底（105）上形成铜层（100）的方法。该方法包括用保护剂（120）涂覆位于半导体衬底上的铜籽晶层（110）以形成保护层（125）。该方法还包括将半导体衬底放置在酸浴（145）中以去除保护层。该方法还包括在铜籽晶层上电化学沉积第二铜层（155）。这样的方法及其导电结构可有利地用于制造包括铜互连的集成电路的方法中。

10. 发明申请

US20060024972A1 Silicon recess improvement through improved post implant resist removal and cleans 有权
标题翻译：通过改进的后植入物抗蚀剂去除和清洁来改善硅凹槽
公开(公告)号：US20060024972A1
公开(公告)日：2006-02-02
申请号：US10901827
申请日：2004-07-29
申请人： Lindsey Hall , Trace Hurd , Deborah Riley
发明人： Lindsey Hall , Trace Hurd , Deborah Riley
IPC分类号： H01L21/302 , H01L21/311
CPC分类号： H01L21/31138 , G03F7/423 , G03F7/427 , H01L21/31133 , H01L21/8238 , H01L29/6659
摘要： The present invention provides a process of manufacturing a semiconductor device 200 while reducing silicon loss. In one aspect, the process includes removing a photoresist layer 270 from a semiconductor substrate 235 adjacent a gate 240 and cleaning the semiconductor substrate with a wet clean solution. The removing step includes subjecting the photoresist layer 270 to a plasma ash. The plasma ash removes at least a portion of a crust 275 formed on the photoresist layer 270 but leaves a substantial portion of the photoresist layer 270. The photoresist layer 270 is subjected to a wet etch subsequent to the plasma ash that removes a substantial portion of the photoresist layer 270.
摘要翻译：本发明提供一种在减少硅损耗的同时制造半导体器件200的工艺。在一个方面，该方法包括从邻近门240的半导体衬底235去除光致抗蚀剂层270并用湿清洁溶液清洁半导体衬底。去除步骤包括使光致抗蚀剂层270经受等离子体灰分。等离子体灰去除形成在光致抗蚀剂层270上的外壳275的至少一部分，但留下光致抗蚀剂层270的大部分。光致抗蚀剂层270在等离子体灰之后进行湿法蚀刻，其除去光致抗蚀剂层270的主要部分。

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