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1. 发明授权

US07892930B2 Method to improve transistor tox using SI recessing with no additional masking steps 有权
标题翻译：使用SI凹陷来改善晶体管的方法，无需额外的掩蔽步骤
公开(公告)号：US07892930B2
公开(公告)日：2011-02-22
申请号：US11868787
申请日：2007-10-08
申请人： Borna Obradovic , Shashank S. Ekbote
发明人： Borna Obradovic , Shashank S. Ekbote
IPC分类号： H01L21/336
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823842 , H01L29/7848
摘要： A method of forming a transistor device is provided wherein a gate structure is formed over a semiconductor body of a first conductivity type. The gate structure is formed comprising a protective cap thereover and defining source/drain regions laterally adjacent thereto. A first implant is performed of a second conductivity type into both the gate structure and the source/drain regions. The semiconductor body is etched to form recesses substantially aligned to the gate structure wherein the first implant is removed from the source/drain regions. Source/drain regions are implanted or grown by a selective epitaxial growth.
摘要翻译：提供一种形成晶体管器件的方法，其中栅极结构形成在第一导电类型的半导体本体上。门结构被形成为包括其上的保护盖并且限定与其横向相邻的源/漏区。在栅极结构和源极/漏极区域中进行第二导电类型的第一注入。半导体本体被蚀刻以形成基本上对准栅极结构的凹槽，其中第一注入从源极/漏极区域移除。通过选择性外延生长植入或生长源极/漏极区域。

2. 发明授权

US07812401B2 MOS device and process having low resistance silicide interface using additional source/drain implant 有权
标题翻译： MOS器件和工艺具有使用额外的源极/漏极注入的低电阻硅化物界面
公开(公告)号：US07812401B2
公开(公告)日：2010-10-12
申请号：US12688966
申请日：2010-01-18
申请人： Borna Obradovic , Shashank Ekbote , Mark Visokay
发明人： Borna Obradovic , Shashank Ekbote , Mark Visokay
IPC分类号： H01L27/092
CPC分类号： H01L29/7833 , H01L21/26513 , H01L21/823814 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a gate insulator over the channel region. A silicide layer forming a low resistance contact is at an interface region at a surface portion of the source and drain. At the interface region a chemical concentration of the first dopant is at least 5×1020 cm−3. Silicide interfaces according to the invention provide MOS transistor with a low silicide interface resistance, low pipe density, with an acceptably small impact on short channel behavior.
摘要翻译：集成电路（IC）包括半导体衬底，形成在衬底中或衬底上的至少一个MOS晶体管，所述MOS晶体管包括掺杂有第一掺杂剂类型的源极和漏极，所述第一掺杂类型具有介于其间的第二掺杂剂类型的沟道区，以及栅电极和沟道区上的栅极绝缘体。形成低电阻接触的硅化物层位于源极和漏极的表面部分的界面区域。在界面区域，第一掺杂剂的化学浓度为至少5×1020cm-3。根据本发明的硅化物界面提供具有低硅化物界面电阻，低管密度的MOS晶体管，对短沟道行为具有可接受的小的影响。

3. 发明申请

US20120168837A1 Ferroelectric Memory Electrical Contact 审中-公开
标题翻译：铁电存储器电接点
公开(公告)号：US20120168837A1
公开(公告)日：2012-07-05
申请号：US13312352
申请日：2011-12-06
申请人： Steven Craig BARTLING , Michael Patrick CLINTON , Borna OBRADOVIC
发明人： Steven Craig BARTLING , Michael Patrick CLINTON , Borna OBRADOVIC
IPC分类号： H01L27/115 , H01L21/8246
CPC分类号： H01L27/11507 , H01L27/0207 , H01L27/11504 , H01L28/55
摘要： A ferroelectric apparatus includes a circuit having a first capacitor electrically coupled to a plate line via a top terminal connection of the first ferroelectric capacitor and to a storage node via a bottom terminal connection of the first ferroelectric capacitor. The circuit also includes a second ferroelectric capacitor electrically coupled to a second plate line via a second bottom terminal connection of the second ferroelectric capacitor and to the storage node via a second top terminal connection of the second ferroelectric capacitor.
摘要翻译：铁电设备包括电路，该电路具有经由第一铁电电容器的顶端连接器电连接到板线的第一电容器和经由第一铁电电容器的底端连接而连接到存储节点的电路。电路还包括经由第二铁电电容器的第二底部端子连接电耦合到第二板线的第二铁电电容器和经由第二铁电电容器的第二顶部端子连接到存储节点的第二铁电电容器。

4. 发明申请

US20110027954A1 METHOD TO IMPROVE TRANSISTOR TOX USING SI RECESSING WITH NO ADDITIONAL MASKING STEPS 审中-公开
标题翻译：使用无附加掩蔽步骤的方法来改善晶状体毒素的方法
公开(公告)号：US20110027954A1
公开(公告)日：2011-02-03
申请号：US12900821
申请日：2010-10-08
申请人： Borna Obradovic , Shashank S. Ekbote
发明人： Borna Obradovic , Shashank S. Ekbote
IPC分类号： H01L21/335 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823842 , H01L29/7848
摘要： A method of forming a transistor device is provided wherein a gate structure is formed over a semiconductor body of a first conductivity type. The gate structure is formed comprising a protective cap thereover and defining source/drain regions laterally adjacent thereto. A first implant is performed of a second conductivity type into both the gate structure and the source/drain regions. The semiconductor body is etched to form recesses substantially aligned to the gate structure wherein the first implant is removed from the source/drain regions. Source/drain regions are implanted or grown by a selective epitaxial growth.
摘要翻译：提供一种形成晶体管器件的方法，其中栅极结构形成在第一导电类型的半导体本体上。门结构被形成为包括其上的保护盖并且限定与其横向相邻的源/漏区。在栅极结构和源极/漏极区域中进行第二导电类型的第一注入。半导体本体被蚀刻以形成基本上对准栅极结构的凹槽，其中第一注入从源极/漏极区域移除。通过选择性外延生长植入或生长源极/漏极区域。

5. 发明申请

US20100109089A1 MOS DEVICE AND PROCESS HAVING LOW RESISTANCE SILICIDE INTERFACE USING ADDITIONAL SOURCE/DRAIN IMPLANT 有权
标题翻译：具有附加源/漏极植入物的低电阻硅化物界面的MOS器件和工艺
公开(公告)号：US20100109089A1
公开(公告)日：2010-05-06
申请号：US12688966
申请日：2010-01-18
申请人： Borna OBRADOVIC , Shashank EKBOTE , Mark VISOKAY
发明人： Borna OBRADOVIC , Shashank EKBOTE , Mark VISOKAY
IPC分类号： H01L27/092
CPC分类号： H01L29/7833 , H01L21/26513 , H01L21/823814 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a gate insulator over the channel region. A silicide layer forming a low resistance contact is at an interface region at a surface portion of the source and drain. At the interface region a chemical concentration of the first dopant is at least 5×1020 cm−3. Silicide interfaces according to the invention provide MOS transistor with a low silicide interface resistance, low pipe density, with an acceptably small impact on short channel behavior.
摘要翻译：集成电路（IC）包括半导体衬底，形成在衬底中或衬底上的至少一个MOS晶体管，所述MOS晶体管包括掺杂有第一掺杂剂类型的源极和漏极，所述第一掺杂类型具有介于其间的第二掺杂剂类型的沟道区，以及栅电极和沟道区上的栅极绝缘体。形成低电阻接触的硅化物层位于源极和漏极的表面部分的界面区域。在界面区域，第一掺杂剂的化学浓度为至少5×1020cm-3。根据本发明的硅化物界面提供具有低硅化物界面电阻，低管密度的MOS晶体管，对短沟道行为具有可接受的小的影响。

6. 发明授权

US07537988B2 Differential offset spacer 有权
标题翻译：差分补偿垫片
公开(公告)号：US07537988B2
公开(公告)日：2009-05-26
申请号：US11870241
申请日：2007-10-10
申请人： Shashank Ekbote , Deborah J. Riley , Borna Obradovic
发明人： Shashank Ekbote , Deborah J. Riley , Borna Obradovic
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L27/1104 , G11C11/412 , H01L21/823864 , H01L27/11
摘要： A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric and a plurality of gate electrodes thereon in both NMOS and PMOS regions using the surface. A multi-layer offset spacer stack including a top layer and a compositionally different bottom layer is formed and the multi-layer spacer stack is etched to form offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize a thinner offset spacer are covered with a first masking material, and transistors designed to utilize a thicker offset spacer are patterned and first implanted. At least a portion of the top layer is removed to leave the thinner offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize the thicker offset spacer are covered with a second masking material, and the transistors designed to utilize the thinner offset spacer are patterned and second implanted. The fabrication of the integrated circuit is then completed.
摘要翻译：制造CMOS集成电路的方法包括以下步骤：使用该表面在NMOS和PMOS区域中提供具有半导体表面的衬底，在其上形成栅极电介质和多个栅电极。形成包括顶层和组成不同底层的多层偏移间隔堆叠，并且蚀刻多层间隔堆叠以在栅电极的侧壁上形成偏置间隔物。设计成利用较薄的偏移间隔物的晶体管被第一掩模材料覆盖，并且被设计成利用更厚的偏移间隔物的晶体管被图案化并且首先被注入。去除顶层的至少一部分以在栅电极的侧壁上留下较薄的偏移间隔物。设计成利用较厚的偏移间隔物的晶体管被第二掩模材料覆盖，并且设计成利用较薄的偏移间隔物的晶体管被图案化并且被第二次注入。然后完成集成电路的制造。

7. 发明申请

US20090093095A1 METHOD TO IMPROVE TRANSISTOR TOX USING SI RECESSING WITH NO ADDITIONAL MASKING STEPS 有权
标题翻译：使用无附加掩蔽步骤的方法来改善晶状体毒素的方法
公开(公告)号：US20090093095A1
公开(公告)日：2009-04-09
申请号：US11868787
申请日：2007-10-08
申请人： Borna Obradovic , Shashank S. Ekbote
发明人： Borna Obradovic , Shashank S. Ekbote
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823842 , H01L29/7848
摘要： A method of forming a transistor device is provided wherein a gate structure is formed over a semiconductor body of a first conductivity type. The gate structure is formed comprising a protective cap thereover and defining source/drain regions laterally adjacent thereto. A first implant is performed of a second conductivity type into both the gate structure and the source/drain regions. The semiconductor body is etched to form recesses substantially aligned to the gate structure wherein the first implant is removed from the source/drain regions. Source/drain regions are implanted or grown by a selective epitaxial growth.
摘要翻译：提供一种形成晶体管器件的方法，其中栅极结构形成在第一导电类型的半导体本体上。门结构被形成为包括其上的保护盖并且限定与其横向相邻的源/漏区。在栅极结构和源极/漏极区域中进行第二导电类型的第一注入。半导体本体被蚀刻以形成基本上对准栅极结构的凹槽，其中第一注入从源极/漏极区域移除。通过选择性外延生长植入或生长源极/漏极区域。

8. 发明申请

US20080230815A1 Mitigation of gate to contact capacitance in CMOS flow 有权
标题翻译：栅极接触电容在CMOS流中的缓解
公开(公告)号：US20080230815A1
公开(公告)日：2008-09-25
申请号：US11726253
申请日：2007-03-21
申请人： Shashank Sureshchandra Ekbote , Borna Obradovic , Lindsey Hall , Craig Huffman , Ajith Varghese
发明人： Shashank Sureshchandra Ekbote , Borna Obradovic , Lindsey Hall , Craig Huffman , Ajith Varghese
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7833 , H01L21/76804 , H01L21/76897 , H01L29/6656 , H01L29/6659 , Y02P80/30
摘要： Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics.
摘要翻译：主要是氧化物而不是氮化物的侧壁间隔物邻近CMOS晶体管的栅极叠层形成。单独的侧壁间隔物位于栅极堆叠的导电栅电极和晶体管的导电接触之间。因此，取决于插入的侧壁间隔物的介电常数，可以在栅电极和接触之间产生电容。因此，从具有比氮化物更低的介电常数的氧化物形成侧壁间隔物减轻了另外可能在这些特征之间产生的电容。这种电容至少是不利的，因为它可以抑制晶体管的切换速度。因此，如本文所述的形成侧壁间隔件可以通过减少具有不令人满意的切换速度和/或其它不期望的性能特征的设备的数量来减轻产量损失。

9. 发明申请

US20060226453A1 Methods of forming stress enhanced PMOS structures 审中-公开
标题翻译：形成应力增强的PMOS结构的方法
公开(公告)号：US20060226453A1
公开(公告)日：2006-10-12
申请号：US11105215
申请日：2005-04-12
申请人： Everett Wang , Martin Giles , Philippe Matagne , Roza Kotlyar , Borna Obradovic , Mark Stettler
发明人： Everett Wang , Martin Giles , Philippe Matagne , Roza Kotlyar , Borna Obradovic , Mark Stettler
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/045 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： Methods of forming a microelectronic structure are described. Embodiments of those methods include providing a gate structure disposed on a substrate comprising at least one recess, wherein a channel region is in a direction, and then forming a compressive layer in the at least one recess.
摘要翻译：描述形成微电子结构的方法。这些方法的实施例包括提供设置在包括至少一个凹部的基底上的栅极结构，其中沟道区在<110>方向上，然后在该至少一个凹部中形成压缩层。

10. 发明申请

US20050130379A1 Method and structure to decrease area capacitance within a buried insulator device 失效
标题翻译：降低埋层绝缘体内部面积电容的方法和结构
公开(公告)号：US20050130379A1
公开(公告)日：2005-06-16
申请号：US10806609
申请日：2004-03-22
申请人： Mark Stettler , Borna Obradovic , Martin Giles , Rafael Rios
发明人： Mark Stettler , Borna Obradovic , Martin Giles , Rafael Rios
IPC分类号： H01L21/336 , H01L27/01 , H01L27/12 , H01L29/786 , H01L31/0392
CPC分类号： B82Y10/00 , H01L29/66772 , H01L29/78603 , H01L29/78606
摘要： Method and structure to decrease area capacitance within a buried insulator device structure are disclosed. A portion of the substrate layer of a buried insulator structure opposite the insulator layer from the gate is doped with the same doping polarity as the source and drain regions of the device, to provide reduced area capacitance. Such doping may be limited to portions of the substrate which are not below the gate.
摘要翻译：公开了减少掩埋绝缘体器件结构内的面积电容的方法和结构。与栅极的绝缘体层相对的掩埋绝缘体结构的衬底层的一部分掺杂有与器件的源极和漏极区相同的掺杂极性，以提供减小的面积电容。这种掺杂可以限于不在栅极下方的衬底的部分。

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