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1. 发明申请

US20080230815A1 Mitigation of gate to contact capacitance in CMOS flow 有权
标题翻译：栅极接触电容在CMOS流中的缓解
公开(公告)号：US20080230815A1
公开(公告)日：2008-09-25
申请号：US11726253
申请日：2007-03-21
申请人： Shashank Sureshchandra Ekbote , Borna Obradovic , Lindsey Hall , Craig Huffman , Ajith Varghese
发明人： Shashank Sureshchandra Ekbote , Borna Obradovic , Lindsey Hall , Craig Huffman , Ajith Varghese
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7833 , H01L21/76804 , H01L21/76897 , H01L29/6656 , H01L29/6659 , Y02P80/30
摘要： Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics.
摘要翻译：主要是氧化物而不是氮化物的侧壁间隔物邻近CMOS晶体管的栅极叠层形成。单独的侧壁间隔物位于栅极堆叠的导电栅电极和晶体管的导电接触之间。因此，取决于插入的侧壁间隔物的介电常数，可以在栅电极和接触之间产生电容。因此，从具有比氮化物更低的介电常数的氧化物形成侧壁间隔物减轻了另外可能在这些特征之间产生的电容。这种电容至少是不利的，因为它可以抑制晶体管的切换速度。因此，如本文所述的形成侧壁间隔件可以通过减少具有不令人满意的切换速度和/或其它不期望的性能特征的设备的数量来减轻产量损失。

2. 发明授权

US08119470B2 Mitigation of gate to contact capacitance in CMOS flow 有权
标题翻译：栅极接触电容在CMOS流中的缓解
公开(公告)号：US08119470B2
公开(公告)日：2012-02-21
申请号：US11726253
申请日：2007-03-21
申请人： Shashank Sureshchandra Ekbote , Borna Obradovic , Lindsey Hall , Craig Huffman , Ajith Varghese
发明人： Shashank Sureshchandra Ekbote , Borna Obradovic , Lindsey Hall , Craig Huffman , Ajith Varghese
IPC分类号： H01L21/338 , H01L21/336 , H01L21/4763
CPC分类号： H01L29/7833 , H01L21/76804 , H01L21/76897 , H01L29/6656 , H01L29/6659 , Y02P80/30
摘要： Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics.
摘要翻译：主要是氧化物而不是氮化物的侧壁间隔物邻近CMOS晶体管的栅极叠层形成。单独的侧壁间隔物位于栅极堆叠的导电栅电极和晶体管的导电接触之间。因此，取决于插入的侧壁间隔物的介电常数，可以在栅电极和接触之间产生电容。因此，从具有比氮化物更低的介电常数的氧化物形成侧壁间隔物减轻了另外可能在这些特征之间产生的电容。这种电容至少是不利的，因为它可以抑制晶体管的切换速度。因此，如本文所述的形成侧壁间隔件可以通过减少具有不令人满意的切换速度和/或其它不期望的性能特征的设备的数量来减轻产量损失。

3. 发明申请

US20120256270A1 DUAL METAL GATES USING ONE METAL TO ALTER WORK FUNCTION OF ANOTHER METAL 审中-公开
标题翻译：使用一种金属的双金属门可以改善其他金属的工作功能
公开(公告)号：US20120256270A1
公开(公告)日：2012-10-11
申请号：US13525840
申请日：2012-06-18
申请人： Byoung H. Lee , Sang Ho Bae , Kisik Choi , Rino Choi , Craig Huffman , Prashant Majhi , Jong Hoan Sim , Seung-Chul Song , Zhibo Zhang
发明人： Byoung H. Lee , Sang Ho Bae , Kisik Choi , Rino Choi , Craig Huffman , Prashant Majhi , Jong Hoan Sim , Seung-Chul Song , Zhibo Zhang
IPC分类号： H01L27/092
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/4966 , H01L29/517
摘要： Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process.
摘要翻译：公开了形成双金属栅极和形成的栅极的方法。一种方法可以包括在第一金属层上的栅极电介质层和第二金属（例如，PMOS金属）层上形成第一金属（例如，NMOS金属）层，由此第二金属层改变第一金属的功函数层（形成PMOS金属）。该方法可以移除第二金属层的一部分以暴露第一区域中的第一金属层; 在第一区域中的暴露的第一金属层上和在第二区域中的第二金属层上形成硅层; 并在第一和第二区域形成双金属栅极。由于栅极电介质层被第一金属连续覆盖，所以不会受到金属蚀刻工艺的损害。

4. 发明授权

US08236686B2 Dual metal gates using one metal to alter work function of another metal 失效
标题翻译：双金属门使用一种金属来改变另一种金属的功能
公开(公告)号：US08236686B2
公开(公告)日：2012-08-07
申请号：US12129984
申请日：2008-05-30
申请人： Byoung H. Lee , Sang Ho Bae , Kisik Choi , Rino Choi , Craig Huffman , Prashant Majhi , Jong Hoan Sim , Seung-Chul Song , Zhibo Zhang
发明人： Byoung H. Lee , Sang Ho Bae , Kisik Choi , Rino Choi , Craig Huffman , Prashant Majhi , Jong Hoan Sim , Seung-Chul Song , Zhibo Zhang
IPC分类号： H01L21/44
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/4966 , H01L29/517
摘要： Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process.
摘要翻译：公开了形成双金属栅极和形成的栅极的方法。一种方法可以包括在第一金属层上的栅极电介质层和第二金属（例如，PMOS金属）层上形成第一金属（例如，NMOS金属）层，由此第二金属层改变第一金属的功函数层（形成PMOS金属）。该方法可以移除第二金属层的一部分以暴露第一区域中的第一金属层; 在第一区域中的暴露的第一金属层上和在第二区域中的第二金属层上形成硅层; 并在第一和第二区域形成双金属栅极。由于栅极电介质层被第一金属连续覆盖，所以不会受到金属蚀刻工艺的损害。

5. 发明申请

US20060160312A1 GATE ELECTRODE FOR FINFET DEVICE 有权
标题翻译： FINFET器件的栅极电极
公开(公告)号：US20060160312A1
公开(公告)日：2006-07-20
申请号：US11039173
申请日：2005-01-20
申请人： Nirmal Chaudhary , Thomas Schulz , Weize Xiong , Craig Huffman
发明人： Nirmal Chaudhary , Thomas Schulz , Weize Xiong , Craig Huffman
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L29/66795 , H01L29/785
摘要： In a method of forming a semiconductor device, a self-planarizing conductive layer is formed over a substrate that includes a topography having sharp drop-offs. The self-planarizing conductive layer is characterized by a substantially flatter surface than the underlying topography. As a result of the self-planarizing layer, a masking layer having a more uniform thickness may be formed over the conductive layer. Because the masking layer has a more uniform thickness, the masking layer may easily be patterned without causing damage to the underlying materials. These techniques may be used to fabricate, among other things, a FinFET without parasitic spacers formed around the fins and the source/drain regions.
摘要翻译：在形成半导体器件的方法中，在包括具有锐利掉落的形貌的衬底上形成自平面化导电层。自平坦化导电层的特征在于比底层形貌基本上更平坦的表面。作为自平坦化层的结果，可以在导电层上形成具有更均匀厚度的掩模层。由于掩模层具有更均匀的厚度，所以掩蔽层可以容易地被图案化，而不会对下面的材料造成损害。除了别的以外，这些技术可以用于制造没有在鳍片和源极/漏极区域周围形成的寄生间隔物的FinFET。

6. 发明授权

US08483412B2 Variable pattern hanging microphone system with remote polar control 有权
标题翻译：可变图案悬挂麦克风系统与远程极性控制
公开(公告)号：US08483412B2
公开(公告)日：2013-07-09
申请号：US12783396
申请日：2010-05-19
申请人： Kelly Statham , Craig Huffman
发明人： Kelly Statham , Craig Huffman
IPC分类号： H04R17/02 , H04R19/04 , H04R17/00 , H04R19/00
CPC分类号： H04R3/005 , H04R1/04 , H04R1/08 , H04R1/326 , H04R2201/021 , H04R2420/01 , H04R2420/09 , H04R2430/20
摘要： A microphone system includes a microphone and a control device external to the microphone. The microphone includes at least two capacitor capsules or one dual-sided capsule. The control device is capable of varying the polar pattern of the microphone over a two-conductor shielded cable or wirelessly. The microphone system may include an anti-rotational positioning mount for the microphone.
摘要翻译：麦克风系统包括麦克风和麦克风外部的控制装置。麦克风包括至少两个电容器胶囊或一个双面胶囊。控制装置能够通过双导体屏蔽电缆或无线地改变麦克风的极性图案。麦克风系统可以包括用于麦克风的防旋转定位支架。

7. 发明授权

US07737015B2 Formation of fully silicided gate with oxide barrier on the source/drain silicide regions 有权
标题翻译：在源极/漏极硅化物区域形成具有氧化物势垒的完全硅化栅极
公开(公告)号：US07737015B2
公开(公告)日：2010-06-15
申请号：US11711297
申请日：2007-02-27
申请人： Puneet Kohli , Craig Huffman , Manfred Ramin
发明人： Puneet Kohli , Craig Huffman , Manfred Ramin
IPC分类号： H01L21/3205
CPC分类号： H01L21/28097 , H01L21/32105 , H01L21/823443 , H01L29/4975 , H01L29/66507 , H01L29/66545
摘要： A simple and cost effective method of forming a fully silicided (FUSI) gate of a MOS transistor is disclosed. In one example, the method comprises forming a nitride hardmask overlying a polysilicon gate, forming an S/D silicide in source/drain regions of the transistor, oxidizing a portion of the S/D silicide to form an oxide barrier overlying the S/D silicide in the source/drain regions, removing the nitride hardmask from the polysilicon gate, and forming a gate silicide such as by deposition of a gate silicide metal over the polysilicon gate and the oxide barrier in the source/drain regions to form a fully silicided (FUSI) gate in the transistor. Thus, the oxide barrier protects the source/drain regions from additional silicide formation by the gate silicide metal formed thereafter. The method may further comprise selectively removing the oxide barrier in the source/drain regions after forming the fully silicided (FUSI) gate.
摘要翻译：公开了一种形成MOS晶体管的完全硅化（FUSI）栅极的简单且成本有效的方法。在一个示例中，该方法包括形成覆盖多晶硅栅极的氮化物硬掩模，在晶体管的源极/漏极区域中形成S / D硅化物，氧化S / D硅化物的一部分以形成覆盖S / D的氧化物屏障在源极/漏极区域中的硅化物，从多晶硅栅极去除氮化物硬掩模，以及形成栅极硅化物，例如通过在多晶硅栅极上沉积栅极硅化物金属和在源极/漏极区域中的氧化物势垒形成完全硅化物（FUSI）栅极。因此，氧化物屏障通过之后形成的栅极硅化物金属保护源极/漏极区域免于另外的硅化物形成。该方法还可以包括在形成完全硅化（FUSI）栅极之后选择性地去除源极/漏极区域中的氧化物势垒。

8. 发明授权

US07094650B2 Gate electrode for FinFET device 有权
标题翻译： FinFET器件用栅极
公开(公告)号：US07094650B2
公开(公告)日：2006-08-22
申请号：US11039173
申请日：2005-01-20
申请人： Nirmal Chaudhary , Thomas Schulz , Weize Xiong , Craig Huffman
发明人： Nirmal Chaudhary , Thomas Schulz , Weize Xiong , Craig Huffman
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L29/66795 , H01L29/785
摘要： In a method of forming a semiconductor device, a self-planarizing conductive layer is formed over a substrate that includes a topography having sharp drop-offs. The self-planarizing conductive layer is characterized by a substantially flatter surface than the underlying topography. As a result of the self-planarizing layer, a masking layer having a more uniform thickness may be formed over the conductive layer. Because the masking layer has a more uniform thickness, the masking layer may easily be patterned without causing damage to the underlying materials. These techniques may be used to fabricate, among other things, a FinFET without parasitic spacers formed around the fins and the source/drain regions.
摘要翻译：在形成半导体器件的方法中，在包括具有锐利掉落的形貌的衬底上形成自平面化导电层。自平坦化导电层的特征在于比底层形貌基本上更平坦的表面。作为自平坦化层的结果，可以在导电层上形成具有更均匀厚度的掩模层。由于掩模层具有更均匀的厚度，所以掩蔽层可以容易地被图案化，而不会对下面的材料造成损害。除了别的以外，这些技术可以用于制造没有在鳍片和源极/漏极区域周围形成的寄生间隔物的FinFET。

9. 发明申请

US20100296674A1 VARIABLE PATTERN HANGING MICROPHONE SYSTEM WITH REMOTE POLAR CONTROL 有权
标题翻译：具有远程极性控制的可变图案悬挂麦克风系统
公开(公告)号：US20100296674A1
公开(公告)日：2010-11-25
申请号：US12783396
申请日：2010-05-19
申请人： Kelly Statham , Craig Huffman
发明人： Kelly Statham , Craig Huffman
IPC分类号： H04R3/00 , H04R25/00 , H04B1/00 , H04R1/02
CPC分类号： H04R3/005 , H04R1/04 , H04R1/08 , H04R1/326 , H04R2201/021 , H04R2420/01 , H04R2420/09 , H04R2430/20
摘要： A microphone system includes a microphone and a control device external to the microphone. The microphone includes at least two capacitor capsules or one dual-sided capsule. The control device is capable of varying the polar pattern of the microphone over a two-conductor shielded cable or wirelessly. The microphone system may include an anti-rotational positioning mount for the microphone.
摘要翻译：麦克风系统包括麦克风和麦克风外部的控制装置。麦克风包括至少两个电容器胶囊或一个双面胶囊。控制装置能够通过双导体屏蔽电缆或无线地改变麦克风的极性图案。麦克风系统可以包括用于麦克风的防旋转定位支架。

10. 发明申请

US20090294867A1 DUAL METAL GATES USING ONE METAL TO ALTER WORK FUNCTION OF ANOTHER METAL 失效
标题翻译：使用一种金属的双金属门可以改善其他金属的工作功能
公开(公告)号：US20090294867A1
公开(公告)日：2009-12-03
申请号：US12129984
申请日：2008-05-30
申请人： Byoung H. Lee , Sang Ho Bae , Kisik Choi , Rino Choi , Craig Huffman , Prashant Majhi , Jong Hoan Sim , Seung-Chul Song , Zhibo Zhang
发明人： Byoung H. Lee , Sang Ho Bae , Kisik Choi , Rino Choi , Craig Huffman , Prashant Majhi , Jong Hoan Sim , Seung-Chul Song , Zhibo Zhang
IPC分类号： H01L29/49 , H01L21/28
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/4966 , H01L29/517
摘要： Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process.
摘要翻译：公开了形成双金属栅极和形成的栅极的方法。一种方法可以包括在第一金属层上的栅极电介质层和第二金属（例如，PMOS金属）层上形成第一金属（例如，NMOS金属）层，由此第二金属层改变第一金属层（形成PMOS金属）。该方法可以移除第二金属层的一部分以暴露第一区域中的第一金属层; 在第一区域中的暴露的第一金属层上和在第二区域中的第二金属层上形成硅层; 并在第一和第二区域形成双金属栅极。由于栅极电介质层被第一金属连续覆盖，所以不会受到金属蚀刻工艺的损害。

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