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1. 发明授权

US08940634B2 Overlapping contacts for semiconductor device 有权
标题翻译：半导体器件重叠触点
公开(公告)号：US08940634B2
公开(公告)日：2015-01-27
申请号：US13171657
申请日：2011-06-29
申请人： Brett H. Engel , Lindsey Hall , David F. Hilscher , Randolph F. Knarr , Steven R. Soss , Jin Z. Wallner
发明人： Brett H. Engel , Lindsey Hall , David F. Hilscher , Randolph F. Knarr , Steven R. Soss , Jin Z. Wallner
IPC分类号： H01L23/528 , H01L21/768 , H01L23/522
CPC分类号： H01L23/528 , H01L21/76816 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.
摘要翻译：在半导体器件中形成重叠触点的方法包括在电介质层中形成第一触点; 蚀刻电介质层以形成与第一接触相邻的凹部，并且在蚀刻介电层的同时去除第一接触的顶部，其中在电介质层中形成凹部之后第一接触的底部保留在电介质层中 ; 以及在与所述第一接触件的底部相邻的所述凹部中形成第二触点，并且在所述第一接触件的底部的顶表面的顶部上形成第二接触。

2. 发明授权

US09625557B2 Work function calibration of a non-contact voltage sensor 有权
公开(公告)号：US09625557B2
公开(公告)日：2017-04-18
申请号：US14285059
申请日：2014-05-22
申请人： M. Brandon Steele , Steven R. Soss
发明人： M. Brandon Steele , Steven R. Soss
IPC分类号： G01R35/00 , G01R31/265
CPC分类号： G01R35/005 , G01R31/265
摘要： A method and a system for calibrating the work function or surface potential of a non-contact voltage sensor probe tip. The method includes preparing one or more reference sample surfaces and a reference non-contact voltage sensor probe tip to have stable surface potentials, measuring the voltage between the reference samples and the reference sensor probe tip, measuring the voltage between a point on a non-reference sample surface and the reference sensor probe tip, measuring the voltage between the same point on the non-reference sample surface and a non-reference non-contact voltage sensor probe tip, and determining a surface potential correction factor for the non-reference, non-contact voltage sensor.

3. 发明申请

US20150338494A1 WORK FUNCTION CALIBRATION OF A NON-CONTACT VOLTAGE SENSOR 有权
标题翻译：非接触式电压传感器的工作功能校准
公开(公告)号：US20150338494A1
公开(公告)日：2015-11-26
申请号：US14285059
申请日：2014-05-22
申请人： M. Brandon Steele , Steven R. Soss
发明人： M. Brandon Steele , Steven R. Soss
IPC分类号： G01R35/00 , G01R31/265
CPC分类号： G01R35/005 , G01R31/265
摘要： A method and a system for calibrating the work function or surface potential of a non-contact voltage sensor probe tip are provided. The method includes preparing one or more reference sample surfaces and a reference non-contact voltage sensor probe tip to have stable surface potentials, measuring the voltage between the reference samples and the reference sensor probe tip, measuring the voltage between a point on a non-reference sample surface and the reference sensor probe tip, measuring the voltage between the same point on the non-reference sample surface and a non-reference non-contact voltage sensor probe tip, and determining a surface potential correction factor for the non-reference, non-contact voltage sensor.
摘要翻译：提供了用于校准非接触式电压传感器探针尖端的功函数或表面电位的方法和系统。该方法包括制备一个或多个参考样品表面和参考非接触电压传感器探针尖端以具有稳定的表面电位，测量参考样品和参考传感器探针尖端之间的电压，测量非极性点之间的电压，参考样品表面和参考传感器探针尖端，测量非参考样品表面上的相同点和非参考非接触电压传感器探针尖端之间的电压，以及确定非参考的表面电位校正因子，非接触式电压传感器。

4. 发明授权

US08853045B2 Low capacitance precision resistor 有权
标题翻译：低电容精密电阻
公开(公告)号：US08853045B2
公开(公告)日：2014-10-07
申请号：US13282224
申请日：2011-10-26
申请人： Steven R. Soss
发明人： Steven R. Soss
IPC分类号： H01L21/20 , H01L27/08 , H01L29/8605 , H01L49/02
CPC分类号： H01L27/0802 , H01L28/20 , H01L29/8605
摘要： A precision low capacitance resistor is formed, e.g., in a bulk substrate. An embodiment includes forming a source/drain region on a substrate, patterning a portion of the source/drain region to form segments, etching the segments to substantially separate an upper section of each segment from a lower section of each segment, and filling the space between the segments with an insulating material. The resulting structure maintains electrical connection between the segments at end pads, but separates the resistor segments from the bottom substrate, thereby avoiding capacitive coupling with the substrate.
摘要翻译：精密的低电容电阻器例如在体衬底中形成。一个实施例包括在衬底上形成源极/漏极区域，图案化源/漏区域的一部分以形成段，蚀刻段以将每个段的上部部分与每个段的下部分基本上分离，并填充空间在具有绝缘材料的段之间。所得到的结构保持端部焊盘处的段之间的电连接，但是将电阻器段与底部衬底分开，从而避免与衬底的电容耦合。

5. 发明授权

US08071457B2 Low capacitance precision resistor 有权
标题翻译：低电容精密电阻
公开(公告)号：US08071457B2
公开(公告)日：2011-12-06
申请号：US12683770
申请日：2010-01-07
申请人： Steven R. Soss
发明人： Steven R. Soss
IPC分类号： H01L21/20
CPC分类号： H01L27/0802 , H01L28/20 , H01L29/8605
摘要： A precision low capacitance resistor is formed, e.g., in a bulk substrate. An embodiment includes forming a source/drain region on a substrate, patterning a portion of the source/drain region to form segments, etching the segments to substantially separate an upper section of each segment from a lower section of each segment, and filling the space between the segments with an insulating material. The resulting structure maintains electrical connection between the segments at end pads, but separates the resistor segments from the bottom substrate, thereby avoiding capacitive coupling with the substrate.
摘要翻译：精密的低电容电阻器例如在体衬底中形成。一个实施例包括在衬底上形成源极/漏极区域，图案化源/漏区域的一部分以形成段，蚀刻段以将每个段的上部部分与每个段的下部分基本上分离，并填充空间在具有绝缘材料的段之间。所得到的结构保持端部焊盘处的段之间的电连接，但是将电阻器段与底部衬底分离，从而避免与衬底的电容耦合。

6. 发明申请

US20110163417A1 METHOD TO DYNAMICALLY TUNE PRECISION RESISTANCE 有权
标题翻译：动态调节精度电阻的方法
公开(公告)号：US20110163417A1
公开(公告)日：2011-07-07
申请号：US12683759
申请日：2010-01-07
申请人： Steven R. Soss , Andreas Knorr
发明人： Steven R. Soss , Andreas Knorr
IPC分类号： H01L29/8605 , H01L21/02
CPC分类号： H01L28/20
摘要： A precision resistor is formed with a controllable resistance to compensate for variations that occur with temperature. An embodiment includes forming a resistive semiconductive element having a width and a length on a substrate, patterning an electrically conductive line across the width of the resistive semiconductive element, but electrically isolated therefrom, and forming a depletion channel in the resistive semiconductive element under the electrically conductive line to control the resistance value of the resistive semiconductive element. The design enables dynamic adjustment of the resistance, thereby improving the reliability of the resistor or allowing for resistance modification during final packaging.
摘要翻译：形成具有可控电阻的精密电阻器，以补偿随温度发生的变化。一个实施例包括形成在衬底上具有宽度和长度的电阻半导体元件，跨越电阻半导体元件的宽度图形化导电线，但与之电隔离，并且在电气半导体元件下方形成耗尽沟道导线来控制电阻半导体元件的电阻值。该设计能够动态调节电阻，从而提高电阻器的可靠性或允许最终封装期间的电阻修改。

7. 发明授权

US07183162B1 Method of forming non-volatile memory cell using sacrificial pillar spacers and non-volatile memory cell formed according to the method 有权
标题翻译：使用牺牲柱间隔物和根据该方法形成的非易失性存储单元形成非易失性存储单元的方法
公开(公告)号：US07183162B1
公开(公告)日：2007-02-27
申请号：US11284982
申请日：2005-11-21
申请人： Steven R. Soss , Krishna Parat
发明人： Steven R. Soss , Krishna Parat
IPC分类号： H01L21/8247
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/66825 , H01L29/7881
摘要： A method of forming a microelectronic non-volatile memory cell, a memory cell formed according to the method, and a system including the memory cell. The method comprises: providing a substrate; providing a pair of spaced apart isolation bodies on the substrate, the isolation bodies including respective raised isolation portions, providing the pair comprising providing a buffer layer on the substrate; providing pillar spacers on side walls of the raised isolation portions; removing the buffer layer after providing the pillar spacers; removing the pillar spacers during removing the buffer layer; providing a tunnel dielectric on the surface of the substrate after removing the buffer layer; providing a floating gate on the tunnel dielectric; reducing a height of the isolation bodies to yield corresponding isolation regions; providing source and drain regions on opposite sides of the floating gate; providing an interpoly dielectric on the floating gate; and providing a control gate on the interpoly dielectric to yield the memory cell.
摘要翻译：形成微电子非易失性存储单元的方法，根据该方法形成的存储单元和包括存储单元的系统。该方法包括：提供衬底; 在所述衬底上提供一对间隔开的隔离体，所述隔离体包括相应的凸起隔离部分，提供所述对，包括在所述衬底上提供缓冲层; 在凸起隔离部分的侧壁上提供柱状间隔物; 在提供柱间隔物之后去除缓冲层; 在移除缓冲层期间移除柱状间隔物; 在去除缓冲层之后在衬底的表面上提供隧道电介质; 在隧道电介质上提供浮动栅极; 降低隔离体的高度以产生相应的隔离区; 在浮动栅极的相对侧上提供源极和漏极区域; 在所述浮动栅极上提供互补电介质; 以及在所述互聚电介质上提供控制栅极以产生所述存储单元。

8. 发明授权

US5956604A Ohmic contact to Gallium Arsenide using epitaxially deposited Cobalt Digermanide 失效
标题翻译：使用外延沉积的钴镍化合物与砷化镓的欧姆接触
公开(公告)号：US5956604A
公开(公告)日：1999-09-21
申请号：US889608
申请日：1997-07-08
申请人： Sabrina L. Lee , Kevin E. Mello , Steven R. Soss , Toh-Ming Lu , Shyam P. Murarka
发明人： Sabrina L. Lee , Kevin E. Mello , Steven R. Soss , Toh-Ming Lu , Shyam P. Murarka
IPC分类号： C30B23/02 , H01L21/285 , H01L29/45 , H01L21/28
CPC分类号： H01L29/452 , C30B23/02 , C30B29/52 , H01L21/28575
摘要： A partially ionized beam (PIB) deposition technique is used to heteroepitally deposit a thin film of CoGe.sub.2 (001) on GaAs (100) substrates 14. The resulting epitaxial arrangement is CoGe.sub.2 (001) GaAs (100). The best epitaxial layer is obtained with an ion energy 1100 eV to 1200 eV and with a substrate temperature of approximately 280.degree. Centigrade. The substrate wafers are treated only by immersion in HF:H.sub.2 O 1:10 immediately prior to deposition of the epitaxial layer. Contacts grown at these optimal conditions display ohmic behavior, while contacts grown at higher or lower substrate temperatures exhibit rectifying behavior. Epitaxial formation of a high melting point, low resistivity cobalt germanide phase results in the formation of a stable contact to n-GaAs.
摘要翻译：使用部分离子束（PIB）沉积技术在GaAs（100）衬底14上异质外延沉积CoGe2（001）薄膜。所得到的外延排列是CoGe2（001）GaAs（100）。获得最佳外延层，其离子能量为1100eV至1200eV，衬底温度为约280℃。在沉积外延层之前，仅在浸入HF:H2O 1:10中处理衬底晶片。在这些最佳条件下生长的接触显示欧姆行为，而在更高或更低的底物温度下生长的接触表现出整流行为。外延形成高熔点，低电阻率的锗化锗相导致与n-GaAs的稳定接触的形成。

9. 发明授权

US08709882B2 Method to dynamically tune precision resistance 有权
标题翻译：动态调整精度电阻的方法
公开(公告)号：US08709882B2
公开(公告)日：2014-04-29
申请号：US12683759
申请日：2010-01-07
申请人： Steven R. Soss , Andreas Knorr
发明人： Steven R. Soss , Andreas Knorr
IPC分类号： H01L21/00
CPC分类号： H01L28/20
摘要： A precision resistor is formed with a controllable resistance to compensate for variations that occur with temperature. An embodiment includes forming a resistive semiconductive element having a width and a length on a substrate, patterning an electrically conductive line across the width of the resistive semiconductive element, but electrically isolated therefrom, and forming a depletion channel in the resistive semiconductive element under the electrically conductive line to control the resistance value of the resistive semiconductive element. The design enables dynamic adjustment of the resistance, thereby improving the reliability of the resistor or allowing for resistance modification during final packaging.
摘要翻译：形成具有可控电阻的精密电阻器，以补偿随温度发生的变化。一个实施例包括形成在衬底上具有宽度和长度的电阻半导体元件，跨越电阻半导体元件的宽度图形化导电线，但与之电隔离，并且在电气半导体元件下方形成耗尽沟道导线来控制电阻半导体元件的电阻值。该设计能够动态调节电阻，从而提高电阻器的可靠性或允许最终封装期间的电阻修改。

10. 发明申请

US20120068234A1 METHOD FOR SELF-ALIGNING A STOP LAYER TO A REPLACEMENT GATE FOR SELF-ALIGNED CONTACT INTEGRATION 审中-公开
标题翻译：将自动对准停止层的方法用于自对准接触集成的替换门
公开(公告)号：US20120068234A1
公开(公告)日：2012-03-22
申请号：US13239874
申请日：2011-09-22
申请人： Steven R. Soss , Andreas Knorr
发明人： Steven R. Soss , Andreas Knorr
IPC分类号： H01L29/772
CPC分类号： H01L29/4966 , H01L21/28114 , H01L21/76834 , H01L21/76895 , H01L21/76897 , H01L29/517 , H01L29/66545 , H01L29/6656 , Y10S438/926
摘要： Semiconductor devices with replacement gate electrodes and integrated self aligned contacts are formed with enhanced gate dielectric layers and improved electrical isolation properties between the gate line and a contact. Embodiments include forming a removable gate electrode on a substrate, forming a self aligned contact stop layer over the electrode and the substrate, removing a portion of the self aligned contact stop layer over the electrode and the electrode itself leaving an opening, forming a replacement gate electrode of metal, in the opening, transforming an upper portion of the metal into a dielectric layer, and forming a self aligned contact. Embodiments include forming the contact stop layer of a dielectric material, and transforming the upper portion of the metal into a dielectric layer. Embodiments also include forming a hardmask layer over the removable gate electrode to protect the electrode during silicidation in source/drain regions of the semiconductor device.
摘要翻译：具有替换栅电极和集成自对准触点的半导体器件由栅极电介质层和栅极线与触点之间的电隔离特性提高而形成。实施例包括在衬底上形成可移除的栅电极，在电极和衬底之上形成自对准的接触停止层，在电极和电极本身上去除一部分自对准的接触阻挡层，留下开口，形成置换栅极金属的电极，在开口中，将金属的上部转变为电介质层，并形成自对准的接触。实施例包括形成电介质材料的接触停止层，并将金属的上部转化成电介质层。实施例还包括在可移除的栅极电极上形成硬掩模层，以在半导体器件的源极/漏极区域中的硅化期间保护电极。

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