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1. 发明授权

US08890164B1 Apparatus and method for reducing plasma-induced damage in pMOSFETS 有权
标题翻译：用于降低pMOSFETS中等离子体诱导的损伤的装置和方法
公开(公告)号：US08890164B1
公开(公告)日：2014-11-18
申请号：US13416297
申请日：2012-03-09
申请人： Hong-Tsz Pan , Qi Lin , Yun Wu , Bang-Thu Nguyen
发明人： Hong-Tsz Pan , Qi Lin , Yun Wu , Bang-Thu Nguyen
IPC分类号： H01L27/108
CPC分类号： H01L27/0928 , H01L21/823493 , H01L21/823892 , H01L27/0255 , H01L27/088
摘要： A metal oxide semiconductor field effect transistor (MOSFET) for an integrated circuit includes a substrate of a first conductivity type, a first well region of a second conductivity type located in the substrate, and a second well region of the second conductivity type located within the substrate. The second well region is functionally connected to the first well region, and the second well region has a surface area greater than a surface area of the first well region. The MOSFET further includes a source of the first conductivity type located in the first well region, a drain of the first conductivity type located in the first well region, a substrate terminal of the second conductivity type located in the first well region, a gate oxide on a top surface of the first well region, and a gate electrode located on a top surface of the gate oxide.
摘要翻译：用于集成电路的金属氧化物半导体场效应晶体管（MOSFET）包括第一导电类型的衬底，位于衬底中的第二导电类型的第一阱区和位于衬底内的第二导电类型的第二阱区基质。第二阱区域功能上连接到第一阱区域，并且第二阱区域具有大于第一阱区域的表面积的表面积。 MOSFET还包括位于第一阱区域中的第一导电类型的源极，位于第一阱区域中的第一导电类型的漏极，位于第一阱区域中的第二导电类型的衬底端子，栅极氧化物在第一阱区的顶表面上，以及栅电极，位于栅极氧化物的顶表面上。

2. 发明授权

US08878337B1 Integrated circuit structure having a capacitor structured to reduce dishing of metal layers 有权
标题翻译：具有电容器的集成电路结构，其构造为减少金属层的凹陷
公开(公告)号：US08878337B1
公开(公告)日：2014-11-04
申请号：US13186279
申请日：2011-07-19
申请人： Hong-Tsz Pan , Yun Wu , Shuxian Wu , Qi Lin , Bang-Thu Nguyen
发明人： Hong-Tsz Pan , Yun Wu , Shuxian Wu , Qi Lin , Bang-Thu Nguyen
IPC分类号： H01L21/02
CPC分类号： H01L29/94 , H01L21/3212 , H01L21/823842 , H01L27/0629 , H01L29/66181 , H01L29/66545 , H01L29/78
摘要： A method and integrated circuit structure for mitigating metal gate dishing resulting from chemical mechanical polishing. The integrated circuit structure comprises a first area comprising at least one first type device; a second area comprising at least one second type device; a third area comprising at least one capacitor having an uppermost layer of polysilicon, where the capacitor area is greater than a sum of the first and second areas. The method utilizes the polysilicon of the capacitor to mitigate metal gate dishing of a metal gate of at least one device.
摘要翻译：一种用于减轻由化学机械抛光引起的金属栅极凹陷的方法和集成电路结构。集成电路结构包括包括至少一个第一类型装置的第一区域; 第二区域，包括至少一个第二类型装置; 第三区域包括至少一个具有多晶硅最上层的电容器，其中电容器面积大于第一和第二区域的总和。该方法利用电容器的多晶硅来减轻至少一个器件的金属栅极的金属栅极凹陷。

3. 发明授权

US08350365B1 Mitigation of well proximity effect in integrated circuits 有权
标题翻译：减轻集成电路中的良好邻近效应
公开(公告)号：US08350365B1
公开(公告)日：2013-01-08
申请号：US13005680
申请日：2011-01-13
申请人： Yun Wu , Hong-Tsz Pan , Qi Lin , Bang-Thu Nguyen
发明人： Yun Wu , Hong-Tsz Pan , Qi Lin , Bang-Thu Nguyen
IPC分类号： H01L21/4763
CPC分类号： H01L21/266 , H01L21/26513
摘要： A hard implantation mask layer is formed on a semiconductor wafer. An etch mask layer is formed on the hard implantation mask layer and patterned. The hard implantation mask layer is etched to form a well implantation pattern and ions are implanted into the semiconductor wafer to form wells in the semiconductor wafer, in areas where the semiconductor wafer is not covered by the well implantation mask.
摘要翻译：在半导体晶片上形成硬注入掩模层。在硬注入掩模层上形成蚀刻掩模层并进行图案化。蚀刻硬注入掩模层以形成良好注入图案，并且在半导体晶片未被阱注入掩模覆盖的区域中，将离子注入到半导体晶片中以在半导体晶片中形成阱。

4. 发明授权

US07673270B1 Method and apparatus for compensating an integrated circuit layout for mechanical stress effects 有权
标题翻译：用于补偿机械应力影响的集成电路布局的方法和装置
公开(公告)号：US07673270B1
公开(公告)日：2010-03-02
申请号：US11717811
申请日：2007-03-13
申请人： Yan Wang , Nui Chong , Hong-Tsz Pan , Bang-Thu Nguyen , Jonathan Jung-Ching Ho , Qi Lin , Yuhao Luo , Hing Yee Angela Wong , Xin X. Wu , Yuezhen Fan
发明人： Yan Wang , Nui Chong , Hong-Tsz Pan , Bang-Thu Nguyen , Jonathan Jung-Ching Ho , Qi Lin , Yuhao Luo , Hing Yee Angela Wong , Xin X. Wu , Yuezhen Fan
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Method and apparatus for compensating an integrated circuit design for mechanical stress effects. One aspect of the invention relates to designing an integrated circuit. Layout data is obtained that describes layers of the integrated circuit. At least one of the layers is analyzed to detect at least one structure susceptible to damage from mechanical stress. A bias is automatically added to each of the at least one structure to reduce mechanical stress of the at least one structure as fabricated. Augmented layout data is then provided for the integrated circuit.
摘要翻译：用于补偿机械应力作用的集成电路设计的方法和装置。本发明的一个方面涉及集成电路的设计。获得描述集成电路层的布局数据。分析至少一层以检测易受机械应力破坏的至少一种结构。偏置被自动地添加到至少一个结构中的每个结构中，以减少所制造的至少一个结构的机械应力。然后为集成电路提供增强的布局数据。

5. 发明授权

US08063654B2 Apparatus and method for testing of stacked die structure 有权
标题翻译：用于堆叠模具结构测试的装置和方法
公开(公告)号：US08063654B2
公开(公告)日：2011-11-22
申请号：US12505215
申请日：2009-07-17
申请人： Arifur Rahman , Hong-Tsz Pan , Bang-Thu Nguyen
发明人： Arifur Rahman , Hong-Tsz Pan , Bang-Thu Nguyen
IPC分类号： G01R31/26
CPC分类号： G01R31/318544 , H01L2224/16145
摘要： An integrated circuit device includes a stacked die and a base die having probe pads that directly couple to test logic of the base die to implement a scan chain for testing of the integrated circuit device. The base die further includes contacts disposed on a back side of the base die and through-die vias coupled to the contacts and coupled to programmable logic of the base die. The base die also includes a first probe pad configured to couple test input, a second probe pad configured to couple test output, and a third probe pad configured to couple control signals. Test logic of the base die is configured to couple to additional test logic of the stacked die to implement the scan chain. The probe pads are coupled directly to the test logic such that configuration of the programmable logic is not required to implement the scan chain.
摘要翻译：集成电路器件包括堆叠管芯和具有探针焊盘的基座，该探针焊盘直接耦合到基座芯片的测试逻辑，以实现用于集成电路器件测试的扫描链。基模还包括设置在基模的背面上的触点和耦合到触点并连接到基模的可编程逻辑的通孔通孔。基座芯片还包括被配置为耦合测试输入的第一探针焊盘，被配置为耦合测试输出的第二探针焊盘和被配置为耦合控制信号的第三探测焊盘。基准芯片的测试逻辑被配置为耦合到堆叠芯片的附加测试逻辑以实现扫描链。探针焊盘直接耦合到测试逻辑，使得不需要可编程逻辑的配置来实现扫描链。

6. 发明申请

US20110012633A1 APPARATUS AND METHOD FOR TESTING OF STACKED DIE STRUCTURE 有权
标题翻译：用于测试堆叠式结构的装置和方法
公开(公告)号：US20110012633A1
公开(公告)日：2011-01-20
申请号：US12505215
申请日：2009-07-17
申请人： Arifur Rahman , Hong-Tsz Pan , Bang-Thu Nguyen
发明人： Arifur Rahman , Hong-Tsz Pan , Bang-Thu Nguyen
IPC分类号： G01R31/02
CPC分类号： G01R31/318544 , H01L2224/16145
摘要： An integrated circuit device is described that includes a stacked die and a base die having probe pads that directly couple to test logic of the base die so as to implement a scan chain for testing of the integrated circuit device. The base die further includes contacts disposed on a back side of the base die and through-die vias coupled to the contacts and coupled to programmable logic of the base die. In addition, the base die includes a first probe pad configured to couple test input, a second probe pad configured to couple test output and a third probe pad configured to couple control signals. Test logic of the base die is configured to couple to additional test logic of the stacked die so as to implement a scan chain for testing of the integrated circuit device. In accordance with aspects of the present invention, the first probe pad, the second probe pad and the third probe pad are coupled directly to the test logic such that configuration of the programmable logic is not required for coupling the test input, the test output and the control signal between the base die and the stacked die so as to implement the scan chain.
摘要翻译：描述了一种集成电路器件，其包括具有探针焊盘的堆叠管芯和基座管芯，所述探针焊盘直接耦合到所述基座管芯的测试逻辑，以便实现用于所述集成电路器件的测试的扫描链。基模还包括设置在基模的背面上的触点和耦合到触点并连接到基模的可编程逻辑的通孔通孔。此外，基座芯片包括被配置为耦合测试输入的第一探针焊盘，被配置为耦合测试输出的第二探针焊盘和被配置为耦合控制信号的第三探针焊盘。基模的测试逻辑被配置为耦合到堆叠管芯的附加测试逻辑，以便实现用于集成电路器件测试的扫描链。根据本发明的方面，第一探针焊盘，第二探针焊盘和第三探针焊盘直接耦合到测试逻辑，使得不需要可编程逻辑的配置来耦合测试输入，测试输出和基模和堆叠管芯之间的控制信号，以实现扫描链。

7. 发明授权

US6010958A Method for improving the planarization of dielectric layer in the fabrication of metallic interconnects 失效
标题翻译：在金属互连制造中改善电介质层平坦化的方法
公开(公告)号：US6010958A
公开(公告)日：2000-01-04
申请号：US907005
申请日：1997-08-06
申请人： Tung-Po Chen , Bing-Chang Wu , Hong-Tsz Pan
发明人： Tung-Po Chen , Bing-Chang Wu , Hong-Tsz Pan
IPC分类号： H01L21/3105 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/3105 , H01L21/76819 , Y10S438/937
摘要： A method for improving the planarization of a dielectric layer in the fabrication of metallic interconnects wherein a rapid thermal processing operation is used in order to consolidate exposed surfaces of a dielectric layer after local planarization of the dielectric layer. This method avoids damage to the dielectric layer caused during a pre-metal etching operation, and consequently, prevents residual tungsten from becoming lodged in fissures during subsequent tungsten deposition to produce stringers which may cause short circuiting on coming in contact with metal wiring.
摘要翻译：一种在制造金属互连件时改善电介质层的平面化的方法，其中使用快速热处理操作以便在介电层局部平坦化之后固化电介质层的暴露表面。该方法避免了在预金属蚀刻操作期间对介电层的损坏，因此，防止在随后的钨沉积期间残留的钨变成楔形，从而产生可能导致与金属布线接触的短路的桁条。

8. 发明授权

US5902752A Active layer mask with dummy pattern 失效
标题翻译：具有虚拟图案的活动层蒙版
公开(公告)号：US5902752A
公开(公告)日：1999-05-11
申请号：US648618
申请日：1996-05-16
申请人： Shin-Wei Sun , Water Lur , Ming-Tzong Yang , Hong-Tsz Pan
发明人： Shin-Wei Sun , Water Lur , Ming-Tzong Yang , Hong-Tsz Pan
IPC分类号： H01L21/3105 , H01L21/762 , H01L23/528 , H01L27/02 , H01L21/283
CPC分类号： H01L27/0207 , H01L21/31053 , H01L21/76229 , H01L23/528 , H01L2924/0002
摘要： A method of designing an active layer mask with a dummy pattern by computer aided design (CAD) in shallow trench isolation using chemical mechanical polishing (CMP) to achieve global planarization. In this method, an original mask is provided with an active region including a diffusion area pattern, a polysilicon area pattern and a well area pattern. The diffusion area pattern and the polysilicon area pattern are expanded by an area of dimension a and the well area pattern is extended inward and outward to an area of dimension b. The expanded diffusion, polysilicon and well areas form a first pattern area. The first pattern area is subtracted from the whole region to obtain a second pattern area. A third pattern area is obtained by performing an AND operation on a dummy array pattern and the second pattern area. Expanding the third pattern area to an area of dimension c, a fourth pattern area is obtained. Finally an active layer mask with a dummy pattern is obtained by performing an OR operation on the fourth pattern area and the diffusion area pattern.
摘要翻译：通过计算机辅助设计（CAD）在使用化学机械抛光（CMP）的浅沟槽隔离中设计具有虚拟图案的有源层掩模的方法来实现全局平面化。在该方法中，原始掩模设置有包括扩散区域图案，多晶硅区域图案和阱区域图案的有源区域。扩散区域图案和多晶硅区域图案通过尺寸a的面积扩大，并且阱区域图案向内和向外延伸到尺寸为b的区域。扩展的扩散，多晶硅和阱区形成第一模式区域。从整个区域中减去第一图案区域以获得第二图案区域。通过对虚拟阵列图案和第二图案区域执行AND运算来获得第三图案区域。将第三图案区域扩展到尺寸c的区域，获得第四图案区域。最后，通过对第四图案区域和扩散区域图案执行OR运算来获得具有虚拟图案的有源层掩模。

9. 发明授权

US5449644A Process for contact hole formation using a sacrificial SOG layer 失效
标题翻译：使用牺牲SOG层的接触孔形成方法
公开(公告)号：US5449644A
公开(公告)日：1995-09-12
申请号：US181298
申请日：1994-01-13
申请人： Gary Hong , Cheng H. Huang , Ming-Tzong Yang , Hong-Tsz Pan
发明人： Gary Hong , Cheng H. Huang , Ming-Tzong Yang , Hong-Tsz Pan
IPC分类号： H01L21/768 , H01L21/302
CPC分类号： H01L21/76802 , Y10S148/133
摘要： A new method of forming a contact opening by using a sacrificial spin-on-glass layer is described. A semiconductor substrate is provided wherein the surface of the substrate has an uneven topography. A glasseous layer is deposited over the uneven surface of the substrate and reflowed at low temperature whereby the glasseous layer will have a trench shaped surface over the planned contact opening area. The glasseous layer is covered with a spin-on-glass layer wherein the spin-on-glass planarizes the surface of the substrate. The spin-on-glass layer is baked and then covered with a uniform thickness layer of photoresist. The photoresist layer is exposed and developed to form the desired photoresist mask for the contact opening. The exposed spin-on-glass and glasseous layers are etched away to provide the contact opening to the semiconductor substrate. The photoresist layer is stripped and the sacrificial spin-on-glass layer is removed to complete the formation of the contact opening in the manufacture of the integrated circuit.
摘要翻译：描述了通过使用牺牲旋涂玻璃层形成接触开口的新方法。提供半导体衬底，其中衬底的表面具有不平坦的形貌。在基体的不平坦表面上沉积有胶层，并在低温下回流，由此在层叠的接触开口区域上形成沟槽形表面。玻璃层被旋涂玻璃层覆盖，其中旋涂玻璃将基材的表面平坦化。将旋涂玻璃层烘烤，然后用均匀的厚度的光致抗蚀剂层覆盖。光致抗蚀剂层被曝光和显影以形成用于接触开口的所需光刻胶掩模。暴露的旋涂玻璃和玻璃层被蚀刻掉以提供到半导体衬底的接触开口。剥离光致抗蚀剂层，去除牺牲旋涂玻璃层，以在集成电路的制造中完成接触开口的形成。

10. 发明授权

US6156633A Process for forming high temperature stable self-aligned metal silicide layer 失效
标题翻译：形成高温稳定自对准金属硅化物层的工艺
公开(公告)号：US6156633A
公开(公告)日：2000-12-05
申请号：US34261
申请日：1998-03-04
申请人： Hong-Tsz Pan , Tung-Po Chen
发明人： Hong-Tsz Pan , Tung-Po Chen
IPC分类号： H01L21/285 , H01L21/44
CPC分类号： H01L21/28518
摘要： A process for forming high temperature stable self-aligned silicide layer that not only establishes itself smoothly and uniformly despite the use of a high temperature in the siliciding reaction, but also can withstand other subsequent high temperature thermal processing operations and maintaining a stable metal silicide layer profile thereafter. Moreover, desired thickness and uniformity of the metal silicide layer can be obtained by suitably adjusting the amorphous implant parameters, while the use of a titanium nitride cap layer help to stabilize the metal silicide layer during high temperature formation and that a stable and uniform metal silicide layer profile can be ensured even if subsequent high temperature processing operations are performed.
摘要翻译：用于形成高温稳定的自对准硅化物层的方法，其不仅在硅化反应中使用高温使其自身平滑均匀，而且还可以承受其它随后的高温热处理操作并保持稳定的金属硅化物层之后的档案。而且，通过适当地调整非晶态注入参数，可以获得所需的金属硅化物层的厚度和均匀性，而使用氮化钛盖层有助于在高温形成期间稳定金属硅化物层，并且使金属硅化物稳定且均匀即使执行后续的高温处理操作，也可以确保层的轮廓。

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