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1. 发明授权

US07476813B2 Multilayer flip-chip substrate interconnect layout 失效
标题翻译：多层倒装衬底互连布局
公开(公告)号：US07476813B2
公开(公告)日：2009-01-13
申请号：US10438238
申请日：2003-05-14
申请人： Hao Shi , Xingchao Yuan
发明人： Hao Shi , Xingchao Yuan
IPC分类号： H01R12/04 , H05K1/11
CPC分类号： H05K1/112 , H01L23/5384 , H01L23/5386 , H01L2224/16225 , H01L2924/3011 , H05K3/4602 , H05K2201/09627 , H05K2201/10674
摘要： The multilayer substrate includes a plurality of layers. Located within the plurality of layers are a number of vias. Conductive traces connect the vias to form trace/via paths having various topologies, geometries, and/or properties.
摘要翻译：多层基板包括多层。位于多个层内的是多个通孔。导电迹线连接通孔以形成具有各种拓扑，几何形状和/或属性的轨迹/通路。

2. 发明申请

US20060160271A1 Stacked semiconductor module 有权
公开(公告)号：US20060160271A1
公开(公告)日：2006-07-20
申请号：US11378008
申请日：2006-03-16
申请人： Thomas Fox , Sayeh Khalili , Belgacem Haba , David Nguyen , Richard Warmke , Xingchao Yuan
发明人： Thomas Fox , Sayeh Khalili , Belgacem Haba , David Nguyen , Richard Warmke , Xingchao Yuan
IPC分类号： H01L21/50
CPC分类号： G11C5/02 , G11C5/04 , G11C29/08 , G11C2029/4402 , H01L23/5382 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable to identify the integrated circuit dice that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dice and the programmable memory device. The integrated circuit dice of the plurality of integrated circuit dice that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dice.

3. 再颁专利

USRE44019E1 Stacked semiconductor module 有权
标题翻译：堆叠式半导体模块
公开(公告)号：USRE44019E1
公开(公告)日：2013-02-19
申请号：US12605303
申请日：2009-10-23
申请人： Thomas F. Fox , Sayeh Khalili , Belgacem Haba , David Nguyen , Richard Warmke , Xingchao Yuan
发明人： Thomas F. Fox , Sayeh Khalili , Belgacem Haba , David Nguyen , Richard Warmke , Xingchao Yuan
IPC分类号： H01L21/00
CPC分类号： G11C5/02 , G11C5/04 , G11C29/08 , G11C2029/4402 , H01L23/5382 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable to identify the integrated circuit dice that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dice and the programmable memory device. The integrated circuit dice of the plurality of integrated circuit dice that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dice.
摘要翻译：提供了半导体模块，其包括半导体外壳和位于壳体内的多个集成电路芯片。半导体模块还包括位于壳体内的电可耦合到多个集成电路芯片的可编程存储器件。可编程存储器件可编程以识别满足预定标准（例如工作频率要求或核心定时等级）的集成电路芯片。此外，提供了一种用于访问半导体模块的方法。提供上述壳体以包围多个集成电路芯片和可编程存储器件。然后识别满足预定标准的多个集成电路芯片的集成电路芯片。随后编程可编程存储器件以识别所选择的集成电路芯片。

4. 发明授权

US08222714B2 Semiconductor package with embedded spiral inductor 有权
标题翻译：半导体封装带嵌入式螺旋电感
公开(公告)号：US08222714B2
公开(公告)日：2012-07-17
申请号：US12523587
申请日：2008-02-04
申请人： Hao Shi , Jung-Hoon Chun , Xingchao Yuan
发明人： Hao Shi , Jung-Hoon Chun , Xingchao Yuan
IPC分类号： H01L27/08
CPC分类号： H01L23/49838 , H01L23/49822 , H01L23/50 , H01L23/645 , H01L24/05 , H01L2224/0401 , H01L2224/05552 , H01L2224/05553 , H01L2224/05555 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/3011 , H05K1/112 , H05K1/165 , H05K3/4602 , H05K2201/09627 , H05K2201/10674 , H01L2924/00
摘要： In some embodiments, the semiconductor package includes a substrate having multiple layers, from a first layer to a final layer, a die coupled to the first layer, an electrical connector such as a solder ball coupled to the final layer, and a spiral trace disposed and electrically coupled between the die and the electrical connector. Inductance of the spiral trace is selected such that the package has a predetermined impedance. Material, cross-sectional area, number and density of windings, and total overall length of the spiral trace are selected accordingly. In other embodiments, the semiconductor package includes a substrate with multiple layers; a die coupled to the first of the layers; an electrical connector coupled to the final layer; and a spiral trace, in or on the substrate. The spiral trace is near the die, and electrically coupled between the die and the electrical connector.
摘要翻译：在一些实施例中，半导体封装包括具有多个层的衬底，从第一层到最终层，耦合到第一层的管芯，耦合到最终层的焊球等电连接器以及布置在其上的螺旋迹线并且电连接在管芯和电连接器之间。选择螺旋迹线的电感，使得封装具有预定的阻抗。相应地选择材料，横截面积，绕组的数量和密度以及螺旋迹线的总长度。在其他实施例中，半导体封装包括具有多层的衬底; 耦合到第一层的管芯; 耦合到最终层的电连接器; 以及衬底中或衬底上的螺旋迹线。螺旋迹线靠近模具，并且电连接在管芯和电连接器之间。

5. 发明授权

US06720643B1 Stacked semiconductor module 有权
标题翻译：堆叠式半导体模块
公开(公告)号：US06720643B1
公开(公告)日：2004-04-13
申请号：US09792788
申请日：2001-02-22
申请人： Thomas F. Fox , Sayeh Khalili , Belgacem Haba , David Nguyen , Richard Warmke , Xingchao Yuan
发明人： Thomas F. Fox , Sayeh Khalili , Belgacem Haba , David Nguyen , Richard Warmke , Xingchao Yuan
IPC分类号： H01L2302
CPC分类号： G11C5/02 , G11C5/04 , G11C29/08 , G11C2029/4402 , H01L23/5382 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dies positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dies. The programmable memory device is programmable to identify the integrated circuit dies that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dies and the programmable memory device. The integrated circuit dies of the plurality of integrated circuit dies that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dies.
摘要翻译：提供了半导体模块，其包括半导体壳体和位于壳体内的多个集成电路模具。该半导体模块还包括位于壳体内并可电耦合到多个集成电路管芯的可编程存储器件。可编程存储器件可编程以识别满足预定标准（例如工作频率要求或核心定时等级）的集成电路管芯。此外，提供了一种用于访问半导体模块的方法。提供上述壳体以封闭多个集成电路管芯和可编程存储器件。然后识别满足预定标准的多个集成电路管芯的集成电路管芯。随后编程可编程存储器件以识别所选择的集成电路管芯。

6. 发明授权

US07164292B2 Reducing electrical noise during bus turnaround in signal transfer systems 有权
标题翻译：在信号传输系统的公交车周转期间减少电气噪声
公开(公告)号：US07164292B2
公开(公告)日：2007-01-16
申请号：US10866157
申请日：2004-06-12
申请人： Ralf Schmitt , Xingchao Yuan
发明人： Ralf Schmitt , Xingchao Yuan
IPC分类号： H03K19/0175
CPC分类号： H04L25/0272 , H03K19/00361
摘要： Systems and methods for reducing electrical noise generated during bus turnaround in signal transfer systems are provided. These systems include differential drivers having current sources continuously coupled to a signal bus during all operating modes of the drivers. A first transistor of the driver couples a first signal line of the bus to the driver current source and a second transistor of the driver couples a second signal line of the bus to the driver current source. Each transistor receives control signals in accordance with the operating mode of the driver. These control signals continuously and selectively couple the current source to the bus lines in a manner which provides uniform current distribution across the bus during all driver operating modes. The uniform current distribution across the bus minimizes interruptions in driver current dissipation and any effects from self-induced supply noise during signal transfers.
摘要翻译：提供了用于减少信号传输系统中总线周转期间产生的电噪声的系统和方法。这些系统包括在驱动器的所有操作模式期间具有连续耦合到信号总线的电流源的差分驱动器。驱动器的第一晶体管将总线的第一信号线耦合到驱动器电流源，并且驱动器的第二晶体管将总线的第二信号线耦合到驱动器电流源。每个晶体管根据驱动器的工作模式接收控制信号。这些控制信号以在所有驱动器操作模式期间通过总线提供均匀电流分配的方式连续地和选择性地将电流源耦合到总线。总线上均匀的电流分配可以最大限度地减少驱动器电流损耗的中断，并在信号传输期间产生自感应电源噪声的任何影响。

7. 发明授权

US07006932B1 Technique for determining performance characteristics of electronic devices and systems 失效
标题翻译：确定电子设备和系统性能特点的技术
公开(公告)号：US07006932B1
公开(公告)日：2006-02-28
申请号：US10954489
申请日：2004-10-01
申请人： Haw-Jyh Liaw , Xingchao Yuan , Mark A. Horowitz
发明人： Haw-Jyh Liaw , Xingchao Yuan , Mark A. Horowitz
IPC分类号： G01R15/00 , G06F19/00
CPC分类号： G01R31/31708 , G01R23/16 , G01R23/20 , G01R31/31717 , G11C29/02 , G11C29/022 , G11C29/025 , G11C29/50012 , G11C29/56 , G11C29/56012 , G11C2029/5004 , H04B17/309
摘要： A technique for determining performance characteristics of electronic devices and systems is disclosed in one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.
摘要翻译：在一个实施例中公开了一种用于确定电子设备和系统的性能特征的技术，该技术通过在第一传输线上传输的单个脉冲测量第一传输线上的第一响应，然后测量第二响应在至少一个第二传输线上传输的单个脉冲的第一传输线，其中所述至少一个第二传输线基本上与所述第一传输线相邻。然后基于用于确定与第一传输线相关联的性能特性的第一响应和第二响应来确定用于在第一传输线和至少一个第二传输线上传输的最差情况比特序列。

8. 发明授权

US06920402B1 Technique for determining performance characteristics of electronic devices and systems 有权
标题翻译：确定电子设备和系统性能特点的技术
公开(公告)号：US06920402B1
公开(公告)日：2005-07-19
申请号：US09799516
申请日：2001-03-07
申请人： Haw-Jyh Liaw , Xingchao Yuan , Mark A. Horowitz
发明人： Haw-Jyh Liaw , Xingchao Yuan , Mark A. Horowitz
IPC分类号： G01R15/00 , G01R31/317 , G11C29/02 , G11C29/56 , H04B17/00 , G06F19/00
CPC分类号： G01R31/31708 , G01R23/16 , G01R23/20 , G01R31/31717 , G11C29/02 , G11C29/022 , G11C29/025 , G11C29/50012 , G11C29/56 , G11C29/56012 , G11C2029/5004 , H04B17/309
摘要： A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response, and the second response for determining performance characteristics associated with the first transmission line.
摘要翻译：公开了一种用于确定电子设备和系统的性能特征的技术。在一个实施例中，该技术通过从在第一传输线上传输的单个脉冲测量第一传输线上的第一响应，然后在从至少一秒钟传输的单个脉冲测量第一传输线上的第二响应来实现传输线，其中所述至少一个第二传输线基本上与所述第一传输线相邻。然后基于第一响应和用于确定与第一传输线相关联的性能特性的第二响应来确定用于在第一传输线和至少一个第二传输线上的传输的最差情况比特序列。

9. 发明授权

US08674477B2 Semiconductor package with embedded spiral inductor 有权
标题翻译：半导体封装带嵌入式螺旋电感
公开(公告)号：US08674477B2
公开(公告)日：2014-03-18
申请号：US13542444
申请日：2012-07-05
申请人： Hao Shi , Jung-Hoon Chun , Xingchao Yuan
发明人： Hao Shi , Jung-Hoon Chun , Xingchao Yuan
IPC分类号： H01L27/08
CPC分类号： H01L23/49838 , H01L23/49822 , H01L23/50 , H01L23/645 , H01L24/05 , H01L2224/0401 , H01L2224/05552 , H01L2224/05553 , H01L2224/05555 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/3011 , H05K1/112 , H05K1/165 , H05K3/4602 , H05K2201/09627 , H05K2201/10674 , H01L2924/00
摘要： In some embodiments, the semiconductor package includes a substrate having multiple layers, from a first layer to a final layer, a die coupled to the first layer, an electrical connector such as a solder ball coupled to the final layer, and a spiral trace disposed and electrically coupled between the die and the electrical connector. Inductance of the spiral trace is selected such that the package has a predetermined impedance. Material, cross-sectional area, number and density of windings, and total overall length of the spiral trace are selected accordingly. In other embodiments, the semiconductor package includes a substrate with multiple layers; a die coupled to the first of the layers; an electrical connector coupled to the final layer; and a spiral trace, in or on the substrate. The spiral trace is near the die, and electrically coupled between the die and the electrical connector.
摘要翻译：在一些实施例中，半导体封装包括具有多个层的衬底，从第一层到最终层，耦合到第一层的管芯，耦合到最终层的焊球等电连接器以及布置在其上的螺旋迹线并且电连接在管芯和电连接器之间。选择螺旋迹线的电感，使得封装具有预定的阻抗。相应地选择材料，横截面积，绕组的数量和密度以及螺旋迹线的总长度。在其他实施例中，半导体封装包括具有多层的衬底; 耦合到第一层的管芯; 耦合到最终层的电连接器; 以及衬底中或衬底上的螺旋迹线。螺旋迹线靠近模具，并且电连接在管芯和电连接器之间。

10. 发明申请

US20110119425A1 DETACHABLE INTERCONNECT FOR CONFIGURABLE WIDTH MEMORY SYSTEM 审中-公开
标题翻译：可配置的宽度存储器系统的可互连的互连
公开(公告)号：US20110119425A1
公开(公告)日：2011-05-19
申请号：US12675105
申请日：2008-06-30
申请人： Ravindranath Kollipara , Xingchao Yuan , Frank Lambrecht , Ming Li , Richard E. Perego , Qi Lin , David Nguyen , Kyung Suk Oh
发明人： Ravindranath Kollipara , Xingchao Yuan , Frank Lambrecht , Ming Li , Richard E. Perego , Qi Lin , David Nguyen , Kyung Suk Oh
IPC分类号： G06F13/40 , G06F13/20
CPC分类号： G06F13/1668 , H01L2224/16225 , H01L2924/15174 , H01L2924/15311 , H05K1/0237 , H05K1/0295 , H05K1/14 , H05K1/141 , H05K1/147 , H05K3/222 , H05K2201/044 , H05K2201/09954 , H05K2201/10159 , H05K2201/10356
摘要： The disclosure relates to a detachable signalling interconnect apparatus that provides connectivity between two or more components of a memory system in conjunction with different modes of operation of the components. The memory system comprises: a first socket to receive a first memory module; a second socket to receive a second memory module; a detachable signal-interconnect; and a memory controller coupled to the detachable signal-interconnect and configured to define a first mode of operation and a second mode of operation, wherein in the first mode of operation the detachable signal-interconnect is to couple the memory-controller to the first memory module and in the second mode of operation the detachable signal-interconnect is to couple the memory controller to the first memory module and the second memory module.
摘要翻译：本公开涉及一种可拆卸信令互连装置，其提供存储器系统的两个或更多个组件与组件的不同操作模式之间的连接。存储器系统包括：第一插座，用于接收第一存储器模块; 用于接收第二存储器模块的第二插座; 可拆卸的信号互连; 以及存储器控制器，其耦合到所述可拆卸信号互连并且被配置为限定第一操作模式和第二操作模式，其中在所述第一操作模式中，所述可拆卸信号互连将所述存储器控制器耦合到所述第一存储器模块，并且在第二操作模式中，可拆卸信号互连将存储器控制器耦合到第一存储器模块和第二存储器模块。

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