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1. 发明授权

US07363560B1 Circuit for and method of determining the location of a defect in an integrated circuit 有权
标题翻译：确定集成电路中缺陷位置的电路和方法
公开(公告)号：US07363560B1
公开(公告)日：2008-04-22
申请号：US11064129
申请日：2005-02-23
申请人： David Mark , Yuezhen Fan
发明人： David Mark , Yuezhen Fan
IPC分类号： G01R31/28 , G01R31/26 , G06F7/38 , H03K19/096
CPC分类号： H03K19/17764 , G01R31/2853 , G01R31/318516 , G01R31/318519
摘要： According to one aspect of the invention, a circuit for determining the location of a defect in an integrated circuit is described. The circuit comprises a conductor extending from a first node to a second node and a test signal driver coupled to the first node of the conductor. The test signal driver receives a test signal using a first clock signal, while a plurality of detector circuits coupled to the conductor between the first node and the second node to detect an output at the plurality of nodes using a second clock signal. According to other embodiments, circuits for determining the location of a defect in a programmable logic device are disclosed. Finally, various methods for determining the location of a defect in an integrated circuit are described.
摘要翻译：根据本发明的一个方面，描述了一种用于确定集成电路中缺陷位置的电路。电路包括从第一节点延伸到第二节点的导体和耦合到导体的第一节点的测试信号驱动器。测试信号驱动器使用第一时钟信号接收测试信号，而多个检测器电路耦合到第一节点和第二节点之间的导体，以使用第二时钟信号检测多个节点处的输出。根据其他实施例，公开了用于确定可编程逻辑器件中的缺陷位置的电路。最后，描述用于确定集成电路中缺陷位置的各种方法。

2. 发明授权

US07673270B1 Method and apparatus for compensating an integrated circuit layout for mechanical stress effects 有权
标题翻译：用于补偿机械应力影响的集成电路布局的方法和装置
公开(公告)号：US07673270B1
公开(公告)日：2010-03-02
申请号：US11717811
申请日：2007-03-13
申请人： Yan Wang , Nui Chong , Hong-Tsz Pan , Bang-Thu Nguyen , Jonathan Jung-Ching Ho , Qi Lin , Yuhao Luo , Hing Yee Angela Wong , Xin X. Wu , Yuezhen Fan
发明人： Yan Wang , Nui Chong , Hong-Tsz Pan , Bang-Thu Nguyen , Jonathan Jung-Ching Ho , Qi Lin , Yuhao Luo , Hing Yee Angela Wong , Xin X. Wu , Yuezhen Fan
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Method and apparatus for compensating an integrated circuit design for mechanical stress effects. One aspect of the invention relates to designing an integrated circuit. Layout data is obtained that describes layers of the integrated circuit. At least one of the layers is analyzed to detect at least one structure susceptible to damage from mechanical stress. A bias is automatically added to each of the at least one structure to reduce mechanical stress of the at least one structure as fabricated. Augmented layout data is then provided for the integrated circuit.
摘要翻译：用于补偿机械应力作用的集成电路设计的方法和装置。本发明的一个方面涉及集成电路的设计。获得描述集成电路层的布局数据。分析至少一层以检测易受机械应力破坏的至少一种结构。偏置被自动地添加到至少一个结构中的每个结构中，以减少所制造的至少一个结构的机械应力。然后为集成电路提供增强的布局数据。

3. 发明授权

US07626874B1 Method and apparatus for testing a memory device with a redundant self repair feature 有权
标题翻译：用于测试具有冗余自修复功能的存储设备的方法和装置
公开(公告)号：US07626874B1
公开(公告)日：2009-12-01
申请号：US11709985
申请日：2007-02-23
申请人： Yuezhen Fan , Zhi-Min Ling , Arnold A. Cruz
发明人： Yuezhen Fan , Zhi-Min Ling , Arnold A. Cruz
IPC分类号： G11C7/00
CPC分类号： G11C29/44 , G11C11/41 , G11C29/4401 , G11C29/70 , G11C2029/1208
摘要： A test methodology for testing a memory device with a RSR feature is disclosed. For example, a method for testing a memory device having at least one memory cell group, at least one redundant memory cell group, and a defect detect register is disclosed. In one embodiment, the method applies at least one memory test to the at least one memory cell group; and applies a defect detect register test to the defect detect register.
摘要翻译：公开了一种用于测试具有RSR特征的存储器件的测试方法。例如，公开了一种用于测试具有至少一个存储单元组，至少一个冗余存储单元组和缺陷检测寄存器的存储器件的方法。在一个实施例中，该方法将至少一个存储器测试应用于至少一个存储器单元组; 并对缺陷检测寄存器应用缺陷检测寄存器测试。

4. 发明授权

US07145344B2 Method and circuits for localizing defective interconnect resources in programmable logic devices 有权
标题翻译：用于在可编程逻辑器件中定位不良互连资源的方法和电路
公开(公告)号：US07145344B2
公开(公告)日：2006-12-05
申请号：US10703326
申请日：2003-11-07
申请人： David Mark , Yuezhen Fan , Zhi-Min Ling , Xiao-Yu Li
发明人： David Mark , Yuezhen Fan , Zhi-Min Ling , Xiao-Yu Li
IPC分类号： G01R31/08 , G01R31/04
CPC分类号： H03K19/17764 , G01R31/2853 , G01R31/318516 , G01R31/318519
摘要： Described are methods and circuits for identifying defective device layers and localizing defects. Production PLD tests extract statistically significant data relating failed interconnect resources to the associated conductive metal layer. Failure data thus collected is then analyzed periodically to identify layer-specific problems. Test circuits in accordance with some embodiments employ interconnect resources heavily weighted in favor of specific conductive layers to provide improved layer-specific failure data. Some such test circuits are designed to identify open defects, while others are designed to identify short defects.
摘要翻译：描述了用于识别缺陷设备层和定位缺陷的方法和电路。生产PLD测试提取与相关导电金属层有关的故障互连资源的统计学显着数据。然后定期分析如此收集的故障数据以识别层特定问题。根据一些实施例的测试电路采用对有利于特定导电层重度加权的互连资源，以提供改进的层特定故障数据。一些这样的测试电路被设计为识别开放缺陷，而其他测试电路被设计为识别短缺陷。

5. 发明授权

US07227364B1 Test circuit for and method of identifying a defect in an integrated circuit 有权
标题翻译：用于识别集成电路中的缺陷的测试电路和方法
公开(公告)号：US07227364B1
公开(公告)日：2007-06-05
申请号：US11016473
申请日：2004-12-16
申请人： Yuezhen Fan , David Mark , Eric J Thorne , Zhi-Min Ling
发明人： Yuezhen Fan , David Mark , Eric J Thorne , Zhi-Min Ling
IPC分类号： G01R31/28 , G01R31/26
CPC分类号： G01R31/318516 , G01R31/31717 , G01R31/31855
摘要： The embodiments of the present invention enable a new metal diagnosis pattern based on a production test pattern to quickly identify open and short circuits of metal lines which cannot be probed, such as the long lines of a programmable logic device, and to further isolates the fault location for physical failure analysis. According to one aspect of the invention, a circuit locally drives a plurality of metal long line segments to determine whether a defect in a line is a short circuit, or further to identify the location of an open circuit.
摘要翻译：本发明的实施例使得能够基于生产测试图案的新的金属诊断模式快速识别不能探测的金属线的开路和短路，例如可编程逻辑器件的长线，并进一步隔离故障物理故障分析的位置。根据本发明的一个方面，电路局部地驱动多个金属长线段以确定线路中的缺陷是短路还是进一步识别开路的位置。

6. 发明授权

US06950771B1 Correlation of electrical test data with physical defect data 有权
标题翻译：电气测试数据与物理缺陷数据的相关性
公开(公告)号：US06950771B1
公开(公告)日：2005-09-27
申请号：US10732493
申请日：2003-12-09
申请人： Yuezhen Fan , Jason Xu , Stephen Wing-Ho Tang , Zhi-Min Ling
发明人： Yuezhen Fan , Jason Xu , Stephen Wing-Ho Tang , Zhi-Min Ling
IPC分类号： G01R31/00 , G01R31/28 , G01R31/3185 , G11C29/44
CPC分类号： G11C29/44 , G01R31/2894 , G01R31/318566 , G11C2029/1806
摘要： Method and apparatus are disclosed for analyzing defect data produced in testing a semiconductor chip from a logic design. In various embodiments, input for processing is a first inspection data set that identifies a first set of physical locations that are associated with defects detected during fabrication of the chip. Also input is a second test data set that includes one or more identifiers associated with failing circuitry in the chip. A second set of physical locations is determined from the one or more identifiers of failing circuitry, hierarchical relationships between blocks of the design, and placement information associated with the blocks. Each of the one or more identifiers is associated with at least one of the blocks. Correspondences are identified between physical locations in the first inspection data set and the second set of physical locations.
摘要翻译：公开了用于分析从逻辑设计测试半导体芯片产生的缺陷数据的方法和装置。在各种实施例中，用于处理的输入是第一检查数据集，其识别与芯片制造期间检测到的缺陷相关联的第一组物理位置。还输入第二测试数据集，其包括与芯片中的故障电路相关联的一个或多个标识符。第二组物理位置由故障电路的一个或多个标识符，设计的块之间的分层关系以及与该块相关联的放置信息确定。一个或多个标识符中的每一个与至少一个块相关联。在第一检查数据集中的物理位置与第二组物理位置之间识别对应关系。

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