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1. 发明申请

US20140374823A1 ENHANCING SCHOTTKY BREAKDOWN VOLTAGE (BV) WITHOUT AFFECTING AN INTEGRATED MOSFET-SCHOTTKY DEVICE LAYOUT 有权
标题翻译：在不影响集成MOSFET肖特基器件布局的情况下增强肖特基势垒（BV）
公开(公告)号：US20140374823A1
公开(公告)日：2014-12-25
申请号：US13925776
申请日：2013-06-24
申请人： Anup Bhalla , Xiaobin Wang , Moses Ho
发明人： Anup Bhalla , Xiaobin Wang , Moses Ho
IPC分类号： H01L29/78
CPC分类号： H01L29/7803 , H01L27/0727 , H01L29/0619 , H01L29/0696 , H01L29/41766 , H01L29/66734 , H01L29/7806 , H01L29/7813 , H01L29/872
摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.
摘要翻译：本发明公开了一种包括具有多个功率晶体管单元的有源单元区域的半导体功率器件。每个所述功率晶体管单元具有平面肖特基二极管，其包括覆盖两个相邻功率晶体管单元之间的分离体区域之间的间隙上方的区域的肖特基结阻挡金属。分离体区域还提供调节每个所述功率晶体管单元中的所述肖特基二极管的漏电流的功能。每个平面肖特基二极管还包括设置在两个相邻功率晶体管单元的分离的体区之间的间隙中的香农注入区，用于进一步调整所述肖特基二极管的漏电流。每个功率晶体管单元进一步包括分离体区域中的重体掺杂区域，其邻近形成结屏障肖特基（JBS）口袋区域的围绕所述肖特基二极管的源极区域。

2. 发明授权

US08802530B2 MOSFET with improved performance through induced net charge region in thick bottom insulator 有权
标题翻译： MOSFET通过在厚底部绝缘体中的感应净电荷区域具有改进的性能
公开(公告)号：US08802530B2
公开(公告)日：2014-08-12
申请号：US13490138
申请日：2012-06-06
申请人： Xiaobin Wang , Anup Bhalla , Daniel Ng
发明人： Xiaobin Wang , Anup Bhalla , Daniel Ng
IPC分类号： H01L21/336 , H01L29/78 , H01L21/42
CPC分类号： H01L29/7813 , H01L21/42 , H01L29/408 , H01L29/41766 , H01L29/42368 , H01L29/66734
摘要： A semiconductor power device includes a thick bottom insulator formed in a lower portion of a trench in a semiconductor epitaxial region. An electrically conductive gate electrode is formed in the trench above the bottom insulator. The gate electrode is electrically insulated from the epitaxial region by the bottom insulator and a gate insulator. Charge is deliberately induced in the thick bottom insulator proximate an interface between the bottom insulator and the epitaxial semiconductor region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：半导体功率器件包括形成在半导体外延区域中的沟槽的下部的厚的底部绝缘体。在底部绝缘体上方的沟槽中形成导电栅电极。栅极电极通过底部绝缘体和栅极绝缘体与外延区域电绝缘。在底部绝缘体和外延半导体区域之间的界面附近的厚底层绝缘体中有意地引起电荷。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

3. 发明授权

US08692322B2 Flexible Crss adjustment in a SGT MOSFET to smooth waveforms and to avoid EMI in DC-DC application 有权
标题翻译： SGT MOSFET中的灵活Crss调整可平滑波形，并避免DC-DC应用中的EMI
公开(公告)号：US08692322B2
公开(公告)日：2014-04-08
申请号：US13539330
申请日：2012-08-26
申请人： Ji Pan , Daniel Ng , Anup Bhalla , Xiaobin Wang
发明人： Ji Pan , Daniel Ng , Anup Bhalla , Xiaobin Wang
IPC分类号： H01L27/088
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/66727 , H01L29/66734 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.
摘要翻译：半导体功率器件包括多个功率晶体管单元，每个功率晶体管单元各自具有设置在栅极沟槽中的沟槽栅极，其中沟槽栅极包括设置在栅极沟槽的底部部分中的屏蔽底部电极，该顶部电极与设置在顶部的顶部栅电极电绝缘栅极沟槽的部分通过电极间绝缘层。晶体管单元中的至少一个包括用作与半导体功率器件的源电极电连接的源极连接屏蔽底部电极的屏蔽底部电极，以及具有用作栅极连接的屏蔽底部电极的至少一个晶体管单元，连接屏蔽底电极，电连接到半导体功率器件的栅极金属。

4. 发明授权

US08637368B2 Fabrication of MOS device with varying trench depth 有权
标题翻译：具有不同沟槽深度的MOS器件的制造
公开(公告)号：US08637368B2
公开(公告)日：2014-01-28
申请号：US13559975
申请日：2012-07-27
申请人： Anup Bhalla , Xiaobin Wang
发明人： Anup Bhalla , Xiaobin Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0623 , H01L29/1095 , H01L29/165 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; disposing gate material in the gate trench; forming a body in the epitaxial layer; forming a source in the body; forming an active region contact trench that has a varying trench depth; and disposing a contact electrode within the active region contact trench. Forming the active region contact trench includes performing a first etch to form a first contact trench depth associated with a first region, and performing a second etch to form a second contact trench depth associated with a second region. The first contact trench depth is substantially different from the second contact trench depth.
摘要翻译：制造半导体器件包括：在覆盖半导体衬底的外延层中形成栅极沟槽; 在门沟中设置栅极材料; 在外延层中形成主体; 在身体中形成一个来源; 形成具有变化的沟槽深度的有源区接触沟槽; 以及将接触电极设置在有源区接触沟槽内。形成有源区接触沟槽包括执行第一蚀刻以形成与第一区域相关联的第一接触沟槽深度，以及执行第二蚀刻以形成与第二区域相关联的第二接触沟槽深度。第一接触沟槽深度与第二接触沟槽深度基本不同。

5. 发明授权

US08354316B2 Reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection 有权
公开(公告)号：US08354316B2
公开(公告)日：2013-01-15
申请号：US12925820
申请日：2010-10-29
申请人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
发明人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
IPC分类号： H01L21/8234
CPC分类号： H01L29/7811 , H01L27/0255 , H01L29/0619 , H01L29/0696 , H01L29/404 , H01L29/66734 , H01L29/7808 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.

6. 发明授权

US08253192B2 MOS device with varying trench depth 有权
标题翻译：具有不同沟槽深度的MOS器件
公开(公告)号：US08253192B2
公开(公告)日：2012-08-28
申请号：US13088275
申请日：2011-04-15
申请人： Anup Bhalla , Xiaobin Wang
发明人： Anup Bhalla , Xiaobin Wang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0623 , H01L29/1095 , H01L29/165 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： A semiconductor device includes a drain region comprising an epitaxial layer, a body disposed in the epitaxial layer, a source embedded in the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source, and an active region contact electrode disposed within the active region contact trench. The active region contact trench has a first width associated with a first region that is in proximity to a bottom portion of the body and a second width associated with a second region that is in proximity to a bottom portion of the source. The first width is substantially different from the second width.
摘要翻译：半导体器件包括：漏区，包括外延层，设置在外延层中的主体，嵌入在主体中的源极，延伸到外延层中的栅极沟槽，设置在栅极沟槽中的栅极，有源区域接触沟槽延伸通过源极，以及设置在有源区接触沟槽内的有源区接触电极。有源区接触沟槽具有与位于本体底部附近的第一区域相关联的第一宽度和与源极底部附近的第二区域相关联的第二宽度。第一宽度与第二宽度大致不同。

7. 发明授权

US08247329B2 Nanotube semiconductor devices 有权
标题翻译：纳米管半导体器件
公开(公告)号：US08247329B2
公开(公告)日：2012-08-21
申请号：US13024256
申请日：2011-02-09
申请人： Hamza Yilmaz , Xiaobin Wang , Anup Bhalla , John Chen , Hong Chang
发明人： Hamza Yilmaz , Xiaobin Wang , Anup Bhalla , John Chen , Hong Chang
IPC分类号： H01L21/311
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0692 , H01L29/1095 , H01L29/6609 , H01L29/66143 , H01L29/66348 , H01L29/66666 , H01L29/7397 , H01L29/861 , H01L29/872
摘要： A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.
摘要翻译：形成半导体器件的方法包括：使用形成在半导体本体中的沟槽的侧壁上的薄外延层来形成纳米管区域。薄的外延层具有均匀的掺杂浓度。在另一个实施例中，在半导体主体中的沟槽的侧壁上形成与半导体本体相同的导电类型的第一薄外延层，并且在第一外延层上形成相反导电类型的第二薄外延层。第一和第二外延层具有均匀的掺杂浓度。选择第一和第二外延层和半导体本体的厚度和掺杂浓度以实现电荷平衡。在一个实施例中，半导体本体是轻掺杂的P型衬底。可以使用相同的N-Epi / P-Epi纳米管结构来形成垂直沟槽MOSFET，IGBT，肖特基二极管和P-N结二极管。

8. 发明申请

US20110198605A1 Termination Structure with Multiple Embedded Potential Spreading Capacitive Structures for Trench MOSFET and Method 有权
标题翻译：具有多个嵌入式电位扩展结构的端接结构，用于沟槽MOSFET和方法
公开(公告)号：US20110198605A1
公开(公告)日：2011-08-18
申请号：US12704528
申请日：2010-02-12
申请人： Xiaobin Wang , Anup Bhalla , Hamza Yilmaz , Daniel Ng
发明人： Xiaobin Wang , Anup Bhalla , Hamza Yilmaz , Daniel Ng
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L29/407 , H01L21/76205 , H01L29/04 , H01L29/0619 , H01L29/0638 , H01L29/0649 , H01L29/0696 , H01L29/402 , H01L29/41766 , H01L29/42368 , H01L29/66727 , H01L29/66734 , H01L29/7803 , H01L29/7811 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.
摘要翻译：公开了具有多个嵌入式电位扩展电容结构（TSMEC）和方法的端接结构，用于在具有底部漏电极的体半导体层（BSL）的顶部端接邻近的沟槽MOSFET。 BSL具有支持漏极 - 源极电压（DSV）的近端体半导体壁（PBSW），并将TSMEC与沟槽MOSFET分离。 TSMEC具有由PBSW和远端体半导体壁（DBSW）界定的氧化物填充的大深沟槽（OFLDT）。 OFLDT包括位于大深度氧化物沟槽内部以及PBSW和DBSW之间的BSL中的大型深层氧化物沟槽和嵌入式电容结构（EBCS），用于在其间空间扩展DSV。在一个实施例中，EBCS包含OFLDT的交错导电嵌入式多晶半导体区域（EPSR）和氧化物柱（OXC），与PBSW相邻的近端EPSR连接到活动上部源区域，并且与DBSW相邻的远端EPSR被连接到星展集团

9. 发明授权

US07910486B2 Method for forming nanotube semiconductor devices 有权
标题翻译：形成纳米管半导体器件的方法
公开(公告)号：US07910486B2
公开(公告)日：2011-03-22
申请号：US12484166
申请日：2009-06-12
申请人： Hamza Yilmaz , Xiaobin Wang , Anup Bhalla , John Chen , Hong Chang
发明人： Hamza Yilmaz , Xiaobin Wang , Anup Bhalla , John Chen , Hong Chang
IPC分类号： H01L21/311
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0692 , H01L29/1095 , H01L29/6609 , H01L29/66143 , H01L29/66348 , H01L29/66666 , H01L29/7397 , H01L29/861 , H01L29/872
摘要： A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.
摘要翻译：形成半导体器件的方法包括：使用形成在半导体本体中的沟槽的侧壁上的薄外延层来形成纳米管区域。薄的外延层具有均匀的掺杂浓度。在另一个实施例中，在半导体主体中的沟槽的侧壁上形成与半导体本体相同的导电类型的第一薄外延层，并且在第一外延层上形成相反导电类型的第二薄外延层。第一和第二外延层具有均匀的掺杂浓度。选择第一和第二外延层和半导体本体的厚度和掺杂浓度以实现电荷平衡。在一个实施例中，半导体本体是轻掺杂的P型衬底。可以使用相同的N-Epi / P-Epi纳米管结构形成垂直沟槽MOSFET，IGBT，肖特基二极管和P-N结二极管。

10. 发明授权

US07884454B2 Use of discrete conductive layer in semiconductor device to re-route bonding wires for semiconductor device package 有权
公开(公告)号：US07884454B2
公开(公告)日：2011-02-08
申请号：US12209106
申请日：2008-09-11
申请人： Jun Lu , Anup Bhalla , Xiaobin Wang , Allen Chang , Man Sheng Hu , Xiaotian Zhang
发明人： Jun Lu , Anup Bhalla , Xiaobin Wang , Allen Chang , Man Sheng Hu , Xiaotian Zhang
IPC分类号： H01L23/495
CPC分类号： H01L21/823487 , H01L23/4952 , H01L23/49524 , H01L23/49531 , H01L23/49562 , H01L23/49575 , H01L23/58 , H01L24/37 , H01L24/39 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/85 , H01L24/91 , H01L25/071 , H01L25/074 , H01L25/18 , H01L27/088 , H01L2224/05552 , H01L2224/0603 , H01L2224/32145 , H01L2224/32245 , H01L2224/37124 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48247 , H01L2224/48465 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49112 , H01L2224/4917 , H01L2224/49171 , H01L2224/49431 , H01L2224/73265 , H01L2224/83801 , H01L2224/8385 , H01L2224/85 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H02J7/0031 , H01L2224/78 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： A semiconductor package assembly may include a lead frame having a die bonding pad and plurality of leads coupled to the first die bonding pad. A vertical semiconductor device may be bonded to the die bonding pad. The device may have a conductive pad electrically connected to one lead through a first bond wire. An electrically isolated conductive trace may be formed from a layer of conductive material of the first semiconductor device. The conductive trace provides an electrically conductive path between the first bond wire and a second bond wire. The conductive path may either pass underneath a third bond wire thereby avoiding the third bond wire crossing another bond wire, or the conductive path may result in a reduced length for the first and second bond wires that is less than a predetermined maximum length.

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