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1. 发明申请

US20140374823A1 ENHANCING SCHOTTKY BREAKDOWN VOLTAGE (BV) WITHOUT AFFECTING AN INTEGRATED MOSFET-SCHOTTKY DEVICE LAYOUT 有权
标题翻译：在不影响集成MOSFET肖特基器件布局的情况下增强肖特基势垒（BV）
公开(公告)号：US20140374823A1
公开(公告)日：2014-12-25
申请号：US13925776
申请日：2013-06-24
申请人： Anup Bhalla , Xiaobin Wang , Moses Ho
发明人： Anup Bhalla , Xiaobin Wang , Moses Ho
IPC分类号： H01L29/78
CPC分类号： H01L29/7803 , H01L27/0727 , H01L29/0619 , H01L29/0696 , H01L29/41766 , H01L29/66734 , H01L29/7806 , H01L29/7813 , H01L29/872
摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.
摘要翻译：本发明公开了一种包括具有多个功率晶体管单元的有源单元区域的半导体功率器件。每个所述功率晶体管单元具有平面肖特基二极管，其包括覆盖两个相邻功率晶体管单元之间的分离体区域之间的间隙上方的区域的肖特基结阻挡金属。分离体区域还提供调节每个所述功率晶体管单元中的所述肖特基二极管的漏电流的功能。每个平面肖特基二极管还包括设置在两个相邻功率晶体管单元的分离的体区之间的间隙中的香农注入区，用于进一步调整所述肖特基二极管的漏电流。每个功率晶体管单元进一步包括分离体区域中的重体掺杂区域，其邻近形成结屏障肖特基（JBS）口袋区域的围绕所述肖特基二极管的源极区域。

2. 发明授权

US08105895B2 Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout 有权
标题翻译：增强肖特基击穿电压（BV），而不影响集成MOSFET肖特基器件布局
公开(公告)号：US08105895B2
公开(公告)日：2012-01-31
申请号：US12932163
申请日：2011-02-17
申请人： Anup Bhalla , Xiaobin Wang , Moses Ho
发明人： Anup Bhalla , Xiaobin Wang , Moses Ho
IPC分类号： H01L21/8234
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/1095 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/872
摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.
摘要翻译：本发明公开了一种包括具有多个功率晶体管单元的有源单元区域的半导体功率器件。每个所述功率晶体管单元具有平面肖特基二极管，其包括覆盖两个相邻功率晶体管单元之间的分离体区域之间的间隙上方的区域的肖特基结阻挡金属。分离体区域还提供调节每个所述功率晶体管单元中的所述肖特基二极管的漏电流的功能。每个平面肖特基二极管还包括设置在两个相邻功率晶体管单元的分离的体区之间的间隙中的香农注入区，用于进一步调整所述肖特基二极管的漏电流。每个功率晶体管单元进一步包括分离体区域中的重体掺杂区域，其邻近形成结屏障肖特基（JBS）口袋区域的围绕所述肖特基二极管的源极区域。

3. 发明授权

US08471332B2 Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout 失效
公开(公告)号：US08471332B2
公开(公告)日：2013-06-25
申请号：US13349288
申请日：2012-01-12
申请人： Anup Bhalla , Xiaobin Wang , Moses Ho
发明人： Anup Bhalla , Xiaobin Wang , Moses Ho
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/1095 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/872
摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.

4. 发明申请

US20080265312A1 Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout 有权
标题翻译：增强肖特基击穿电压（BV），而不影响集成MOSFET肖特基器件布局
公开(公告)号：US20080265312A1
公开(公告)日：2008-10-30
申请号：US12217092
申请日：2008-06-30
申请人： Anup Bhalla , Xiaobin Wang , Moses Ho
发明人： Anup Bhalla , Xiaobin Wang , Moses Ho
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/1095 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/872
摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.
摘要翻译：本发明公开了一种包括具有多个功率晶体管单元的有源单元区域的半导体功率器件。每个所述功率晶体管单元具有平面肖特基二极管，其包括覆盖两个相邻功率晶体管单元之间的分离体区域之间的间隙上方的区域的肖特基结阻挡金属。分离体区域还提供调节每个所述功率晶体管单元中的所述肖特基二极管的漏电流的功能。每个平面肖特基二极管还包括设置在两个相邻功率晶体管单元的分离的体区之间的间隙中的香农注入区，用于进一步调整所述肖特基二极管的漏电流。每个功率晶体管单元进一步包括分离体区域中的重体掺杂区域，其邻近形成结屏障肖特基（JBS）口袋区域的围绕所述肖特基二极管的源极区域。

5. 发明申请

US20110140194A1 Enhancing Schottky breakdown voltage (BV) without affecting an integrated Mosfet-Schottky device layout 有权
标题翻译：增强肖特基击穿电压（BV），而不影响集成的Mosfet-Schottky器件布局
公开(公告)号：US20110140194A1
公开(公告)日：2011-06-16
申请号：US12932163
申请日：2011-02-17
申请人： Anup Bhalla , Xiaobin Wang , Moses Ho
发明人： Anup Bhalla , Xiaobin Wang , Moses Ho
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/1095 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/872
摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.
摘要翻译：本发明公开了一种包括具有多个功率晶体管单元的有源单元区域的半导体功率器件。每个所述功率晶体管单元具有平面肖特基二极管，其包括覆盖两个相邻功率晶体管单元之间的分离体区域之间的间隙上方的区域的肖特基结阻挡金属。分离体区域还提供调节每个所述功率晶体管单元中的所述肖特基二极管的漏电流的功能。每个平面肖特基二极管还包括设置在两个相邻功率晶体管单元的分离的体区之间的间隙中的香农注入区，用于进一步调整所述肖特基二极管的漏电流。每个功率晶体管单元进一步包括分离体区域中的重体掺杂区域，其邻近形成结屏障肖特基（JBS）口袋区域的围绕所述肖特基二极管的源极区域。

6. 发明授权

US07952139B2 Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout 有权
标题翻译：增强肖特基击穿电压（BV），而不影响集成MOSFET肖特基器件布局
公开(公告)号：US07952139B2
公开(公告)日：2011-05-31
申请号：US12217092
申请日：2008-06-30
申请人： Anup Bhalla , Xiaobin Wang , Moses Ho
发明人： Anup Bhalla , Xiaobin Wang , Moses Ho
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/1095 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/872
摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.
摘要翻译：本发明公开了一种包括具有多个功率晶体管单元的有源单元区域的半导体功率器件。每个所述功率晶体管单元具有平面肖特基二极管，其包括覆盖两个相邻功率晶体管单元之间的分离体区域之间的间隙上方的区域的肖特基结阻挡金属。分离体区域还提供调节每个所述功率晶体管单元中的所述肖特基二极管的漏电流的功能。每个平面肖特基二极管还包括设置在两个相邻功率晶体管单元的分离的体区之间的间隙中的香农注入区，用于进一步调整所述肖特基二极管的漏电流。每个功率晶体管单元进一步包括分离体区域中的重体掺杂区域，其邻近形成结屏障肖特基（JBS）口袋区域的围绕所述肖特基二极管的源极区域。

7. 发明申请

US20130009238A1 ENHANCING SCHOTTKY BREAKDOWN VOLTAGE (BV) WITHOUT AFFECTING AN INTEGRATED MOSFET-SCHOTTKY DEVICE LAYOUT 失效
标题翻译：在不影响集成MOSFET肖特基器件布局的情况下增强肖特基势垒（BV）
公开(公告)号：US20130009238A1
公开(公告)日：2013-01-10
申请号：US13349288
申请日：2012-01-12
申请人： Anup Bhalla , Xiaobin Wang , Moses Ho
发明人： Anup Bhalla , Xiaobin Wang , Moses Ho
IPC分类号： H01L27/06 , H01L21/329
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/1095 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/872
摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.
摘要翻译：本发明公开了一种包括具有多个功率晶体管单元的有源单元区域的半导体功率器件。每个所述功率晶体管单元具有平面肖特基二极管，其包括覆盖两个相邻功率晶体管单元之间的分离体区域之间的间隙上方的区域的肖特基结阻挡金属。分离体区域还提供调节每个所述功率晶体管单元中的所述肖特基二极管的漏电流的功能。每个平面肖特基二极管还包括设置在两个相邻功率晶体管单元的分离的体区之间的间隙中的香农注入区，用于进一步调整所述肖特基二极管的漏电流。每个功率晶体管单元进一步包括分离体区域中的重体掺杂区域，其邻近形成结屏障肖特基（JBS）口袋区域的围绕所述肖特基二极管的源极区域。

8. 发明授权

US08802530B2 MOSFET with improved performance through induced net charge region in thick bottom insulator 有权
标题翻译： MOSFET通过在厚底部绝缘体中的感应净电荷区域具有改进的性能
公开(公告)号：US08802530B2
公开(公告)日：2014-08-12
申请号：US13490138
申请日：2012-06-06
申请人： Xiaobin Wang , Anup Bhalla , Daniel Ng
发明人： Xiaobin Wang , Anup Bhalla , Daniel Ng
IPC分类号： H01L21/336 , H01L29/78 , H01L21/42
CPC分类号： H01L29/7813 , H01L21/42 , H01L29/408 , H01L29/41766 , H01L29/42368 , H01L29/66734
摘要： A semiconductor power device includes a thick bottom insulator formed in a lower portion of a trench in a semiconductor epitaxial region. An electrically conductive gate electrode is formed in the trench above the bottom insulator. The gate electrode is electrically insulated from the epitaxial region by the bottom insulator and a gate insulator. Charge is deliberately induced in the thick bottom insulator proximate an interface between the bottom insulator and the epitaxial semiconductor region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：半导体功率器件包括形成在半导体外延区域中的沟槽的下部的厚的底部绝缘体。在底部绝缘体上方的沟槽中形成导电栅电极。栅极电极通过底部绝缘体和栅极绝缘体与外延区域电绝缘。在底部绝缘体和外延半导体区域之间的界面附近的厚底层绝缘体中有意地引起电荷。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

9. 发明授权

US08692322B2 Flexible Crss adjustment in a SGT MOSFET to smooth waveforms and to avoid EMI in DC-DC application 有权
标题翻译： SGT MOSFET中的灵活Crss调整可平滑波形，并避免DC-DC应用中的EMI
公开(公告)号：US08692322B2
公开(公告)日：2014-04-08
申请号：US13539330
申请日：2012-08-26
申请人： Ji Pan , Daniel Ng , Anup Bhalla , Xiaobin Wang
发明人： Ji Pan , Daniel Ng , Anup Bhalla , Xiaobin Wang
IPC分类号： H01L27/088
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/66727 , H01L29/66734 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.
摘要翻译：半导体功率器件包括多个功率晶体管单元，每个功率晶体管单元各自具有设置在栅极沟槽中的沟槽栅极，其中沟槽栅极包括设置在栅极沟槽的底部部分中的屏蔽底部电极，该顶部电极与设置在顶部的顶部栅电极电绝缘栅极沟槽的部分通过电极间绝缘层。晶体管单元中的至少一个包括用作与半导体功率器件的源电极电连接的源极连接屏蔽底部电极的屏蔽底部电极，以及具有用作栅极连接的屏蔽底部电极的至少一个晶体管单元，连接屏蔽底电极，电连接到半导体功率器件的栅极金属。

10. 发明授权

US08637368B2 Fabrication of MOS device with varying trench depth 有权
标题翻译：具有不同沟槽深度的MOS器件的制造
公开(公告)号：US08637368B2
公开(公告)日：2014-01-28
申请号：US13559975
申请日：2012-07-27
申请人： Anup Bhalla , Xiaobin Wang
发明人： Anup Bhalla , Xiaobin Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0623 , H01L29/1095 , H01L29/165 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; disposing gate material in the gate trench; forming a body in the epitaxial layer; forming a source in the body; forming an active region contact trench that has a varying trench depth; and disposing a contact electrode within the active region contact trench. Forming the active region contact trench includes performing a first etch to form a first contact trench depth associated with a first region, and performing a second etch to form a second contact trench depth associated with a second region. The first contact trench depth is substantially different from the second contact trench depth.
摘要翻译：制造半导体器件包括：在覆盖半导体衬底的外延层中形成栅极沟槽; 在门沟中设置栅极材料; 在外延层中形成主体; 在身体中形成一个来源; 形成具有变化的沟槽深度的有源区接触沟槽; 以及将接触电极设置在有源区接触沟槽内。形成有源区接触沟槽包括执行第一蚀刻以形成与第一区域相关联的第一接触沟槽深度，以及执行第二蚀刻以形成与第二区域相关联的第二接触沟槽深度。第一接触沟槽深度与第二接触沟槽深度基本不同。

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