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1. 发明授权

US08802530B2 MOSFET with improved performance through induced net charge region in thick bottom insulator 有权
标题翻译： MOSFET通过在厚底部绝缘体中的感应净电荷区域具有改进的性能
公开(公告)号：US08802530B2
公开(公告)日：2014-08-12
申请号：US13490138
申请日：2012-06-06
申请人： Xiaobin Wang , Anup Bhalla , Daniel Ng
发明人： Xiaobin Wang , Anup Bhalla , Daniel Ng
IPC分类号： H01L21/336 , H01L29/78 , H01L21/42
CPC分类号： H01L29/7813 , H01L21/42 , H01L29/408 , H01L29/41766 , H01L29/42368 , H01L29/66734
摘要： A semiconductor power device includes a thick bottom insulator formed in a lower portion of a trench in a semiconductor epitaxial region. An electrically conductive gate electrode is formed in the trench above the bottom insulator. The gate electrode is electrically insulated from the epitaxial region by the bottom insulator and a gate insulator. Charge is deliberately induced in the thick bottom insulator proximate an interface between the bottom insulator and the epitaxial semiconductor region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：半导体功率器件包括形成在半导体外延区域中的沟槽的下部的厚的底部绝缘体。在底部绝缘体上方的沟槽中形成导电栅电极。栅极电极通过底部绝缘体和栅极绝缘体与外延区域电绝缘。在底部绝缘体和外延半导体区域之间的界面附近的厚底层绝缘体中有意地引起电荷。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

2. 发明授权

US08692322B2 Flexible Crss adjustment in a SGT MOSFET to smooth waveforms and to avoid EMI in DC-DC application 有权
标题翻译： SGT MOSFET中的灵活Crss调整可平滑波形，并避免DC-DC应用中的EMI
公开(公告)号：US08692322B2
公开(公告)日：2014-04-08
申请号：US13539330
申请日：2012-08-26
申请人： Ji Pan , Daniel Ng , Anup Bhalla , Xiaobin Wang
发明人： Ji Pan , Daniel Ng , Anup Bhalla , Xiaobin Wang
IPC分类号： H01L27/088
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/66727 , H01L29/66734 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.
摘要翻译：半导体功率器件包括多个功率晶体管单元，每个功率晶体管单元各自具有设置在栅极沟槽中的沟槽栅极，其中沟槽栅极包括设置在栅极沟槽的底部部分中的屏蔽底部电极，该顶部电极与设置在顶部的顶部栅电极电绝缘栅极沟槽的部分通过电极间绝缘层。晶体管单元中的至少一个包括用作与半导体功率器件的源电极电连接的源极连接屏蔽底部电极的屏蔽底部电极，以及具有用作栅极连接的屏蔽底部电极的至少一个晶体管单元，连接屏蔽底电极，电连接到半导体功率器件的栅极金属。

3. 发明授权

US08354316B2 Reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection 有权
公开(公告)号：US08354316B2
公开(公告)日：2013-01-15
申请号：US12925820
申请日：2010-10-29
申请人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
发明人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
IPC分类号： H01L21/8234
CPC分类号： H01L29/7811 , H01L27/0255 , H01L29/0619 , H01L29/0696 , H01L29/404 , H01L29/66734 , H01L29/7808 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.

4. 发明申请

US20110198605A1 Termination Structure with Multiple Embedded Potential Spreading Capacitive Structures for Trench MOSFET and Method 有权
标题翻译：具有多个嵌入式电位扩展结构的端接结构，用于沟槽MOSFET和方法
公开(公告)号：US20110198605A1
公开(公告)日：2011-08-18
申请号：US12704528
申请日：2010-02-12
申请人： Xiaobin Wang , Anup Bhalla , Hamza Yilmaz , Daniel Ng
发明人： Xiaobin Wang , Anup Bhalla , Hamza Yilmaz , Daniel Ng
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L29/407 , H01L21/76205 , H01L29/04 , H01L29/0619 , H01L29/0638 , H01L29/0649 , H01L29/0696 , H01L29/402 , H01L29/41766 , H01L29/42368 , H01L29/66727 , H01L29/66734 , H01L29/7803 , H01L29/7811 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.
摘要翻译：公开了具有多个嵌入式电位扩展电容结构（TSMEC）和方法的端接结构，用于在具有底部漏电极的体半导体层（BSL）的顶部端接邻近的沟槽MOSFET。 BSL具有支持漏极 - 源极电压（DSV）的近端体半导体壁（PBSW），并将TSMEC与沟槽MOSFET分离。 TSMEC具有由PBSW和远端体半导体壁（DBSW）界定的氧化物填充的大深沟槽（OFLDT）。 OFLDT包括位于大深度氧化物沟槽内部以及PBSW和DBSW之间的BSL中的大型深层氧化物沟槽和嵌入式电容结构（EBCS），用于在其间空间扩展DSV。在一个实施例中，EBCS包含OFLDT的交错导电嵌入式多晶半导体区域（EPSR）和氧化物柱（OXC），与PBSW相邻的近端EPSR连接到活动上部源区域，并且与DBSW相邻的远端EPSR被连接到星展集团

5. 发明申请

US20160315053A1 FLEXIBLE CRSS ADJUSTMENT IN A SGT MOSFET TO SMOOTH WAVEFORMS AND TO AVOID EMI IN DC-DC APPLICATION 有权
公开(公告)号：US20160315053A1
公开(公告)日：2016-10-27
申请号：US14242851
申请日：2014-04-01
申请人： Ji Pan , Daniel Ng , Anup Bhalla , Xiaobin Wang
发明人： Ji Pan , Daniel Ng , Anup Bhalla , Xiaobin Wang
IPC分类号： H01L23/552 , H02M1/44 , H01L29/66 , H02M3/158 , H01L29/40 , H01L29/78
CPC分类号： H01L23/552 , H01L29/0638 , H01L29/401 , H01L29/407 , H01L29/41766 , H01L29/66704 , H01L29/66727 , H01L29/66734 , H01L29/7811 , H01L29/7813 , H01L29/7823 , H01L29/7825 , H02M1/44 , H02M3/158
摘要： A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.

6. 发明申请

US20140167212A1 Termination Structure with Multiple Embedded Potential Spreading Capacitive Structures for Trench MOSFET and Method 有权
标题翻译：具有多个嵌入式电位扩展结构的端接结构，用于沟槽MOSFET和方法
公开(公告)号：US20140167212A1
公开(公告)日：2014-06-19
申请号：US13712980
申请日：2012-12-13
申请人： Xiaobin Wang , Anup Bhalla , Hamza Yilmaz , Daniel Ng
发明人： Xiaobin Wang , Anup Bhalla , Hamza Yilmaz , Daniel Ng
IPC分类号： H01L21/762 , H01L29/06
CPC分类号： H01L29/407 , H01L21/76205 , H01L29/04 , H01L29/0619 , H01L29/0638 , H01L29/0649 , H01L29/0696 , H01L29/402 , H01L29/41766 , H01L29/42368 , H01L29/66727 , H01L29/66734 , H01L29/7803 , H01L29/7811 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.
摘要翻译：公开了具有多个嵌入式电位扩展电容结构（TSMEC）和方法的端接结构，用于在具有底部漏电极的体半导体层（BSL）的顶部端接邻近的沟槽MOSFET。 BSL具有支持漏极 - 源极电压（DSV）的近端体半导体壁（PBSW），并将TSMEC与沟槽MOSFET分离。 TSMEC具有由PBSW和远端体半导体壁（DBSW）界定的氧化物填充的大深沟槽（OFLDT）。 OFLDT包括位于大深度氧化物沟槽内部以及PBSW和DBSW之间的BSL中的大型深层氧化物沟槽和嵌入式电容结构（EBCS），用于在其间空间扩展DSV。在一个实施例中，EBCS包含OFLDT的交错导电嵌入式多晶半导体区域（EPSR）和氧化物柱（OXC），与PBSW相邻的近端EPSR连接到活动上部源区域，并且与DBSW相邻的远端EPSR被连接到星展集团

7. 发明授权

US07825431B2 Reduced mask configuration for power MOSFETs with electrostatic discharge (ESD) circuit protection 有权
标题翻译：降低了具有静电放电（ESD）电路保护功能MOSFET的掩模配置
公开(公告)号：US07825431B2
公开(公告)日：2010-11-02
申请号：US12006398
申请日：2007-12-31
申请人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
发明人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
IPC分类号： H01L29/72 , H01L23/62
CPC分类号： H01L29/7811 , H01L27/0255 , H01L29/0619 , H01L29/0696 , H01L29/404 , H01L29/66734 , H01L29/7808 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.
摘要翻译：支撑在半导体衬底上的半导体功率器件包括设置在半导体衬底顶部的图案化ESD多晶硅层的第一部分上的静电放电（ESD）保护电路。该半导体功率器件还包括构图的ESD多晶硅层的第二部分，其构成体部注入离子阻挡层，用于阻止注入体离子进入体内注入离子阻挡层下方的半导体衬底。在示例性实施例中，半导体衬底顶部上的静电放电（ESD）多晶硅层进一步覆盖半导体器件边缘上的划线，由此不再需要钝化层制造用于减少图案所需掩模的半导体器件钝化层。

8. 发明申请

US20120126317A1 ACCUFET WITH INTEGRATED CLAMPING CIRCUIT 审中-公开
标题翻译：具有集成钳位电路的ACCUFET
公开(公告)号：US20120126317A1
公开(公告)日：2012-05-24
申请号：US12949218
申请日：2010-11-18
申请人： Daniel Ng , Anup Bhalla , Xiaobin Wang
发明人： Daniel Ng , Anup Bhalla , Xiaobin Wang
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L27/0727 , H01L27/0629 , H01L29/872
摘要： The present invention features a field effect transistor that includes a semiconductor substrate having gate, source and drain regions; and a p-n junction formed on the semiconductor substrate and in electrical communication with the gate, drain and source regions to establish a desired breakdown voltage. In one embodiment, gate region further includes a plurality of spaced-apart trench gates with the p-n junction being defined by an interface between an epitaxial layer in which the trench gates are formed and the interface with a metallization layer. The breakdown voltage provided is defined, in part by the number of p-n junctions formed. In another embodiment, the p-n junctions are formed by generating a plurality of spaced-apart p-type regions in areas of the epitaxial layer located adjacent to the trench gates.
摘要翻译：本发明的特征在于一种场效应晶体管，其包括具有栅极，源极和漏极区域的半导体衬底; 以及形成在半导体衬底上并与栅极，漏极和源极区域电连通以建立期望的击穿电压的p-n结。在一个实施例中，栅极区域还包括多个间隔开的沟槽栅极，其中p-n结由其中形成沟槽栅极的外延层与与金属化层的界面之间的界面限定。提供的击穿电压部分地由形成的p-n结的数量定义。在另一个实施例中，通过在邻近沟槽栅极定位的外延层的区域中产生多个间隔开的p型区域来形成p-n结。

9. 发明申请

US20110076815A1 Reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection 有权
标题翻译：降低了具有静电放电（ESD）电路保护功率的MOSFET的掩模配置
公开(公告)号：US20110076815A1
公开(公告)日：2011-03-31
申请号：US12925820
申请日：2010-10-29
申请人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
发明人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
IPC分类号： H01L21/8234
CPC分类号： H01L29/7811 , H01L27/0255 , H01L29/0619 , H01L29/0696 , H01L29/404 , H01L29/66734 , H01L29/7808 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.
摘要翻译：支撑在半导体衬底上的半导体功率器件包括设置在半导体衬底顶部的图案化ESD多晶硅层的第一部分上的静电放电（ESD）保护电路。该半导体功率器件还包括构图的ESD多晶硅层的第二部分，其构成体部注入离子阻挡层，用于阻止注入体离子进入体内注入离子阻挡层下方的半导体衬底。在示例性实施例中，半导体衬底顶部上的静电放电（ESD）多晶硅层进一步覆盖半导体器件边缘上的划线，由此不再需要钝化层制造用于减少图案所需掩模的半导体器件钝化层。

10. 发明申请

US20130001683A1 FLEXIBLE CRSS ADJUSTMENT IN A SGT MOSFET TO SMOOTH WAVEFORMS AND TO AVOID EMI IN DC-DC APPLICATION 有权
标题翻译： SGT MOSFET中的灵活CRSS调整到平滑波形并避免DC-DC应用中的EMI
公开(公告)号：US20130001683A1
公开(公告)日：2013-01-03
申请号：US13539330
申请日：2012-08-26
申请人： Ji Pan , Daniel Ng , Anup Bhalla , Xiaobin Wang
发明人： Ji Pan , Daniel Ng , Anup Bhalla , Xiaobin Wang
IPC分类号： H01L27/088 , H01L21/28
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/66727 , H01L29/66734 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.
摘要翻译：半导体功率器件包括多个功率晶体管单元，每个功率晶体管单元各自具有设置在栅极沟槽中的沟槽栅极，其中沟槽栅极包括设置在栅极沟槽的底部部分中的屏蔽底部电极，该顶部电极与设置在顶部的顶部栅电极电绝缘栅极沟槽的部分通过电极间绝缘层。晶体管单元中的至少一个包括用作与半导体功率器件的源电极电连接的源极连接屏蔽底部电极的屏蔽底部电极，以及具有用作栅极连接的屏蔽底部电极的至少一个晶体管单元，连接屏蔽底电极，电连接到半导体功率器件的栅极金属。

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