专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08753964B2 FinFET structure having fully silicided fin 有权
标题翻译： FinFET结构具有完全硅化的翅片
公开(公告)号：US08753964B2
公开(公告)日：2014-06-17
申请号：US13015123
申请日：2011-01-27
申请人： Andres Bryant , Huiming Bu , Dechao Guo , Wilfried E. Haensch , Chun-Chen Yeh
发明人： Andres Bryant , Huiming Bu , Dechao Guo , Wilfried E. Haensch , Chun-Chen Yeh
IPC分类号： H01L29/786
CPC分类号： H01L29/41791 , H01L21/28518 , H01L21/76895 , H01L29/66795 , H01L29/7843 , H01L29/785
摘要： A semiconductor device which includes fins of a semiconductor material formed on a semiconductor substrate and then a gate electrode formed over and in contact with the fins. An insulator layer is deposited over the gate electrode and the fins. A trench opening is then etched in the insulator layer. The trench opening exposes the fins and extends between the fins. The fins are then silicided through the trench opening. Then, the trench opening is filled with a metal in contact with the silicided fins to form a local interconnect connecting the fins.
摘要翻译：一种半导体器件，其包括在半导体衬底上形成的半导体材料的散热片，然后形成在鳍片上并与翅片接触的栅电极。绝缘体层沉积在栅电极和鳍片上。然后在绝缘体层中蚀刻沟槽开口。沟槽开口暴露翅片并在翅片之间延伸。然后将鳍片通过沟槽开口硅化。然后，沟槽开口填充有与硅化物翅片接触的金属，以形成连接翅片的局部互连。

2. 发明申请

US20120193712A1 FinFET STRUCTURE HAVING FULLY SILICIDED FIN 有权
标题翻译：具有完全硅化物的FinFET结构
公开(公告)号：US20120193712A1
公开(公告)日：2012-08-02
申请号：US13015123
申请日：2011-01-27
申请人： Andres Bryant , Huiming Bu , Dechao Guo , Wilfried E. Haensch , Chun-Chen Yeh
发明人： Andres Bryant , Huiming Bu , Dechao Guo , Wilfried E. Haensch , Chun-Chen Yeh
IPC分类号： H01L29/786 , H01L21/28
CPC分类号： H01L29/41791 , H01L21/28518 , H01L21/76895 , H01L29/66795 , H01L29/7843 , H01L29/785
摘要： A semiconductor device which includes fins of a semiconductor material formed on a semiconductor substrate and then a gate electrode formed over and in contact with the fins. An insulator layer is deposited over the gate electrode and the fins. A trench opening is then etched in the insulator layer. The trench opening exposes the fins and extends between the fins. The fins are then silicided through the trench opening. Then, the trench opening is filled with a metal in contact with the silicided fins to form a local interconnect connecting the fins.
摘要翻译：一种半导体器件，其包括在半导体衬底上形成的半导体材料的散热片，然后形成在鳍片上并与翅片接触的栅电极。绝缘体层沉积在栅电极和鳍片上。然后在绝缘体层中蚀刻沟槽开口。沟槽开口暴露翅片并在翅片之间延伸。然后将鳍片通过沟槽开口硅化。然后，沟槽开口填充有与硅化物翅片接触的金属，以形成连接翅片的局部互连。

3. 发明授权

US08637931B2 finFET with merged fins and vertical silicide 有权
标题翻译： finFET具有合并翅片和垂直硅化物
公开(公告)号：US08637931B2
公开(公告)日：2014-01-28
申请号：US13337874
申请日：2011-12-27
申请人： Veeraraghavan S. Basker , Andres Bryant , Huiming Bu , Wilfried Haensch , Effendi Leobandung , Chung-Hsun Lin , Theodorus E. Standaert , Tenko Yamashita , Chun-chen Yeh
发明人： Veeraraghavan S. Basker , Andres Bryant , Huiming Bu , Wilfried Haensch , Effendi Leobandung , Chung-Hsun Lin , Theodorus E. Standaert , Tenko Yamashita , Chun-chen Yeh
IPC分类号： H01L27/12
CPC分类号： H01L29/41791 , H01L29/66795
摘要： A finFET device is provided. The finFET device includes a BOX layer, fin structures located over the BOX layer, a gate stack located over the fin structures, gate spacers located on vertical sidewalls of the gate stack, an epi layer covering the fin structures, source and drain regions located in the semiconductor layers of the fin structures, and silicide regions abutting the source and drain regions. The fin structures each comprise a semiconductor layer and extend in a first direction, and the gate stack extends in a second direction that is perpendicular. The gate stack comprises a high-K dielectric layer and a metal gate, and the epi layer merges the fin structures together. The silicide regions each include a vertical portion located on the vertical sidewall of the source or drain region.
摘要翻译：提供了finFET器件。 finFET器件包括BOX层，位于BOX层上方的翅片结构，位于鳍结构上方的栅极堆叠，位于栅叠层的垂直侧壁上的栅极隔离物，覆盖翅片结构的外延层，位于翅片结构的半导体层和邻接源极和漏极区域的硅化物区域。翅片结构各自包括半导体层并沿第一方向延伸，并且栅极堆叠沿垂直的第二方向延伸。栅极堆叠包括高K电介质层和金属栅极，并且外延层将鳍结构融合在一起。硅化物区域各自包括位于源极或漏极区域的垂直侧壁上的垂直部分。

4. 发明申请

US20130161744A1 FINFET WITH MERGED FINS AND VERTICAL SILICIDE 有权
标题翻译：具有合并的FINS和垂直硅胶的FINFET
公开(公告)号：US20130161744A1
公开(公告)日：2013-06-27
申请号：US13337874
申请日：2011-12-27
申请人： Veeraraghavan S. BASKER , Andres Bryant , Huiming Bu , Wilfried Haensch , Effendi Leobandung , Chung-Hsun Lin , Theodorus E. Standaert , Tenko Yamashita , Chun-chen Yeh
发明人： Veeraraghavan S. BASKER , Andres Bryant , Huiming Bu , Wilfried Haensch , Effendi Leobandung , Chung-Hsun Lin , Theodorus E. Standaert , Tenko Yamashita , Chun-chen Yeh
IPC分类号： H01L27/12 , H01L29/78 , H01L21/336
CPC分类号： H01L29/41791 , H01L29/66795
摘要： A finFET device is provided. The finFET device includes a BOX layer, fin structures located over the BOX layer, a gate stack located over the fin structures, gate spacers located on vertical sidewalls of the gate stack, an epi layer covering the fin structures, source and drain regions located in the semiconductor layers of the fin structures, and silicide regions abutting the source and drain regions. The fin structures each comprise a semiconductor layer and extend in a first direction, and the gate stack extends in a second direction that is perpendicular. The gate stack comprises a high-K dielectric layer and a metal gate, and the epi layer merges the fin structures together. The silicide regions each include a vertical portion located on the vertical sidewall of the source or drain region.
摘要翻译：提供了finFET器件。 finFET器件包括BOX层，位于BOX层上方的翅片结构，位于鳍结构上方的栅极堆叠，位于栅叠层的垂直侧壁上的栅极隔离物，覆盖翅片结构的外延层，位于翅片结构的半导体层和邻接源极和漏极区域的硅化物区域。翅片结构各自包括半导体层并沿第一方向延伸，并且栅极堆叠沿垂直的第二方向延伸。栅极堆叠包括高K电介质层和金属栅极，并且外延层将鳍结构融合在一起。硅化物区域各自包括位于源极或漏极区域的垂直侧壁上的垂直部分。

5. 发明授权

US08455313B1 Method for fabricating finFET with merged fins and vertical silicide 有权
标题翻译：使用合并翅片和垂直硅化物制造finFET的方法
公开(公告)号：US08455313B1
公开(公告)日：2013-06-04
申请号：US13617709
申请日：2012-09-14
申请人： Veeraraghavan S. Basker , Andres Bryant , Huiming Bu , Wilfried Haensch , Effendi Leobandung , Chung-Hsun Lin , Theodorus E. Standaert , Tenko Yamashita , Chun-chen Yeh
发明人： Veeraraghavan S. Basker , Andres Bryant , Huiming Bu , Wilfried Haensch , Effendi Leobandung , Chung-Hsun Lin , Theodorus E. Standaert , Tenko Yamashita , Chun-chen Yeh
IPC分类号： H01L21/336
CPC分类号： H01L29/41791 , H01L29/66795
摘要： A method is provided for fabricating a finFET device. Fin structures are formed over a BOX layer. The fin structures include a semiconductor layer and extend in a first direction. A gate stack is formed on the BOX layer over the fin structures and extending in a second direction. The gate stack includes a high-K dielectric layer and a metal gate. Gate spacers are formed on sidewalls of the gate stack, and an epi layer is deposited to merge the fin structures. Ions are implanted to form source and drain regions, and dummy spacers are formed on sidewalls of the gate spacers. The dummy spacers are used as a mask to recess or completely remove an exposed portion of the epi layer. Silicidation forms silicide regions that abut the source and drain regions and each include a vertical portion located on the vertical sidewall of the source or drain region.
摘要翻译：提供了一种用于制造finFET器件的方法。翅片结构形成在BOX层上。翅片结构包括半导体层并沿第一方向延伸。栅极叠层形成在鳍状结构上的BOX层上并沿第二方向延伸。栅极堆叠包括高K电介质层和金属栅极。栅极间隔物形成在栅极堆叠的侧壁上，并且沉积外延层以使翅片结构合并。植入离子以形成源极和漏极区，并且在栅极间隔物的侧壁上形成虚设间隔物。虚拟间隔物用作掩模以凹进或完全去除外延层的暴露部分。硅化形成邻接源极和漏极区域的硅化物区域，并且每个都包括位于源极或漏极区域的垂直侧壁上的垂直部分。

6. 发明授权

US08604546B1 Reducing gate resistance in nonplanar multi-gate transistor 失效
标题翻译：降低非平面多栅极晶体管的栅极电阻
公开(公告)号：US08604546B1
公开(公告)日：2013-12-10
申请号：US13544176
申请日：2012-07-09
申请人： Andres Bryant , Theodorus E. Standaert , Gen Tsutsui , Chun-Chen Yeh
发明人： Andres Bryant , Theodorus E. Standaert , Gen Tsutsui , Chun-Chen Yeh
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7845
摘要： A semiconductor transistor structure has a plurality of fins, a cap on the center portion of the top of each of the fins, a conductive liner lining the cap and the sidewalls of the center portion of the fins, and an insulator between the center portions of the fins. The insulator contacts the conductive liner, and the fins extend further from the surface of the substrate relative to an amount the insulator extends from the surface of the substrate. The structure further includes a conductive layer positioned on the insulator between the center portions of the fins and positioned between the cap of the fins. The conductive layer contacts the conductive liner.
摘要翻译：半导体晶体管结构具有多个散热片，在每个翅片的顶部的中心部分上的盖，衬套盖的导电衬垫和散热片的中心部分的侧壁以及中心部分之间的绝缘体翅片绝缘体接触导电衬垫，并且散热片相对于绝缘体从衬底的表面延伸的量从衬底的表面进一步延伸。所述结构还包括位于所述绝缘体之间的导电层，所述导电层位于所述翅片的中心部分之间并且位于所述翅片的帽之间。导电层接触导电衬垫。

7. 发明授权

US09768304B2 Method of fabricating a FINFET having a gate structure disposed at least partially at a bend region of the semiconductor fin 有权
公开(公告)号：US09768304B2
公开(公告)日：2017-09-19
申请号：US13492108
申请日：2012-06-08
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L21/20 , H01L29/78 , H01L21/8238 , H01L27/12 , H01L29/10 , H01L21/3115 , H01L21/762 , H01L29/66
CPC分类号： H01L29/785 , H01L21/31155 , H01L21/76283 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1203 , H01L29/1037 , H01L29/66621 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/7849
摘要： A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.

8. 发明授权

US08941180B2 Integrated circuit structure incorporating one or more asymmetric field effect transistors as power gates for an electronic circuit with stacked symmetric field effect transistors 有权
标题翻译：集成电路结构，其包括一个或多个不对称场效应晶体管作为具有堆叠对称场效应晶体管的电子电路的功率门
公开(公告)号：US08941180B2
公开(公告)日：2015-01-27
申请号：US13044872
申请日：2011-03-10
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L27/02 , H01L27/12 , H01L21/8234 , H01L29/786 , H01L21/8238
CPC分类号： H01L27/1203 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L29/78624
摘要： Disclosed is an integrated circuit having an asymmetric FET as a power gate for an electronic circuit, which has at least two stacked symmetric field effect transistors. The asymmetric FET has an asymmetric halo configuration (i.e., a single source-side halo or a source-side halo with a higher dopant concentration than a drain-side halo) and an asymmetric source/drain extension configuration (i.e., the source extension can be overlapped to a greater extent by the gate structure than the drain extension and/or the source extension can have a higher dopant concentration than the drain extension). As a result, the asymmetric FET has a low off current. In operation, the asymmetric FET is turned off when the electronic circuit is placed in a standby state and, due to the low off current (Ioff), effectively reduces standby leakage current from the electronic circuit. Additionally, avoiding the use of stacked asymmetric field effect transistors within the electronic circuit itself prevents performance degradation due to reduced linear drain current (Idlin).
摘要翻译：公开了具有不对称FET作为电子电路的功率门的集成电路，其具有至少两个堆叠的对称场效应晶体管。非对称FET具有不对称的卤素配置（即，具有比漏极侧卤素更高的掺杂剂浓度的单个源极卤素或源极卤素）和非对称源极/漏极延伸配置（即，源极延伸可以通过栅极结构比漏极延伸更大程度地重叠和/或源极延伸可以具有比漏极延伸更高的掺杂剂浓度）。结果，不对称FET具有低截止电流。在操作中，当电子电路处于待机状态时，不对称FET被关闭，并且由于低关断电流（Ioff），有效地减少了来自电子电路的待机漏电流。另外，避免使用电子电路内的层叠的非对称场效应晶体管本身可以防止由于线性漏极电流（Idlin）的降低导致的性能劣化。

9. 发明授权

US08900954B2 Blanket short channel roll-up implant with non-angled long channel compensating implant through patterned opening 有权
标题翻译：毯子短通道卷起植入物，具有通过图案化开口的非角度长通道补偿植入物
公开(公告)号：US08900954B2
公开(公告)日：2014-12-02
申请号：US13289051
申请日：2011-11-04
申请人： James W. Adkisson , Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： James W. Adkisson , Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/772 , H01L21/336 , H01L21/28 , H01L29/66 , H01L29/10 , H01L21/265
CPC分类号： H01L29/1041 , H01L21/2652 , H01L21/26586 , H01L21/28026 , H01L29/0847 , H01L29/1045 , H01L29/36 , H01L29/66537 , H01L29/66583 , H01L29/6659 , H01L29/78
摘要： A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers.
摘要翻译：一种形成将衬底植入衬底的结构的方法，在衬底上图案掩模（具有暴露衬底的沟道区的至少一个开口），并在掩模上形成共形电介质层并使开口。保形介电层覆盖衬底的沟道区。该方法还在保形电介质层上形成共形栅极金属层，通过共形栅极金属层和共形绝缘层将补偿注入植入衬底的沟道区，并在共形栅极金属层上形成栅极导体。此外，该方法去除掩模以在衬底上留下栅极堆叠，在栅极堆叠上形成侧壁间隔物，然后在衬底中部分地在侧壁间隔物下方形成源极/漏极区域。

10. 发明授权

US08759916B2 Field effect transistor and a method of forming the transistor 失效
标题翻译：场效应晶体管和形成晶体管的方法
公开(公告)号：US08759916B2
公开(公告)日：2014-06-24
申请号：US13359615
申请日：2012-01-27
申请人： Andres Bryant , Edward J. Nowak
发明人： Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/78
CPC分类号： H01L29/66742 , H01L29/66795 , H01L29/785 , H01L29/78621 , H01L29/78684
摘要： Disclosed are embodiments of a metal oxide semiconductor field effect transistor (MOSFET) structure and a method of forming the structure. The structure incorporates source/drain regions and a channel region between the source/drain regions. The source/drain regions can comprise silicon, which has high diffusivity to the source/drain dopant. The channel region can comprise a silicon alloy selected for optimal charge carrier mobility and band energy and for its low source/drain dopant diffusivity. During processing, the source/drain dopant can diffuse into the edge portions of the channel region. However, due to the low diffusivity of the silicon alloy to the source/drain dopant, the dopant does not diffuse deep into channel region. Thus, the edge portions of the silicon alloy channel region can have essentially the same dopant profile as the source/drain regions, but a different dopant profile than the center portion of the silicon alloy channel region.
摘要翻译：公开了金属氧化物半导体场效应晶体管（MOSFET）结构的实施例和形成该结构的方法。该结构包括源极/漏极区域和源极/漏极区域之间的沟道区域。源极/漏极区域可以包括对源极/漏极掺杂剂具有高扩散性的硅。通道区域可以包括选择用于最佳电荷载流子迁移率和带能量以及其低源极/漏极掺杂剂扩散率的硅合金。在处理期间，源/漏掺杂剂可以扩散到沟道区的边缘部分。然而，由于硅合金对源极/漏极掺杂剂的低扩散性，掺杂剂不会深入沟道区域。因此，硅合金沟道区域的边缘部分可以具有与源极/漏极区域基本相同的掺杂剂分布，但是与硅合金沟道区域的中心部分不同的掺杂剂分布。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式