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1. 发明授权

US08900954B2 Blanket short channel roll-up implant with non-angled long channel compensating implant through patterned opening 有权
标题翻译：毯子短通道卷起植入物，具有通过图案化开口的非角度长通道补偿植入物
公开(公告)号：US08900954B2
公开(公告)日：2014-12-02
申请号：US13289051
申请日：2011-11-04
申请人： James W. Adkisson , Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： James W. Adkisson , Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/772 , H01L21/336 , H01L21/28 , H01L29/66 , H01L29/10 , H01L21/265
CPC分类号： H01L29/1041 , H01L21/2652 , H01L21/26586 , H01L21/28026 , H01L29/0847 , H01L29/1045 , H01L29/36 , H01L29/66537 , H01L29/66583 , H01L29/6659 , H01L29/78
摘要： A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers.
摘要翻译：一种形成将衬底植入衬底的结构的方法，在衬底上图案掩模（具有暴露衬底的沟道区的至少一个开口），并在掩模上形成共形电介质层并使开口。保形介电层覆盖衬底的沟道区。该方法还在保形电介质层上形成共形栅极金属层，通过共形栅极金属层和共形绝缘层将补偿注入植入衬底的沟道区，并在共形栅极金属层上形成栅极导体。此外，该方法去除掩模以在衬底上留下栅极堆叠，在栅极堆叠上形成侧壁间隔物，然后在衬底中部分地在侧壁间隔物下方形成源极/漏极区域。

2. 发明申请

US20130113050A1 BLANKET SHORT CHANNEL ROLL-UP IMPLANT WITH NON-ANGLED LONG CHANNEL COMPENSATING IMPLANT THROUGH PATTERNED OPENING 有权
公开(公告)号：US20130113050A1
公开(公告)日：2013-05-09
申请号：US13289051
申请日：2011-11-04
申请人： James W. Adkisson , Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： James W. Adkisson , Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/1041 , H01L21/2652 , H01L21/26586 , H01L21/28026 , H01L29/0847 , H01L29/1045 , H01L29/36 , H01L29/66537 , H01L29/66583 , H01L29/6659 , H01L29/78
摘要： A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers.

3. 发明申请

US20090261415A1 FULLY-DEPLETED LOW-BODY DOPING FIELD EFFECT TRANSISTOR (FET) WITH REVERSE SHORT CHANNEL EFFECTS (SCE) INDUCED BY SELF-ALIGNED EDGE BACK-GATE(S) 有权
标题翻译：具有反向短路通道效应（SCE）的全自动低体积场效应晶体管（FET）由自对准边缘背栅（S）
公开(公告)号：US20090261415A1
公开(公告)日：2009-10-22
申请号：US12104683
申请日：2008-04-17
申请人： James W. Adkisson , Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
发明人： James W. Adkisson , Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
IPC分类号： H01L49/00 , H01L21/00
CPC分类号： H01L29/78603 , H01L29/66621 , H01L29/78645 , H01L29/78648 , H01L29/78696
摘要： Disclosed are embodiments of a field effect transistor (FET) and, more particularly, a fully-depleted, thin-body (FDTB) FET that allows for scaling with minimal short channel effects, such as drain induced barrier lowering (DIBL) and saturation threshold voltage (Vtsat) roll-off, at shorter channel lengths. The FDTB FET embodiments are configured with either an edge back-gate or split back-gate that can be biased in order to selectively adjust the potential barrier between the source/drain regions and the channel region for minimizing off-state leakage current between the drain region and the source region and/or for varying threshold voltage. These unique back-gate structures avoid the need for halo doping to ensure linear threshold voltage (Vtlin) roll-up at smaller channel lengths and, thus, avoid across-chip threshold voltage variations due to random doping fluctuations. Also disclosed are method embodiments for forming such FETs.
摘要翻译：公开了场效应晶体管（FET）的具体实施例，更具体地说，是允许以最小的短沟道效应（例如漏极感应势垒降低（DIBL）和饱和阈值））进行缩放的完全耗尽的薄体（FDTB）FET 电压（Vtsat）滚降，通道长度较短。 FDTB FET实施例配置有可被偏置的边缘背栅极或分支反向栅极，以便选择性地调节源极/漏极区域和沟道区域之间的势垒，以最小化漏极之间的截止状态漏电流区域和源极区域和/或用于改变阈值电压。这些独特的背栅结构避免了对光晕掺杂的需要，以确保较小通道长度的线性阈值电压（Vtlin）汇总，从而避免由于随机掺杂波动引起的跨芯片阈值电压变化。还公开了用于形成这种FET的方法实施例。

4. 发明申请

US20150041904A1 BLANKET SHORT CHANNEL ROLL-UP IMPLANT WITH NON-ANGLED LONG CHANNEL COMPENSATING IMPLANT THROUGH PATTERNED OPENING 有权
标题翻译：空心短路通道带有非直线长通道补偿的通道拉伸通过图案打开进行植入
公开(公告)号：US20150041904A1
公开(公告)日：2015-02-12
申请号：US14493749
申请日：2014-09-23
申请人： James W. Adkisson , Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： James W. Adkisson , Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/10 , H01L29/36 , H01L29/08 , H01L29/78
CPC分类号： H01L29/1041 , H01L21/2652 , H01L21/26586 , H01L21/28026 , H01L29/0847 , H01L29/1045 , H01L29/36 , H01L29/66537 , H01L29/66583 , H01L29/6659 , H01L29/78
摘要： A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers.
摘要翻译：一种形成将衬底植入衬底的结构的方法，在衬底上图案掩模（具有暴露衬底的沟道区的至少一个开口），并在掩模上形成共形电介质层并使开口。保形介电层覆盖衬底的沟道区。该方法还在保形电介质层上形成共形栅极金属层，通过共形栅极金属层和共形绝缘层将补偿注入植入衬底的沟道区，并在共形栅极金属层上形成栅极导体。此外，该方法去除掩模以在衬底上留下栅极堆叠，在栅极堆叠上形成侧壁间隔物，然后在衬底中部分地在侧壁间隔物下方形成源极/漏极区域。

5. 发明申请

US20130154003A1 ASYMMETRIC ANTI-HALO FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：不对称抗HALO场效应晶体管
公开(公告)号：US20130154003A1
公开(公告)日：2013-06-20
申请号：US13329440
申请日：2011-12-19
申请人： James W. Adkisson , Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： James W. Adkisson , Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26586 , H01L29/1045 , H01L29/66492 , H01L29/66583 , H01L29/6659 , H01L29/66659 , H01L29/7835
摘要： A method of forming an integrated circuit structure implants a first compensating implant into a substrate. The method patterns a mask on the first compensating implant in the substrate. The mask includes an opening exposing a channel location of the substrate. The method implants a second compensating implant into the channel location of the substrate. The second compensating implant is made through the opening in the mask and at an angle that is offset from perpendicular to the top surface of the substrate. The second compensating implant is positioned closer to a first side of the channel location relative to an opposite second side of the channel location and the second compensating implant comprises a material having the same doping polarity as the semiconductor channel implant. Then, the method forms a gate conductor above the channel location of the substrate in the opening of the mask.
摘要翻译：形成集成电路结构的方法将第一补偿植入物植入衬底。该方法在衬底中的第一补偿植入物上形成掩模。掩模包括暴露基板的通道位置的开口。该方法将第二补偿植入物植入衬底的通道位置。第二补偿植入物通过掩模中的开口并以与衬底的顶表面垂直的角度形成。第二补偿植入件相对于沟道位置的相对的第二侧被定位成更靠近通道位置的第一侧，并且第二补偿植入物包括具有与半导体沟道植入物相同的掺杂极性的材料。然后，该方法在掩模的开口中在衬底的通道位置之上形成栅极导体。

6. 发明授权

US07943997B2 Fully-depleted low-body doping field effect transistor (FET) with reverse short channel effects (SCE) induced by self-aligned edge back-gate(s) 有权
标题翻译：具有由自对准边缘后栅极引起的反向短沟道效应（SCE）的全耗尽低体积掺杂场效应晶体管（FET）
公开(公告)号：US07943997B2
公开(公告)日：2011-05-17
申请号：US12104683
申请日：2008-04-17
申请人： James W. Adkisson , Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , Edward J. Nowak
发明人： James W. Adkisson , Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , Edward J. Nowak
IPC分类号： H01L27/12
CPC分类号： H01L29/78603 , H01L29/66621 , H01L29/78645 , H01L29/78648 , H01L29/78696
摘要： Disclosed are embodiments of a field effect transistor (FET) and, more particularly, a fully-depleted, thin-body (FDTB) FET that allows for scaling with minimal short channel effects, such as drain induced barrier lowering (DIBL) and saturation threshold voltage (Vtsat) roll-off, at shorter channel lengths. The FDTB FET embodiments are configured with either an edge back-gate or split back-gate that can be biased in order to selectively adjust the potential barrier between the source/drain regions and the channel region for minimizing off-state leakage current between the drain region and the source region and/or for varying threshold voltage. These unique back-gate structures avoid the need for halo doping to ensure linear threshold voltage (Vtlin) roll-up at smaller channel lengths and, thus, avoid across-chip threshold voltage variations due to random doping fluctuations. Also disclosed are method embodiments for forming such FETs.
摘要翻译：公开了场效应晶体管（FET）的具体实施例，更具体地说，是允许以最小的短沟道效应（例如漏极感应势垒降低（DIBL）和饱和阈值））进行缩放的完全耗尽的薄体（FDTB）FET 电压（Vtsat）滚降，通道长度较短。 FDTB FET实施例配置有可被偏置的边缘背栅极或分支反向栅极，以便选择性地调节源极/漏极区域和沟道区域之间的势垒，以最小化漏极之间的截止状态漏电流区域和源极区域和/或用于改变阈值电压。这些独特的背栅结构避免了对光晕掺杂的需要，以确保较小通道长度的线性阈值电压（Vtlin）汇总，从而避免由于随机掺杂波动引起的跨芯片阈值电压变化。还公开了用于形成这种FET的方法实施例。

7. 发明授权

US08946027B2 Replacement-gate FinFET structure and process 有权
标题翻译：替代栅FinFET结构和工艺
公开(公告)号：US08946027B2
公开(公告)日：2015-02-03
申请号：US13367725
申请日：2012-02-07
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L29/66795 , H01L29/785
摘要： A fin field effect transistor (FinFET) structure and method of making the FinFET including a silicon fin that includes a channel region and source/drain (S/D) regions, formed on each end of the channel region, where an entire bottom surface of the channel region contacts a top surface of a lower insulator and bottom surfaces of the S/D regions contact first portions of top surfaces of a lower silicon germanium (SiGe) layer. The FinFET structure also includes extrinsic S/D regions that contact a top surface and both side surfaces of each of the S/D regions and second portions of top surfaces of the lower SiGe layer. The FinFET structure further includes a replacement gate or gate stack that contacts a conformal dielectric, formed over a top surface and both side surfaces of the channel region.
摘要翻译：鳍状场效应晶体管（FinFET）结构和制造FinFET的方法，其包括形成在沟道区的每个端部上的沟道区和源/漏（S / D）区的硅鳍，其中整个底表面沟道区域接触下绝缘体的顶表面，S / D区的底表面接触下硅锗（SiGe）层的顶表面的第一部分。 FinFET结构还包括接触顶部表面的外部S / D区域和下部SiGe层的顶表面的每个S / D区域和第二部分的两个侧表面。 FinFET结构还包括形成在通道区域的顶表面和两个侧表面上的适形电介质的替代栅极或栅极堆叠。

8. 发明授权

US08698245B2 Partially depleted (PD) semiconductor-on-insulator (SOI) field effect transistor (FET) structure with a gate-to-body tunnel current region for threshold voltage (VT) lowering and method of forming the structure 有权
标题翻译：部分耗尽（PD）绝缘体上半导体（SOI）场效应晶体管（FET）结构，具有用于阈值电压（VT）降低的栅 - 体隧道电流区域和形成结构的方法
公开(公告)号：US08698245B2
公开(公告)日：2014-04-15
申请号：US12967329
申请日：2010-12-14
申请人： Brent A. Anderson , Andres Bryant , Jiale Liang , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Jiale Liang , Edward J. Nowak
IPC分类号： H01L27/12
CPC分类号： H01L29/78 , H01L21/26506 , H01L29/32 , H01L29/66477 , H01L29/78612
摘要： Disclosed are embodiments of a field effect transistor with a gate-to-body tunnel current region (GTBTCR) and a method. In one embodiment, a gate, having adjacent sections with different conductivity types, traverses the center portion of a semiconductor layer to create, within the center portion, a channel region and a GTBTCR below the adjacent sections having the different conductivity types, respectively. In another embodiment, a semiconductor layer has a center portion with a channel region and a GTBTCR. The GTBTCR comprises: a first implant region adjacent to and doped with a higher concentration of the same first conductivity type dopant as the channel region; a second implant region, having a second conductivity type, adjacent to the first implant region; and an enhanced generation and recombination region between the implant regions. A gate with the second conductivity type traverses the center portion.
摘要翻译：公开了具有栅对体隧道电流区域（GTBTCR）的场效应晶体管的实施例和方法。在一个实施例中，具有不同导电类型的相邻部分的栅极穿过半导体层的中心部分，以在中心部分内分别在具有不同导电类型的相邻部分之下分别形成沟道区域和GTBTCR。在另一个实施例中，半导体层具有具有沟道区域的中心部分和GTBTCR。 GTBTCR包括：与沟道区相邻并掺杂相同的第一导电类型掺杂剂的较高浓度的第一注入区; 具有第二导电类型的与第一植入区相邻的第二植入区; 以及植入区域之间的增强的生成和重组区域。具有第二导电类型的栅极穿过中心部分。

9. 发明授权

US08580601B2 Pixel sensor cell with a dual work function gate electrode 有权
标题翻译：具有双功能栅极电极的像素传感器单元
公开(公告)号：US08580601B2
公开(公告)日：2013-11-12
申请号：US13571986
申请日：2012-08-10
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , John Joseph Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , John Joseph Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L21/00
CPC分类号： H01L27/14614
摘要： Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. The pixel sensor cell has a gate structure that includes a gate dielectric and a gate electrode on the gate dielectric. The gate electrode includes a layer with first and second sections that have a juxtaposed relationship on the gate dielectric. The second section of the gate electrode is comprised of a conductor, such as doped polysilicon or a metal. The first section of the gate electrode is comprised of a metal having a higher work function than the conductor comprising the second section so that the gate structure has an asymmetric threshold voltage.
摘要翻译：像素传感器单元，制造像素传感器单元的方法以及像素传感器单元的设计结构。像素传感器单元具有在栅极电介质上包括栅极电介质和栅电极的栅极结构。栅极电极包括具有在栅极电介质上具有并置关系的第一和第二部分的层。栅电极的第二部分由诸如掺杂多晶硅或金属的导体组成。栅电极的第一部分由具有比包括第二部分的导体更高的功函的金属组成，使得栅极结构具有非对称阈值电压。

10. 发明授权

US08536018B1 Maskless inter-well deep trench isolation structure and methods of manufacture 有权
标题翻译：无掩膜深沟槽隔离结构及制造方法
公开(公告)号：US08536018B1
公开(公告)日：2013-09-17
申请号：US13467314
申请日：2012-05-09
申请人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Michael A. Guillorn , Ryoji Hasumi , Edward J. Nowak , Mickey H. Yu
发明人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Michael A. Guillorn , Ryoji Hasumi , Edward J. Nowak , Mickey H. Yu
IPC分类号： H01L27/108
CPC分类号： H01L21/76283 , H01L21/76232 , H01L21/84
摘要： A low power maskless inter-well deep trench isolation structure and methods of manufacture such structure are provided. A method includes depositing a plurality of layers over a substrate, and forming a layer over the plurality of layers. The method also includes forming well structures in the substrate, and forming sidewall spacers at opposing sides of the layer. The method further includes forming a self-aligned deep trench in the substrate to below the well structures, by removing the sidewall spacers and portions of the substrate aligned with an opening formed by the removal of the sidewall spacers. The method also includes forming a shallow trench in alignment with the deep trench. The method further includes forming shallow trench isolation structures and deep trench isolation structures by filling the shallow trench and the deep trench with insulator material.
摘要翻译：提供了一种低功率无掩膜深沟槽隔离结构及其制造方法。一种方法包括在衬底上沉积多个层，并在多个层上形成层。该方法还包括在衬底中形成阱结构，以及在层的相对侧形成侧壁间隔物。该方法还包括通过去除侧壁间隔件和与通过去除侧壁间隔件形成的开口对准的衬底的部分，将衬底中的自对准深沟槽形成在阱结构下方。该方法还包括形成与深沟槽对准的浅沟槽。该方法还包括通过用绝缘体材料填充浅沟槽和深沟槽来形成浅沟槽隔离结构和深沟槽隔离结构。

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