专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120315736A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20120315736A1
公开(公告)日：2012-12-13
申请号：US13585394
申请日：2012-08-14
申请人： Toshiyuki Iwamoto , Gen Tsutsui
发明人： Toshiyuki Iwamoto , Gen Tsutsui
IPC分类号： H01L21/336
CPC分类号： H01L21/823431 , H01L21/823412 , H01L21/823462
摘要： A method of manufacturing a semiconductor device includes forming a first region including a FinFET (Fin Field Effect Transistor), forming a second region including a PlanarFET (Planar Field Effect Transistor), forming first extension regions in the plurality of fins in the first region, forming second extension regions in the second region using the second gate electrode as a mask, forming first side walls and second side walls on side surfaces of the first gate electrode and on side surfaces of the second gate electrode, respectively, and forming a source and a drain of the FinFET in the first region using the first gate electrode and first side walls as masks and forming a source and a drain of the PlanarFET in the second region by an ion implantation method using the second gate electrode and second side walls as masks, at the same time.
摘要翻译：一种制造半导体器件的方法包括：形成包括FinFET（Fin场效应晶体管）的第一区域，形成包括平面场效应晶体管的平面场效应晶体管的平面场效应晶体管的第二区域，形成第一区域中的多个鳍片的第一延伸区域; 使用所述第二栅电极作为掩模在所述第二区域中形成第二延伸区域，分别在所述第一栅电极的侧表面和所述第二栅电极的侧表面上分别形成第一侧壁和第二侧壁，以及形成源使用第一栅电极和第一侧壁作为掩模在第一区域中的FinFET的漏极，并且通过使用第二栅电极和第二侧壁作为掩模的离子注入方法在第二区域中形成平面FET的源极和漏极，与此同时。

2. 发明申请

US20100123200A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20100123200A1
公开(公告)日：2010-05-20
申请号：US12591040
申请日：2009-11-05
申请人： Gen Tsutsui
发明人： Gen Tsutsui
IPC分类号： H01L27/088 , H01L21/8236
CPC分类号： H01L21/823462 , H01L21/82345
摘要： Provided is a semiconductor device which includes, on the same semiconductor substrate, a first FET and a second FET higher in threshold voltage than the first FET. The first FET includes a first gate insulating film and a first gate electrode. The second FET includes a second gate insulating film and a second gate electrode. The first gate electrode, the second gate insulating film, and the second gate electrode contain at least one metal element selected from the group consisting of Hf, Zr, Al, La, Pr, Y, Ta, and W. Concentration of the at least one metal element at an interface between the second gate insulating film and the second gate electrode in the second FET is higher than concentration of the at least one metal element at an interface between the first gate insulating film and the first gate electrode in the first FET.
摘要翻译：提供一种半导体器件，其在同一半导体衬底上包括比第一FET高的阈值电压的第一FET和第二FET。第一FET包括第一栅极绝缘膜和第一栅电极。第二FET包括第二栅极绝缘膜和第二栅电极。第一栅极电极，第二栅极绝缘膜和第二栅极电极含有选自Hf，Zr，Al，La，Pr，Y，Ta和W中的至少一种金属元素。在第二FET中的第二栅极绝缘膜和第二栅电极之间的界面处的一个金属元件高于第一FET中第一栅极绝缘膜和第一栅极之间的界面处的至少一个金属元件的浓度。

3. 发明申请

US20100117156A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20100117156A1
公开(公告)日：2010-05-13
申请号：US12617434
申请日：2009-11-12
申请人： Gen TSUTSUI , Kiyotaka IMAI
发明人： Gen TSUTSUI , Kiyotaka IMAI
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L27/088 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823475 , H01L29/785
摘要： A semiconductor device includes a first transistor, a second transistor, a first interconnect, a second interconnect, and a first gate electrode. The first gate electrode is a gate electrode of the first and second transistors and extends linearly over first and second channel regions. In addition, a first source of the first transistor is located at the opposite side of a second source of the second transistor with the first gate electrode interposed therebetween, and a first drain of the first transistor is located at the opposite side of a second drain of the second transistor with the first gate electrode interposed therebetween.
摘要翻译：半导体器件包括第一晶体管，第二晶体管，第一互连，第二互连和第一栅电极。第一栅电极是第一和第二晶体管的栅电极，并且在第一和第二沟道区上线性延伸。此外，第一晶体管的第一源位于第二晶体管的第二源极的相反侧，第一栅电极介于其间，第一晶体管的第一漏极位于第二漏极的相对侧的第二晶体管，其间插入有第一栅电极。

4. 发明申请

US20100013017A1 Method of manufacturing semiconductor device, and semiconductor device 有权
标题翻译：制造半导体器件的方法和半导体器件
公开(公告)号：US20100013017A1
公开(公告)日：2010-01-21
申请号：US12458337
申请日：2009-07-08
申请人： Gen Tsutsui
发明人： Gen Tsutsui
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L21/823462
摘要： A method of manufacturing a semiconductor device including implanting an element selected from fluorine and nitrogen, over the entire region of a semiconductor substrate; oxidizing the semiconductor substrate to thereby form a first oxide film over the surface of the semiconductor substrate; selectively removing the first oxide film in a partial region; oxidizing the semiconductor substrate in the partial region to thereby form a second oxide film thinner than the first oxide film in the partial region; and forming gates to thereby form transistors.
摘要翻译：一种制造半导体器件的方法，包括在半导体衬底的整个区域上植入选自氟和氮的元素; 氧化半导体衬底，从而在半导体衬底的表面上形成第一氧化膜; 选择性地去除部分区域中的第一氧化物膜; 在部分区域中氧化半导体衬底，从而形成比部分区域中的第一氧化膜更薄的第二氧化物膜; 并形成栅极从而形成晶体管。

5. 发明申请

US20080093699A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080093699A1
公开(公告)日：2008-04-24
申请号：US11874221
申请日：2007-10-18
申请人： Tomohisa ABE , Gen Tsutsui , Tadashi Fukase , Yasushi Nakahara , Kiyotaka Imai
发明人： Tomohisa ABE , Gen Tsutsui , Tadashi Fukase , Yasushi Nakahara , Kiyotaka Imai
IPC分类号： H01L29/00
CPC分类号： H01L21/2652 , H01L21/82385 , H01L27/0207 , H01L27/105 , H01L27/11 , H01L27/1116 , H01L29/105
摘要： The semiconductor device includes a plurality of transistors at least having different channel widths from each other. Threshold voltages of those transistors are set to be substantially equal to each other, by using both of substantially the same channel dose for each of those transistors, and work function control using a predetermined metal to be deposited on a gate insulating of those transistors and/or a gate electrode material of each of those transistors (that is, work function control based on a gate structure (gate insulating film and/or gate electrode) with respect to a channel region of each of those transistors).
摘要翻译：半导体器件包括至少具有彼此不同沟道宽度的多个晶体管。这些晶体管的阈值电压通过使用这些晶体管中的每一个的基本上相同的通道剂量和使用要沉积在那些晶体管的栅极绝缘上的预定金属的功函数控制来设置为彼此基本相等，和/ 或这些晶体管中的每一个的栅极电极材料（即，相对于这些晶体管的沟道区域，基于栅极结构（栅极绝缘膜和/或栅电极）的功函数控制）。

6. 发明授权

US08604546B1 Reducing gate resistance in nonplanar multi-gate transistor 失效
标题翻译：降低非平面多栅极晶体管的栅极电阻
公开(公告)号：US08604546B1
公开(公告)日：2013-12-10
申请号：US13544176
申请日：2012-07-09
申请人： Andres Bryant , Theodorus E. Standaert , Gen Tsutsui , Chun-Chen Yeh
发明人： Andres Bryant , Theodorus E. Standaert , Gen Tsutsui , Chun-Chen Yeh
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7845
摘要： A semiconductor transistor structure has a plurality of fins, a cap on the center portion of the top of each of the fins, a conductive liner lining the cap and the sidewalls of the center portion of the fins, and an insulator between the center portions of the fins. The insulator contacts the conductive liner, and the fins extend further from the surface of the substrate relative to an amount the insulator extends from the surface of the substrate. The structure further includes a conductive layer positioned on the insulator between the center portions of the fins and positioned between the cap of the fins. The conductive layer contacts the conductive liner.
摘要翻译：半导体晶体管结构具有多个散热片，在每个翅片的顶部的中心部分上的盖，衬套盖的导电衬垫和散热片的中心部分的侧壁以及中心部分之间的绝缘体翅片绝缘体接触导电衬垫，并且散热片相对于绝缘体从衬底的表面延伸的量从衬底的表面进一步延伸。所述结构还包括位于所述绝缘体之间的导电层，所述导电层位于所述翅片的中心部分之间并且位于所述翅片的帽之间。导电层接触导电衬垫。

7. 发明授权

US08088677B2 Method of manufacturing semiconductor device, and semiconductor device 有权
标题翻译：制造半导体器件的方法和半导体器件
公开(公告)号：US08088677B2
公开(公告)日：2012-01-03
申请号：US12458337
申请日：2009-07-08
申请人： Gen Tsutsui
发明人： Gen Tsutsui
IPC分类号： H01L21/00
CPC分类号： H01L21/823462
摘要： A method of manufacturing a semiconductor device including implanting an element selected from fluorine and nitrogen, over the entire region of a semiconductor substrate; oxidizing the semiconductor substrate to thereby form a first oxide film over the surface of the semiconductor substrate; selectively removing the first oxide film in a partial region; oxidizing the semiconductor substrate in the partial region to thereby form a second oxide film thinner than the first oxide film in the partial region; and forming gates to thereby form transistors.
摘要翻译：一种制造半导体器件的方法，包括在半导体衬底的整个区域上植入选自氟和氮的元素; 氧化半导体衬底，从而在半导体衬底的表面上形成第一氧化膜; 选择性地去除部分区域中的第一氧化物膜; 在部分区域中氧化半导体衬底，从而形成比部分区域中的第一氧化膜更薄的第二氧化物膜; 并形成栅极从而形成晶体管。

8. 发明申请

US20100270621A1 Semiconductor device and method of manufacturing the semiconductor device 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20100270621A1
公开(公告)日：2010-10-28
申请号：US12662498
申请日：2010-04-20
申请人： Toshiyuki Iwamoto , Gen Tsutsui
发明人： Toshiyuki Iwamoto , Gen Tsutsui
IPC分类号： H01L27/088
CPC分类号： H01L21/823431 , H01L21/823412 , H01L21/823462
摘要： A semiconductor device includes: a FinFET (Fin Field Effect Transistor); and a PlanarFET (Planar Field Effect Transistor). The FinFET is provided on a chip. The PlanarFET is provided on the chip. A second gate insulating layer of the PlanarFET is thicker than a first gate insulating layer of the FinFET.
摘要翻译：半导体器件包括：FinFET（Fin场效应晶体管）; 和平面场效应晶体管（Planar Field Effect Transistor）。 FinFET在芯片上提供。在芯片上提供了PlanarFET。平面FET的第二栅极绝缘层比FinFET的第一栅极绝缘层厚。

9. 发明授权

US08269271B2 Hybrid planarFET and FinFET provided on a chip 失效
标题翻译：混合平面FET和FinFET提供在芯片上
公开(公告)号：US08269271B2
公开(公告)日：2012-09-18
申请号：US12662498
申请日：2010-04-20
申请人： Toshiyuki Iwamoto , Gen Tsutsui
发明人： Toshiyuki Iwamoto , Gen Tsutsui
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823431 , H01L21/823412 , H01L21/823462
摘要： A semiconductor device includes: a FinFET (Fin Field Effect Transistor); and a PlanarFET (Planar Field Effect Transistor). The FinFET is provided on a chip. The PlanarFET is provided on the chip. A second gate insulating layer of the PlanarFET is thicker than a first gate insulating layer of the FinFET.
摘要翻译：半导体器件包括：FinFET（Fin场效应晶体管）; 和平面场效应晶体管（Planar Field Effect Transistor）。 FinFET在芯片上提供。在芯片上提供了PlanarFET。平面FET的第二栅极绝缘层比FinFET的第一栅极绝缘层厚。

10. 发明授权

US08586437B2 Semiconductor device and method of manufacturing the semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08586437B2
公开(公告)日：2013-11-19
申请号：US13585394
申请日：2012-08-14
申请人： Toshiyuki Iwamoto , Gen Tsutsui
发明人： Toshiyuki Iwamoto , Gen Tsutsui
IPC分类号： H01L21/8234 , H01L27/088
CPC分类号： H01L21/823431 , H01L21/823412 , H01L21/823462
摘要： A method of manufacturing a semiconductor device includes forming a first region including a FinFET (Fin Field Effect Transistor), forming a second region including a PlanarFET (Planar Field Effect Transistor), forming first extension regions in the plurality of fins in the first region, forming second extension regions in the second region using the second gate electrode as a mask, forming first side walls and second side walls on side surfaces of the first gate electrode and on side surfaces of the second gate electrode, respectively, and forming a source and a drain of the FinFET in the first region using the first gate electrode and first side walls as masks and forming a source and a drain of the PlanarFET in the second region by an ion implantation method using the second gate electrode and second side walls as masks, at the same time.
摘要翻译：一种制造半导体器件的方法包括：形成包括FinFET（Fin场效应晶体管）的第一区域，形成包括平面场效应晶体管的平面场效应晶体管的平面场效应晶体管的第二区域，形成第一区域中的多个鳍片的第一延伸区域; 使用所述第二栅电极作为掩模在所述第二区域中形成第二延伸区域，分别在所述第一栅电极的侧表面和所述第二栅电极的侧表面上分别形成第一侧壁和第二侧壁，以及形成源使用第一栅电极和第一侧壁作为掩模在第一区域中的FinFET的漏极，并且通过使用第二栅电极和第二侧壁作为掩模的离子注入方法在第二区域中形成平面FET的源极和漏极，与此同时。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式