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1. 发明授权

US08723262B2 SOI FinFET with recessed merged fins and liner for enhanced stress coupling 有权
标题翻译： SOI FinFET具有凹入的合并翅片和衬垫，用于增强应力耦合
公开(公告)号：US08723262B2
公开(公告)日：2014-05-13
申请号：US13606893
申请日：2012-09-07
申请人： Veeraraghavan S. Basker , Huiming Bu , Effendi Leobandung , Theodorus E. Standaert , Tenko Yamashita , Chun-Chen Yeh
发明人： Veeraraghavan S. Basker , Huiming Bu , Effendi Leobandung , Theodorus E. Standaert , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/7843 , H01L29/6656 , H01L29/66795
摘要： FinFETS and methods for making FinFETs with a recessed stress liner. A method includes providing an SOI substrate with fins, forming a gate over the fins, forming an off-set spacer on the gate, epitaxially growing a film to merge the fins, depositing a dummy spacer around the gate, and recessing the merged epi film. Silicide is then formed on the recessed merged epi film followed by deposition of a stress liner film over the FinFET. By using a recessed merged epi process, a MOSFET with a vertical silicide (i.e. perpendicular to the substrate) can be formed. The perpendicular silicide improves spreading resistance.
摘要翻译： FinFET和用于制造具有凹陷应力衬垫的FinFET的方法。一种方法包括向SOI衬底提供翅片，在鳍片上形成栅极，在栅极上形成偏置间隔物，外延生长膜以合并鳍片，在栅极周围沉积虚拟间隔物，并使合并的膜片膜凹陷。然后在凹陷的合并epi膜上形成硅化物，然后在FinFET上沉积应力衬垫膜。通过使用凹入的合并epi工艺，可以形成具有垂直硅化物（即垂直于衬底）的MOSFET。垂直硅化物提高了耐扩散性。

2. 发明申请

US20140087526A1 MULTI-GATE FIELD EFFECT TRANSISTOR DEVICES 审中-公开
标题翻译：多门场效应晶体管器件
公开(公告)号：US20140087526A1
公开(公告)日：2014-03-27
申请号：US13628251
申请日：2012-09-27
申请人： Veeraraghavan S. Basker , Tenko Yamashita , Chun-Chen Yeh
发明人： Veeraraghavan S. Basker , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66545 , H01L29/66795
摘要： A method for fabricating a field effect transistor device includes patterning a semiconductor fin on a substrate insulator layer, the substrate insulator layer arranged on a substrate, patterning a dummy gate stack over a portion of the fin, forming spacers adjacent to the dummy gate stack, removing the dummy gate stack to form a cavity that exposes portions of the substrate insulator layer and the fin, removing exposed portions of the substrate insulator layer to increase a depth of the cavity, removing a region of the substrate insulator layer from beneath the fin to suspend a portion of the fin above the substrate insulator layer, forming a gate stack in the cavity, removing a portion of the gate stack in the cavity to expose a portion of a dielectric layer arranged on the fin, and depositing an insulator material in the cavity.
摘要翻译：一种用于制造场效应晶体管器件的方法，包括在衬底绝缘体层上图形化半导体鳍片，将衬底绝缘体层布置在衬底上，在鳍片的一部分上构图虚拟栅极堆叠，形成与虚拟栅极叠层相邻的间隔区，去除虚拟栅极堆叠以形成露出衬底绝缘体层和鳍的部分的空腔，去除衬底绝缘体层的暴露部分以增加空腔的深度，从衬底下方去除衬底绝缘体层的区域到悬挂在衬底绝缘体层上方的鳍片的一部分，在空腔中形成栅极叠层，去除空腔中的栅极叠层的一部分以暴露布置在鳍片上的电介质层的一部分，并将绝缘体材料沉积在腔。

3. 发明申请

US20130307079A1 ETCH RESISTANT BARRIER FOR REPLACEMENT GATE INTEGRATION 审中-公开
标题翻译：用于替换门槛整合的耐蚀阻挡层
公开(公告)号：US20130307079A1
公开(公告)日：2013-11-21
申请号：US13494511
申请日：2012-06-12
申请人： HEMANTH JAGANNATHAN , SANJAY MEHTA , CHUN-CHEN YEH
发明人： HEMANTH JAGANNATHAN , SANJAY MEHTA , CHUN-CHEN YEH
IPC分类号： H01L29/78
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/66545 , H01L29/785
摘要： Semiconductor devices and methods of their fabrication are disclosed. One device includes a plurality of gates and a dielectric gap filling material with a pre-determined aspect ratio that is between the gates. The device further includes an etch resistant nitride layer that is configured to maintain the aspect ratio of the dielectric gap filling material during fabrication of the device and is disposed above the dielectric gap filling material and between the plurality of gates.
摘要翻译：公开了半导体器件及其制造方法。一个装置包括多个栅极和具有在门之间的预定宽高比的电介质间隙填充材料。该器件还包括耐蚀刻氮化物层，其被配置为在器件的制造过程中保持电介质间隙填充材料的纵横比并且设置在电介质间隙填充材料之上和多个栅极之间。

4. 发明授权

US08530315B2 finFET with fully silicided gate 有权
标题翻译： finFET具有完全硅化的栅极
公开(公告)号：US08530315B2
公开(公告)日：2013-09-10
申请号：US13614662
申请日：2012-09-13
申请人： Ming Cai , Dechao Guo , Chun-chen Yeh
发明人： Ming Cai , Dechao Guo , Chun-chen Yeh
IPC分类号： H01L21/336 , H01L21/84
CPC分类号： H01L29/785 , H01L27/1211
摘要： A method is provided for fabricating a finFET device. Multiple fin structures are formed over a BOX layer, and a gate stack is formed on the BOX layer. The fin structures each include a semiconductor layer and extend in a first direction, and the gate stack is formed over the fin structures and extends in a second direction. The gate stack includes dielectric and polysilicon layers. Gate spacers are formed on vertical sidewalls of the gate stack, and an epi layer is deposited over the fin structures. Ions are implanted to form source and drain regions, and the gate spacers are etched so that their upper surface is below an upper surface of the gate stack. After etching the gate spacers, silicidation is performed to fully silicide the polysilicon layer of the gate stack and to form silicide regions in an upper surface of the source and drain regions.
摘要翻译：提供了一种用于制造finFET器件的方法。多个鳍结构形成在BOX层上，并且在BOX层上形成栅堆叠。翅片结构各自包括半导体层并且在第一方向上延伸，并且栅极堆叠形成在鳍状结构上并沿第二方向延伸。栅堆叠包括电介质层和多晶硅层。栅极间隔物形成在栅极堆叠的垂直侧壁上，并且外延层沉积在鳍结构上。植入离子以形成源极和漏极区域，并且栅极间隔物被蚀刻，使得它们的上表面在栅极堆叠的上表面下方。在蚀刻栅极间隔物之后，进行硅化以完全硅化栅叠层的多晶硅层并在源区和漏区的上表面中形成硅化物区。

5. 发明申请

US20130178020A1 FINFET WITH FULLY SILICIDED GATE 有权
公开(公告)号：US20130178020A1
公开(公告)日：2013-07-11
申请号：US13614662
申请日：2012-09-13
申请人： Ming CAI , Dechao Guo , Chun-chen Yeh
发明人： Ming CAI , Dechao Guo , Chun-chen Yeh
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L27/1211
摘要： A method is provided for fabricating a finFET device. Multiple fin structures are formed over a BOX layer, and a gate stack is formed on the BOX layer. The fin structures each include a semiconductor layer and extend in a first direction, and the gate stack is formed over the fin structures and extends in a second direction. The gate stack includes dielectric and polysilicon layers. Gate spacers are formed on vertical sidewalls of the gate stack, and an epi layer is deposited over the fin structures. Ions are implanted to form source and drain regions, and the gate spacers are etched so that their upper surface is below an upper surface of the gate stack. After etching the gate spacers, silicidation is performed to fully silicide the polysilicon layer of the gate stack and to form silicide regions in an upper surface of the source and drain regions.

6. 发明申请

US20130175594A1 INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC 有权
公开(公告)号：US20130175594A1
公开(公告)日：2013-07-11
申请号：US13551714
申请日：2012-07-18
申请人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni , Tenko Yamashita , Chun-Chen Yeh
发明人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L27/12 , H01L21/782
CPC分类号： H01L21/84 , H01L27/10861 , H01L27/1087 , H01L27/10873 , H01L27/10894 , H01L27/10897 , H01L27/1108 , H01L27/1116 , H01L27/1203 , H01L29/945
摘要： An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.

7. 发明申请

US20130164890A1 METHOD FOR FABRICATING FINFET WITH MERGED FINS AND VERTICAL SILICIDE 有权
标题翻译：用合适的FINS和垂直硅胶制造FINFET的方法
公开(公告)号：US20130164890A1
公开(公告)日：2013-06-27
申请号：US13617709
申请日：2012-09-14
申请人： Veeraraghavan S. BASKER , Andres BRYANT , Huiming BU , Wilfried HAENSCH , Effendi LEOBANDUNG , Chung-Hsun LIN , Theodorus E. STANDAERT , Tenko YAMASHITA , Chun-chen YEH
发明人： Veeraraghavan S. BASKER , Andres BRYANT , Huiming BU , Wilfried HAENSCH , Effendi LEOBANDUNG , Chung-Hsun LIN , Theodorus E. STANDAERT , Tenko YAMASHITA , Chun-chen YEH
IPC分类号： H01L21/336
CPC分类号： H01L29/41791 , H01L29/66795
摘要： A method is provided for fabricating a finFET device. Fin structures are formed over a BOX layer. The fin structures include a semiconductor layer and extend in a first direction. A gate stack is formed on the BOX layer over the fin structures and extending in a second direction. The gate stack includes a high-K dielectric layer and a metal gate. Gate spacers are formed on sidewalls of the gate stack, and an epi layer is deposited to merge the fin structures. Ions are implanted to form source and drain regions, and dummy spacers are formed on sidewalls of the gate spacers. The dummy spacers are used as a mask to recess or completely remove an exposed portion of the epi layer. Silicidation forms silicide regions that abut the source and drain regions and each include a vertical portion located on the vertical sidewall of the source or drain region.
摘要翻译：提供了一种用于制造finFET器件的方法。翅片结构形成在BOX层上。翅片结构包括半导体层并沿第一方向延伸。栅极叠层形成在鳍状结构上的BOX层上并沿第二方向延伸。栅极堆叠包括高K电介质层和金属栅极。栅极间隔物形成在栅极堆叠的侧壁上，并且沉积外延层以使翅片结构合并。植入离子以形成源极和漏极区，并且在栅极间隔物的侧壁上形成虚设间隔物。虚拟间隔物用作掩模以凹进或完全去除外延层的暴露部分。硅化形成邻接源极和漏极区域的硅化物区域，并且每个都包括位于源极或漏极区域的垂直侧壁上的垂直部分。

8. 发明授权

US08470678B2 Tensile stress enhancement of nitride film for stressed channel field effect transistor fabrication 失效
标题翻译：用于应力沟道场效应晶体管制造的氮化膜的拉伸应力增强
公开(公告)号：US08470678B2
公开(公告)日：2013-06-25
申请号：US13034045
申请日：2011-02-24
申请人： Ming Cai , Dechao Guo , Chun-chen Yeh , Pranita Kulkarni
发明人： Ming Cai , Dechao Guo , Chun-chen Yeh , Pranita Kulkarni
IPC分类号： H01L21/00
CPC分类号： H01L29/7843 , H01L21/3105 , H01L21/76814 , H01L21/76825 , H01L21/76834
摘要： A method for inducing a tensile stress in a channel of a field effect transistor (FET) includes forming a nitride film over the FET; forming a contact hole to the FET through the nitride film; and performing ultraviolet (UV) curing of the nitride film after forming the contact hole to the FET through the nitride film, wherein the UV cured nitride film induces the tensile stress in the channel of the FET.
摘要翻译：用于在场效应晶体管（FET）的沟道中诱发拉伸应力的方法包括在FET上形成氮化物膜; 通过氮化物膜形成与FET的接触孔; 并且通过氮化物膜在形成接触孔之后对氮化物膜进行紫外（UV）固化，其中，UV固化的氮化物膜在FET的沟道中引起拉伸应力。

9. 发明申请

US20130154029A1 EMBEDDED STRESSORS FOR MULTIGATE TRANSISTOR DEVICES 有权
公开(公告)号：US20130154029A1
公开(公告)日：2013-06-20
申请号：US13611068
申请日：2012-09-12
申请人： Ming Cai , Dechao Guo , Pranita Kulkarni , Chun-Chen Yeh
发明人： Ming Cai , Dechao Guo , Pranita Kulkarni , Chun-Chen Yeh
IPC分类号： H01L29/78
CPC分类号： H01L29/66795 , H01L29/165 , H01L29/7848 , H01L29/785
摘要： Multigate transistor devices and methods of their fabrication are disclosed. In accordance with one method, a fin and a gate structure that is disposed on a plurality of surfaces of the fin are formed. In addition, at least a portion of an extension of the fin is removed to form a recessed portion that is below the gate structure, is below a channel region of the fin, and includes at least one angled indentation. Further, a terminal extension is grown in the at least one angled indentation below the channel region and along a surface of the channel region such that the terminal extension provides a stress on the channel region to enhance charge carrier mobility in the channel region.

10. 发明申请

US20130082329A1 MULTI-GATE FIELD-EFFECT TRANSISTORS WITH VARIABLE FIN HEIGHTS 审中-公开
标题翻译：具有可变熔接高度的多栅极场效应晶体管
公开(公告)号：US20130082329A1
公开(公告)日：2013-04-04
申请号：US13251815
申请日：2011-10-03
申请人： Hsueh-Chung Chen , Su Chen Fan , Theodorus E. Standaert , Chun-Chen Yeh
发明人： Hsueh-Chung Chen , Su Chen Fan , Theodorus E. Standaert , Chun-Chen Yeh
IPC分类号： H01L27/088 , H01L21/28 , H01L29/78
CPC分类号： H01L21/823431 , H01L27/0886
摘要： Multi-gate devices and methods of their fabrication are disclosed. A multi-gate device can include a gate structure and a plurality of fins. The gate structure envelops a plurality of surfaces of the fins, which are directly on a substrate that is composed of a semiconducting material. Each of the fins provides a channel between a respective source and a respective drain, is composed of the semiconducting material and is doped. A first fin of the plurality of fins has a first height that is different from a second height of a second fin of the plurality of fins such that drive currents of the first and second fins are different. Further, the first and second fins form a respective cohesive structure of the semiconducting material with the substrate. In addition, surfaces of the substrate that border the fins are disposed at a same vertical position.
摘要翻译：公开了多栅极器件及其制造方法。多栅极器件可以包括栅极结构和多个鳍。栅极结构包围鳍片的多个表面，其直接在由半导体材料构成的衬底上。每个翅片在相应的源和相应的漏极之间提供通道，由半导体材料组成并且被掺杂。多个翅片的第一翅片具有与多个翅片中的第二翅片的第二高度不同的第一高度，使得第一和第二翅片的驱动电流不同。此外，第一和第二散热片形成半导体材料与衬底的相应的内聚结构。此外，与翅片相接的基板的表面设置在相同的垂直位置。

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