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1. 发明授权

US08455313B1 Method for fabricating finFET with merged fins and vertical silicide 有权
标题翻译：使用合并翅片和垂直硅化物制造finFET的方法
公开(公告)号：US08455313B1
公开(公告)日：2013-06-04
申请号：US13617709
申请日：2012-09-14
申请人： Veeraraghavan S. Basker , Andres Bryant , Huiming Bu , Wilfried Haensch , Effendi Leobandung , Chung-Hsun Lin , Theodorus E. Standaert , Tenko Yamashita , Chun-chen Yeh
发明人： Veeraraghavan S. Basker , Andres Bryant , Huiming Bu , Wilfried Haensch , Effendi Leobandung , Chung-Hsun Lin , Theodorus E. Standaert , Tenko Yamashita , Chun-chen Yeh
IPC分类号： H01L21/336
CPC分类号： H01L29/41791 , H01L29/66795
摘要： A method is provided for fabricating a finFET device. Fin structures are formed over a BOX layer. The fin structures include a semiconductor layer and extend in a first direction. A gate stack is formed on the BOX layer over the fin structures and extending in a second direction. The gate stack includes a high-K dielectric layer and a metal gate. Gate spacers are formed on sidewalls of the gate stack, and an epi layer is deposited to merge the fin structures. Ions are implanted to form source and drain regions, and dummy spacers are formed on sidewalls of the gate spacers. The dummy spacers are used as a mask to recess or completely remove an exposed portion of the epi layer. Silicidation forms silicide regions that abut the source and drain regions and each include a vertical portion located on the vertical sidewall of the source or drain region.
摘要翻译：提供了一种用于制造finFET器件的方法。翅片结构形成在BOX层上。翅片结构包括半导体层并沿第一方向延伸。栅极叠层形成在鳍状结构上的BOX层上并沿第二方向延伸。栅极堆叠包括高K电介质层和金属栅极。栅极间隔物形成在栅极堆叠的侧壁上，并且沉积外延层以使翅片结构合并。植入离子以形成源极和漏极区，并且在栅极间隔物的侧壁上形成虚设间隔物。虚拟间隔物用作掩模以凹进或完全去除外延层的暴露部分。硅化形成邻接源极和漏极区域的硅化物区域，并且每个都包括位于源极或漏极区域的垂直侧壁上的垂直部分。

2. 发明授权

US08637931B2 finFET with merged fins and vertical silicide 有权
标题翻译： finFET具有合并翅片和垂直硅化物
公开(公告)号：US08637931B2
公开(公告)日：2014-01-28
申请号：US13337874
申请日：2011-12-27
申请人： Veeraraghavan S. Basker , Andres Bryant , Huiming Bu , Wilfried Haensch , Effendi Leobandung , Chung-Hsun Lin , Theodorus E. Standaert , Tenko Yamashita , Chun-chen Yeh
发明人： Veeraraghavan S. Basker , Andres Bryant , Huiming Bu , Wilfried Haensch , Effendi Leobandung , Chung-Hsun Lin , Theodorus E. Standaert , Tenko Yamashita , Chun-chen Yeh
IPC分类号： H01L27/12
CPC分类号： H01L29/41791 , H01L29/66795
摘要： A finFET device is provided. The finFET device includes a BOX layer, fin structures located over the BOX layer, a gate stack located over the fin structures, gate spacers located on vertical sidewalls of the gate stack, an epi layer covering the fin structures, source and drain regions located in the semiconductor layers of the fin structures, and silicide regions abutting the source and drain regions. The fin structures each comprise a semiconductor layer and extend in a first direction, and the gate stack extends in a second direction that is perpendicular. The gate stack comprises a high-K dielectric layer and a metal gate, and the epi layer merges the fin structures together. The silicide regions each include a vertical portion located on the vertical sidewall of the source or drain region.
摘要翻译：提供了finFET器件。 finFET器件包括BOX层，位于BOX层上方的翅片结构，位于鳍结构上方的栅极堆叠，位于栅叠层的垂直侧壁上的栅极隔离物，覆盖翅片结构的外延层，位于翅片结构的半导体层和邻接源极和漏极区域的硅化物区域。翅片结构各自包括半导体层并沿第一方向延伸，并且栅极堆叠沿垂直的第二方向延伸。栅极堆叠包括高K电介质层和金属栅极，并且外延层将鳍结构融合在一起。硅化物区域各自包括位于源极或漏极区域的垂直侧壁上的垂直部分。

3. 发明申请

US20130161744A1 FINFET WITH MERGED FINS AND VERTICAL SILICIDE 有权
标题翻译：具有合并的FINS和垂直硅胶的FINFET
公开(公告)号：US20130161744A1
公开(公告)日：2013-06-27
申请号：US13337874
申请日：2011-12-27
申请人： Veeraraghavan S. BASKER , Andres Bryant , Huiming Bu , Wilfried Haensch , Effendi Leobandung , Chung-Hsun Lin , Theodorus E. Standaert , Tenko Yamashita , Chun-chen Yeh
发明人： Veeraraghavan S. BASKER , Andres Bryant , Huiming Bu , Wilfried Haensch , Effendi Leobandung , Chung-Hsun Lin , Theodorus E. Standaert , Tenko Yamashita , Chun-chen Yeh
IPC分类号： H01L27/12 , H01L29/78 , H01L21/336
CPC分类号： H01L29/41791 , H01L29/66795
摘要： A finFET device is provided. The finFET device includes a BOX layer, fin structures located over the BOX layer, a gate stack located over the fin structures, gate spacers located on vertical sidewalls of the gate stack, an epi layer covering the fin structures, source and drain regions located in the semiconductor layers of the fin structures, and silicide regions abutting the source and drain regions. The fin structures each comprise a semiconductor layer and extend in a first direction, and the gate stack extends in a second direction that is perpendicular. The gate stack comprises a high-K dielectric layer and a metal gate, and the epi layer merges the fin structures together. The silicide regions each include a vertical portion located on the vertical sidewall of the source or drain region.
摘要翻译：提供了finFET器件。 finFET器件包括BOX层，位于BOX层上方的翅片结构，位于鳍结构上方的栅极堆叠，位于栅叠层的垂直侧壁上的栅极隔离物，覆盖翅片结构的外延层，位于翅片结构的半导体层和邻接源极和漏极区域的硅化物区域。翅片结构各自包括半导体层并沿第一方向延伸，并且栅极堆叠沿垂直的第二方向延伸。栅极堆叠包括高K电介质层和金属栅极，并且外延层将鳍结构融合在一起。硅化物区域各自包括位于源极或漏极区域的垂直侧壁上的垂直部分。

4. 发明申请

US20110175164A1 DEVICE STRUCTURE, LAYOUT AND FABRICATION METHOD FOR UNIAXIALLY STRAINED TRANSISTORS 有权
标题翻译：非均匀应变晶体管的器件结构，布局和制造方法
公开(公告)号：US20110175164A1
公开(公告)日：2011-07-21
申请号：US12689346
申请日：2010-01-19
申请人： Stephen W. Bedell , Huiming Bu , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz , Devendra K. Sadana , Chun-chen Yeh
发明人： Stephen W. Bedell , Huiming Bu , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz , Devendra K. Sadana , Chun-chen Yeh
IPC分类号： H01L27/12 , H01L21/86
CPC分类号： H01L21/823807 , H01L21/823814 , H01L27/0207 , H01L29/6656 , H01L29/66628 , H01L29/78 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.
摘要翻译：一种用于制造半导体器件的半导体器件和方法包括提供具有第一应变轴的应变半导体层，在应变半导体层的表面内形成有源区，其中有源区具有沿应变轴的纵向轴线并形成栅极结构在活跃地区。在应变半导体层的表面上方和与栅极结构相邻的有源区上形成升高的源/漏区，以形成晶体管器件。

5. 发明授权

US08513131B2 Fin field effect transistor with variable channel thickness for threshold voltage tuning 有权
标题翻译：具有可变通道厚度的Fin场效应晶体管用于阈值电压调谐
公开(公告)号：US08513131B2
公开(公告)日：2013-08-20
申请号：US13050101
申请日：2011-03-17
申请人： Ming Cai , Dechao Guo , Chung-hsun Lin , Chun-chen Yeh
发明人： Ming Cai , Dechao Guo , Chung-hsun Lin , Chun-chen Yeh
IPC分类号： H01L21/311
CPC分类号： H01L27/0886 , H01L21/3086 , H01L21/845 , H01L27/1211
摘要： A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers.
摘要翻译：一种形成集成电路（IC）的方法包括在基板上形成第一和第二多个间隔物，其中所述基板包括硅层，并且其中所述第一多个间隔件的厚度不同于所述第二多个间隔物; 并且使用所述第一和第二多个间隔物作为掩模来蚀刻所述衬底中的所述硅层，其中所述蚀刻的硅层形成第一多个和第二多个鳍状场效应晶体管（FINFET）沟道区，并且其中所述第一多个 FINFET通道区域各自具有对应于第一多个间隔物的厚度的相应厚度，并且其中第二多个FINFET沟道区域各自具有对应于第二多个间隔物的厚度的相应厚度。

6. 发明申请

US20120235247A1 FIN FIELD EFFECT TRANSISTOR WITH VARIABLE CHANNEL THICKNESS FOR THRESHOLD VOLTAGE TUNING 有权
标题翻译：具有用于阈值电压调谐的可变通道厚度的FIN场效应晶体管
公开(公告)号：US20120235247A1
公开(公告)日：2012-09-20
申请号：US13050101
申请日：2011-03-17
申请人： Ming Cai , Dechao Guo , Chung-hsun Lin , Chun-chen Yeh
发明人： Ming Cai , Dechao Guo , Chung-hsun Lin , Chun-chen Yeh
IPC分类号： H01L27/088 , H01L21/32
CPC分类号： H01L27/0886 , H01L21/3086 , H01L21/845 , H01L27/1211
摘要： A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers.
摘要翻译：一种形成集成电路（IC）的方法包括在基板上形成第一和第二多个间隔物，其中所述基板包括硅层，并且其中所述第一多个间隔件的厚度不同于所述第二多个间隔物; 并且使用所述第一和第二多个间隔物作为掩模来蚀刻所述衬底中的所述硅层，其中所述蚀刻的硅层形成第一多个和第二多个鳍状场效应晶体管（FINFET）沟道区，并且其中所述第一多个 FINFET通道区域各自具有对应于第一多个间隔物的厚度的相应厚度，并且其中第二多个FINFET沟道区域各自具有对应于第二多个间隔物的厚度的相应厚度。

7. 发明授权

US08530315B2 finFET with fully silicided gate 有权
标题翻译： finFET具有完全硅化的栅极
公开(公告)号：US08530315B2
公开(公告)日：2013-09-10
申请号：US13614662
申请日：2012-09-13
申请人： Ming Cai , Dechao Guo , Chun-chen Yeh
发明人： Ming Cai , Dechao Guo , Chun-chen Yeh
IPC分类号： H01L21/336 , H01L21/84
CPC分类号： H01L29/785 , H01L27/1211
摘要： A method is provided for fabricating a finFET device. Multiple fin structures are formed over a BOX layer, and a gate stack is formed on the BOX layer. The fin structures each include a semiconductor layer and extend in a first direction, and the gate stack is formed over the fin structures and extends in a second direction. The gate stack includes dielectric and polysilicon layers. Gate spacers are formed on vertical sidewalls of the gate stack, and an epi layer is deposited over the fin structures. Ions are implanted to form source and drain regions, and the gate spacers are etched so that their upper surface is below an upper surface of the gate stack. After etching the gate spacers, silicidation is performed to fully silicide the polysilicon layer of the gate stack and to form silicide regions in an upper surface of the source and drain regions.
摘要翻译：提供了一种用于制造finFET器件的方法。多个鳍结构形成在BOX层上，并且在BOX层上形成栅堆叠。翅片结构各自包括半导体层并且在第一方向上延伸，并且栅极堆叠形成在鳍状结构上并沿第二方向延伸。栅堆叠包括电介质层和多晶硅层。栅极间隔物形成在栅极堆叠的垂直侧壁上，并且外延层沉积在鳍结构上。植入离子以形成源极和漏极区域，并且栅极间隔物被蚀刻，使得它们的上表面在栅极堆叠的上表面下方。在蚀刻栅极间隔物之后，进行硅化以完全硅化栅叠层的多晶硅层并在源区和漏区的上表面中形成硅化物区。

8. 发明申请

US20130178020A1 FINFET WITH FULLY SILICIDED GATE 有权
公开(公告)号：US20130178020A1
公开(公告)日：2013-07-11
申请号：US13614662
申请日：2012-09-13
申请人： Ming CAI , Dechao Guo , Chun-chen Yeh
发明人： Ming CAI , Dechao Guo , Chun-chen Yeh
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L27/1211
摘要： A method is provided for fabricating a finFET device. Multiple fin structures are formed over a BOX layer, and a gate stack is formed on the BOX layer. The fin structures each include a semiconductor layer and extend in a first direction, and the gate stack is formed over the fin structures and extends in a second direction. The gate stack includes dielectric and polysilicon layers. Gate spacers are formed on vertical sidewalls of the gate stack, and an epi layer is deposited over the fin structures. Ions are implanted to form source and drain regions, and the gate spacers are etched so that their upper surface is below an upper surface of the gate stack. After etching the gate spacers, silicidation is performed to fully silicide the polysilicon layer of the gate stack and to form silicide regions in an upper surface of the source and drain regions.

9. 发明授权

US08470678B2 Tensile stress enhancement of nitride film for stressed channel field effect transistor fabrication 失效
标题翻译：用于应力沟道场效应晶体管制造的氮化膜的拉伸应力增强
公开(公告)号：US08470678B2
公开(公告)日：2013-06-25
申请号：US13034045
申请日：2011-02-24
申请人： Ming Cai , Dechao Guo , Chun-chen Yeh , Pranita Kulkarni
发明人： Ming Cai , Dechao Guo , Chun-chen Yeh , Pranita Kulkarni
IPC分类号： H01L21/00
CPC分类号： H01L29/7843 , H01L21/3105 , H01L21/76814 , H01L21/76825 , H01L21/76834
摘要： A method for inducing a tensile stress in a channel of a field effect transistor (FET) includes forming a nitride film over the FET; forming a contact hole to the FET through the nitride film; and performing ultraviolet (UV) curing of the nitride film after forming the contact hole to the FET through the nitride film, wherein the UV cured nitride film induces the tensile stress in the channel of the FET.
摘要翻译：用于在场效应晶体管（FET）的沟道中诱发拉伸应力的方法包括在FET上形成氮化物膜; 通过氮化物膜形成与FET的接触孔; 并且通过氮化物膜在形成接触孔之后对氮化物膜进行紫外（UV）固化，其中，UV固化的氮化物膜在FET的沟道中引起拉伸应力。

10. 发明授权

US08796812B2 Self-aligned trench over fin 有权
标题翻译：自对准沟槽鳍
公开(公告)号：US08796812B2
公开(公告)日：2014-08-05
申请号：US13561142
申请日：2012-07-30
申请人： Chiahsun Tseng , Chun-chen Yeh , Yunpeng Yin , Lei L. Zhuang
发明人： Chiahsun Tseng , Chun-chen Yeh , Yunpeng Yin , Lei L. Zhuang
IPC分类号： H01L29/00
CPC分类号： H01L21/30604 , H01L21/0334 , H01L21/3085 , H01L21/3086 , H01L21/3088
摘要： A stack of a first hard mask portion and a second hard mask portion is formed over a semiconductor material layer by anisotropically etching a stack, from bottom to top, of a first hard mask layer and a second hard mask layer. The first hard mask portion is laterally recessed by an isotropic etch. A dielectric material layer is conformally deposited and planarized. The dielectric material layer is etched employing an anisotropic etch that is selective to the first hard mask portion to form a dielectric material portion that laterally surrounds the first hard mask portion. After removal of the second and first hard mask portions, the semiconductor material layer is etched employing the dielectric material portion as an etch mask. Optionally, portions of the semiconductor material layer underneath the first and second hard mask portions can be undercut at a periphery.
摘要翻译：通过从第一硬掩模层和第二硬掩模层的从底部到顶部的各向异性地蚀刻叠层，在半导体材料层上形成第一硬掩模部分和第二硬掩模部分的堆叠。通过各向同性蚀刻，第一硬掩模部分被横向凹进。电介质材料层被共形沉积并平坦化。使用对第一硬掩模部分选择性的各向异性蚀刻蚀刻电介质材料层，以形成侧向围绕第一硬掩模部分的电介质材料部分。在去除第二和第一硬掩模部分之后，使用介电材料部分作为蚀刻掩模蚀刻半导体材料层。可选地，第一和第二硬掩模部分下面的半导体材料层的一部分可以在周边被切削。

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