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1. 发明授权

US08860107B2 FinFET-compatible metal-insulator-metal capacitor 有权
标题翻译： FinFET兼容金属 - 绝缘体 - 金属电容器
公开(公告)号：US08860107B2
公开(公告)日：2014-10-14
申请号：US12793292
申请日：2010-06-03
申请人： Wilfried E. Haensch , Pranita Kulkarni , Tenko Yamashita
发明人： Wilfried E. Haensch , Pranita Kulkarni , Tenko Yamashita
IPC分类号： H01L27/108 , H01L21/8234 , H01L27/08 , H01L27/06
CPC分类号： H01L21/823431 , H01L27/0629 , H01L27/0805
摘要： At least one semiconductor fin for a capacitor is formed concurrently with other semiconductor fins for field effect transistors. A lower conductive layer is deposited and lithographically patterned to form a lower conductive plate located on the at least one semiconductor fin. A dielectric layer and at least one upper conductive layer are formed and lithographically patterned to form a node dielectric and an upper conductive plate over the lower conductive plate as well as a gate dielectric and a gate conductor over the other semiconductor fins. The lower conductive plate, the node dielectric, and the upper conductive plate collectively form a capacitor. The finFETs may be dual gate finFETs or trigate finFETs. A buried insulator layer may be optionally recessed to increase the capacitance. Alternately, the lower conductive plate may be formed on a planar surface of the buried insulator layer.
摘要翻译：用于电容器的至少一个半导体鳍片与用于场效应晶体管的其它半导体鳍片同时形成。沉积下导电层并以光刻方式图案化以形成位于至少一个半导体鳍片上的下导电板。形成电介质层和至少一个上导电层，并将其光刻图案化以在下导电板上形成节点电介质和上导电板，以及在其它半导体鳍片上的栅极电介质和栅极导体。下导电板，节点电介质和上导电板共同形成电容器。 finFET可以是双栅极finFET或者触发的finFET。埋入的绝缘体层可以任选地凹入以增加电容。或者，下导电板可以形成在掩埋绝缘体层的平坦表面上。

2. 发明授权

US08492794B2 Vertical polysilicon-germanium heterojunction bipolar transistor 有权
公开(公告)号：US08492794B2
公开(公告)日：2013-07-23
申请号：US13048366
申请日：2011-03-15
申请人： Jin Cai , Kevin K. Chan , Wilfried E. Haensch , Tak H. Ning
发明人： Jin Cai , Kevin K. Chan , Wilfried E. Haensch , Tak H. Ning
IPC分类号： H01L29/66
CPC分类号： H01L29/737 , H01L21/76229 , H01L29/0649 , H01L29/0821 , H01L29/165 , H01L29/66242 , H01L29/7375
摘要： A vertical heterojunction bipolar transistor (HBT) includes doped polysilicon having a doping of a first conductivity type as a wide-gap-emitter with an energy bandgap of about 1.12 eV and doped single crystalline Ge having a doping of the second conductivity type as the base having the energy bandgap of about 0.66 eV. Doped single crystalline Ge having of doping of the first conductivity type is employed as the collector. Because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. Further, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.

3. 发明授权

US08455932B2 Local interconnect structure self-aligned to gate structure 有权
标题翻译：局部互连结构自对准到门结构
公开(公告)号：US08455932B2
公开(公告)日：2013-06-04
申请号：US13102073
申请日：2011-05-06
申请人： Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Wilfried E. Haensch , Balasubramanian S. Haran , Pranita Kulkarni
发明人： Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Wilfried E. Haensch , Balasubramanian S. Haran , Pranita Kulkarni
IPC分类号： H01L21/336
CPC分类号： H01L27/0207 , H01L21/28518 , H01L21/76802 , H01L21/76895 , H01L21/76897 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L27/1104 , H01L29/41783 , H01L29/66545 , H01L29/6659 , H01L29/7834
摘要： A common cut mask is employed to define a gate pattern and a local interconnect pattern so that local interconnect structures and gate structures are formed with zero overlay variation relative to one another. A local interconnect structure may be laterally spaced from a gate structure in a first horizontal direction, and contact another gate structure in a second horizontal direction that is different from the first horizontal direction. Further, a gate structure may be formed to be collinear with a local interconnect structure that adjoins the gate structure. The local interconnect structures and the gate structures are formed by a common damascene processing step so that the top surfaces of the gate structures and the local interconnect structures are coplanar with each other.
摘要翻译：采用公共切割掩模来限定栅极图案和局部互连图案，使得局部互连结构和栅极结构相对于彼此形成为零覆盖变化。局部互连结构可以在第一水平方向上与栅极结构横向间隔开，并且在与第一水平方向不同的第二水平方向上接触另一个栅极结构。此外，栅极结构可以形成为与邻接栅极结构的局部互连结构共线。局部互连结构和栅极结构通过公共镶嵌处理步骤形成，使得栅极结构的顶表面和局部互连结构彼此共面。

4. 发明授权

US08367508B2 Self-aligned contacts for field effect transistor devices 有权
标题翻译：场效应晶体管器件的自对准触点
公开(公告)号：US08367508B2
公开(公告)日：2013-02-05
申请号：US12757201
申请日：2010-04-09
申请人： Dechao Guo , Wilfried E. Haensch , Xinhui Wang , Keith Kwong Hon Wong
发明人： Dechao Guo , Wilfried E. Haensch , Xinhui Wang , Keith Kwong Hon Wong
IPC分类号： H01L21/336
CPC分类号： H01L29/665 , H01L21/28088 , H01L21/28114 , H01L21/28525 , H01L21/76897 , H01L21/78 , H01L29/66545
摘要： A method for forming a field effect transistor includes forming a gate stack, a spacer adjacent to opposing sides of the gate stack, a silicide source region and a silicide drain region on opposing sides of the spacer, epitaxially growing silicon on the source region and the drain region; forming a liner layer on the gate stack and the spacer, removing a portion of the liner layer to expose a portion of the hardmask layer, removing the exposed portions of the hardmask layer to expose a silicon layer of the gate stack, removing exposed silicon to expose a portion of a metal layer of the gate stack, the source region, and the drain region; and depositing a conductive material on the metal layer of the gate stack, the silicide source region, and the silicide drain region.
摘要翻译：一种用于形成场效应晶体管的方法，包括：形成栅极叠层，与栅叠层的相对侧相邻的间隔物，在间隔物的相对侧上的硅化物源区和硅化物漏极区，在源区上外延生长硅，漏区; 在栅极堆叠和间隔物上形成衬垫层，去除衬里层的一部分以露出硬掩模层的一部分，去除硬掩模层的暴露部分以暴露栅堆叠的硅层，将暴露的硅去除暴露栅叠层，源极区和漏区的金属层的一部分; 以及在栅叠层，硅化物源区和硅化物漏极区的金属层上沉积导电材料。

5. 发明申请

US20120181508A1 Graphene Devices and Silicon Field Effect Transistors in 3D Hybrid Integrated Circuits 有权
标题翻译：三维混合集成电路中的石墨烯器件和硅场效应晶体管
公开(公告)号：US20120181508A1
公开(公告)日：2012-07-19
申请号：US13009280
申请日：2011-01-19
申请人： Josephine B. Chang , Wilfried E. Haensch , Fei Liu , Zihong Liu
发明人： Josephine B. Chang , Wilfried E. Haensch , Fei Liu , Zihong Liu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/0688 , H01L21/28506 , H01L21/8221 , H01L29/1606 , H01L29/66045 , H01L29/78 , H01L29/78684
摘要： A three dimensional integrated circuit includes a silicon substrate, a first source region disposed on the substrate, a first drain region disposed on the substrate, a first gate stack portion disposed on the substrate, a first dielectric layer disposed on the first source region, the first drain region, the first gate stack portion, and the substrate, a second dielectric layer formed on the first dielectric layer, a second source region disposed on the second dielectric layer, a second drain region disposed on the second dielectric layer, and a second gate stack portion disposed on the second dielectric layer, the second gate stack portion including a graphene layer.
摘要翻译：三维集成电路包括硅衬底，设置在衬底上的第一源极区域，设置在衬底上的第一漏极区域，设置在衬底上的第一栅极堆叠部分，设置在第一源极区域上的第一电介质层，第一漏极区域，第一栅极堆叠部分和衬底，形成在第一电介质层上的第二电介质层，设置在第二电介质层上的第二源极区域，设置在第二电介质层上的第二漏极区域，以及第二漏极区域栅极堆叠部分设置在第二介电层上，第二栅极堆叠部分包括石墨烯层。

6. 发明申请

US20120175749A1 Structure and Method to Fabricate Resistor on FinFET Processes 有权
标题翻译：在FinFET工艺上制造电阻的结构和方法
公开(公告)号：US20120175749A1
公开(公告)日：2012-07-12
申请号：US12985669
申请日：2011-01-06
申请人： Wilfried E. Haensch , Pranita Kulkarni , Tenko Yamashita
发明人： Wilfried E. Haensch , Pranita Kulkarni , Tenko Yamashita
IPC分类号： H01L29/06 , H01L21/22
CPC分类号： H01L21/845 , H01L27/1211
摘要： A structure comprises first and at least second fin structures are formed. Each of the first and at least second fin structures has a vertically oriented semiconductor body. The vertically oriented semiconductor body is comprised of vertical surfaces. A doped region in each of the first and at least second fin structures is comprised of a concentration of dopant ions present in the semiconductor body to form a first resistor and at least a second resistor, and a pair of merged fins formed on outer portions of the doped regions of the first and at least second fin structures. The pair of merged fins is electrically connected so that the first and at least second resistors are electrically connected in parallel with each other.
摘要翻译：一种结构包括形成第一和至少第二鳍结构。第一鳍片结构和至少第二鳍片结构中的每一个具有垂直取向的半导体本体。垂直取向的半导体主体由垂直表面组成。第一和至少第二翅片结构中的每一个中的掺杂区域包括存在于半导体主体中的掺杂剂离子的浓度，以形成第一电阻器和至少第二电阻器，以及一对形成在第一和至少第二鳍结构的掺杂区域。这对合并的翅片电连接，使得第一和至少第二电阻器彼此并联电连接。

7. 发明授权

US07838942B2 Substrate solution for back gate controlled SRAM with coexisting logic devices 有权
标题翻译：用于具有共存逻辑器件的背栅控制SRAM的衬底解决方案
公开(公告)号：US07838942B2
公开(公告)日：2010-11-23
申请号：US12144272
申请日：2008-06-23
申请人： Robert H. Dennard , Wilfried E. Haensch , Arvind Kumar , Robert J. Miller
发明人： Robert H. Dennard , Wilfried E. Haensch , Arvind Kumar , Robert J. Miller
IPC分类号： H01L29/76
CPC分类号： H01L27/1108
摘要： A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.
摘要翻译：一种半导体结构，其包括至少一个逻辑器件区域和至少一个静态随机存取存储器（SRAM）器件区域，其中每个器件区域包括双门控场效应晶体管（FET），其中每个FET器件的背栅极掺杂提供了特定的水平，以提高不同器件区域内的FET器件的性能。特别地，SRAM器件区域内的背栅极比逻辑器件区域内的后栅极重掺杂。为了控制短沟道效应，逻辑器件区域内的FET器件包括掺杂沟道，而SRAM器件区域内的FET器件不是。在源极/漏极区域之下具有低净掺杂的非均匀横向掺杂分布和在沟道下方的高净掺杂将为逻辑器件提供附加的SCE控制。

8. 发明授权

US07342406B2 Methods and apparatus for inline variability measurement of integrated circuit components 有权
标题翻译：集成电路元件在线可变性测量方法与装置
公开(公告)号：US07342406B2
公开(公告)日：2008-03-11
申请号：US11297730
申请日：2005-12-08
申请人： Manjul Bhushan , Karen M. G. V. Gettings , Wilfried E. Haensch , Brian L. Ji , Mark B. Ketchen
发明人： Manjul Bhushan , Karen M. G. V. Gettings , Wilfried E. Haensch , Brian L. Ji , Mark B. Ketchen
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , H01L2924/0002 , H01L2924/00
摘要： A method of measuring variability of integrated circuit components is provided. A specified parameter of at least one first array configuration comprising a plurality of the integrated circuit components without specified internal connections between the integrated circuit components is measured. The specified parameter of at least one second array configuration comprising a plurality of the integrated circuit components nominally identical to those of the first array configuration with specified internal connections between the integrated circuit components is also measured. A variation coefficient is determined for the integrated circuit components based on the measured specified parameter of the at least one first array configuration and the at least one second array configuration.
摘要翻译：提供了一种测量集成电路部件的可变性的方法。测量包括集成电路部件之间没有规定内部连接的多个集成电路部件的至少一个第一阵列配置的指定参数。还测量包括与集成电路部件之间具有规定的内部连接的第一阵列配置的名义上相同的多个集成电路部件的至少一个第二阵列配置的指定参数。基于所测量的至少一个第一阵列配置和至少一个第二阵列配置的指定参数，为集成电路组件确定变化系数。

9. 发明申请

US20070287256A1 Contact scheme for FINFET structures with multiple FINs 审中-公开
标题翻译：具有多个FIN的FINFET结构的接触方案
公开(公告)号：US20070287256A1
公开(公告)日：2007-12-13
申请号：US11448702
申请日：2006-06-07
申请人： Leland Chang , Wilfried E. Haensch , Meikei Ieong , Ghavam Shahidi , Huiling Shang
发明人： Leland Chang , Wilfried E. Haensch , Meikei Ieong , Ghavam Shahidi , Huiling Shang
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66628 , H01L29/66795
摘要： A FINFET-containing structure having multiple FINs that are merged together without source/drain contact pads or a local interconnect is provided. In accordance with the present invention, the inventive structure includes a plurality of semiconducting bodies (i.e., FINs) which extend above a surface of a substrate. A common patterned gate stack surrounds the plurality of semiconducting bodies and a nitride-containing spacer is located on sidewalls of the common patterned gate stack. An epitaxial semiconductor layer is used to merge each of the semiconducting bodies together.
摘要翻译：提供了一种具有融合在一起而没有源极/漏极接触焊盘或局部互连的多个FIN的具有FINFET的结构。根据本发明，本发明的结构包括在衬底的表面上方延伸的多个半导电体（即，FIN）。常见的图案化栅极堆叠围绕多个半导体本体，并且含氮化物的间隔物位于公共图案化栅叠层的侧壁上。使用外延半导体层将每个半导电体合并在一起。

10. 发明授权

US06812527B2 Method to control device threshold of SOI MOSFET's 有权
标题翻译：控制SOI MOSFET器件阈值的方法
公开(公告)号：US06812527B2
公开(公告)日：2004-11-02
申请号：US10235147
申请日：2002-09-05
申请人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
发明人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
IPC分类号： H01L2701
CPC分类号： H01L29/66772 , H01L29/458 , H01L29/78621 , H01L29/78648
摘要： A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided in which an implanted back-gate is formed into a Si-containing layer of an SOI wafer. The implanted back-gate thus formed is capable of controlling the threshold voltage of a polysilicon-containing front-gate which is formed over a portion of the implanted back-gate region. The implanted back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.
摘要翻译：提供了一种形成绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）器件的方法，其中注入的背栅极形成为SOI晶片的含Si层。如此形成的注入后栅极能够控制在植入的背栅区域的一部分上形成的含多晶硅的前栅的阈值电压。在SOI MOSFET器件中，植入式背栅可用作动态阈值电压控制系统，因为它适用于电路/系统有效期间和电路/系统空闲期间。

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