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    • 7. 发明授权
    • Multiple copper vias for integrated circuit metallization
    • 用于集成电路金属化的多个铜通孔
    • US07078817B2
    • 2006-07-18
    • US11010596
    • 2004-12-13
    • Paul S. HoKi-Don LeeEnnis OgawaHideki Matsuhashi
    • Paul S. HoKi-Don LeeEnnis OgawaHideki Matsuhashi
    • H01L23/48H01L23/52H01L29/40
    • H01L22/34H01L23/522H01L23/5226H01L23/53228H01L2924/0002H01L2924/00
    • Electromigration can be reduced in a copper-based metallization of an integrated circuit that includes a first copper-containing via that electrically connects an underlying conductive line and an overlying copper-containing line through an intervening insulating layer. Electromigration can be reduced by forming at least a second copper-containing via that electrically connects the underlying conductive line and the overlying copper-containing line through the intervening insulating layer, in parallel with the first copper-containing via. Multi-vias can provide redundancy to reduce early failure statistics. Moreover, since current is distributed among the vias, the electromigration driving force can be reduced and local Joule heating, in voids at the via interface, also may be reduced. Accordingly, even if via voids are formed, the structure may not fail by catastrophic thermal runaway due to Joule heating.
    • 可以减少集成电路的铜基金属化中的电迁移,该集成电路包括通过中间绝缘层将下面的导电线与覆盖的含铜线电连接的第一含铜通孔。 通过形成至少第二含铜通孔,通过与第一含铜通孔平行地电连接下面的导电线路和覆盖的含铜线路穿过中间绝缘层,可以减少电迁移。 多通道可以提供冗余以减少早期故障统计。 此外,由于电流分布在通孔中,所以可以减少电迁移驱动力,并且可以减少在通孔接口处的空隙中的局部焦耳加热。 因此,即使形成通孔,由于焦耳加热,结构也可能不会由于灾难性热失控而失效。
    • 9. 发明申请
    • SELF-ALIGNED MASKS AND METHODS OF USE
    • 自对准掩模和使用方法
    • US20150054135A1
    • 2015-02-26
    • US14466059
    • 2014-08-22
    • Paul S. HoZhuojie Wu
    • Paul S. HoZhuojie Wu
    • H01L21/3065H01L21/308H01L21/027
    • B81C1/00H01L21/0337H01L21/3086H01L21/31116H01L21/31122
    • The disclosure relates to a method for forming a nanoscale structure by forming a pattern on a selectively etched layer located on top of a substrate using lithography, wherein the pattern results a gap having sidewalls, performing RIE on the gap having sidewalls, wherein RIE results in the formation of a self-aligned mask on the bottom wall of the gap with unprotected regions on the bottom wall of the gap near the junctions with the sidewalls, and wet etching the gap having a self-aligned mask and unprotected regions to remove the substrate under the unprotected regions to form a nanoscale structure in the substrate.The disclosure also relates to a nanoscale structure array including a plurality of nanotrenches, nanochannels or nanofins having a width of 50 nm or less and an average variation in width of 5% or less along the entire length of each nanotrench, nanochannel or nanofin.
    • 本公开涉及一种用于通过使用光刻在位于衬底顶部的选择性蚀刻层上形成图案形成纳米尺度结构的方法,其中所述图案形成具有侧壁的间隙,在具有侧壁的间隙上执行RIE,其中RIE导致 在与侧壁接合的间隙的底壁上的未保护区域的间隙的底壁上形成自对准掩模,并且湿蚀刻具有自对准掩模和未保护区域的间隙以去除衬底 在未保护的区域下,在衬底中形成纳米尺度结构。 本公开还涉及纳米尺度结构阵列,其包括沿着每个纳米管,纳米通道或纳米芬的整个长度的宽度为50nm或更小的宽度为5%或更小的多个纳米管,纳米通道或纳米线。