会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 9. 发明授权
    • Programmable logic array apparatus
    • 可编程逻辑阵列设备
    • US5021690A
    • 1991-06-04
    • US434797
    • 1989-11-13
    • Alfredo R. Linz
    • Alfredo R. Linz
    • H03K19/177
    • H03K19/17716
    • An apparatus adaptable for use as a programmable logic array as disclosed for receiving control signals from a signal source and producing resultant output signals logically related to the control signals according to a program which is comprised of a plurality of program instructions, each of which is identified by an address. The apparatus includes a clock for generating a plurality of clock signals and first and second iteration processing circuits for effecting iteration operations upon the input signals and producing resultant output signals on a plurality of output lines. The apparatus further includes a plurality of minterm lines common to the first and second iteration processing circuits. The first iteration processing circuit includes a plurality of first switching devices connected in series within selected of the minterm lines and gated by the input signals. The program is executed within the first iteration processing circuit by selectively gating appropriate of the switching devices to define a continuous path for discharging selected of the minterm lines. Placement of the first switching devices within the first iteration processing circuit is defined by the program. Selection of the minterm lines for participation in a respective program instruction is determined according to the address of the particular program instruction, which address is stored in a cyclic memory device. The apparatus is arranged in a plurality of blocks, each of which blocks implements a predetermined group of program instructions in a pipeline manner.