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1. 发明授权

US07283078B2 Digital-to-analog converter 有权
标题翻译：数模转换器
公开(公告)号：US07283078B2
公开(公告)日：2007-10-16
申请号：US11446829
申请日：2006-06-05
申请人： Frédéric Poulet , Guillaume Cogniard
发明人： Frédéric Poulet , Guillaume Cogniard
IPC分类号： H03M1/82
CPC分类号： H03M3/358 , H03M3/506 , H03M7/3024 , H03M7/3035 , H03M7/3037
摘要： A converter of a digital signal into a pulse-width modulated signal, comprising a first conversion unit receiving, at a first frequency, successive digital signals each having one of a first determined number of values, and providing first intermediary signals, at the first frequency, each having one of a second determined number of values smaller than the first determined number; a unit performing a decimation of the first intermediary signals to provide second intermediary signals at a second frequency equal to the first frequency divided by the second determined number minus one; and a second conversion unit providing at the second frequency, from the second intermediary signals, a two-state pulse-width modulated signal having a minimum duration in one of the two states which is equal to the inverse of the first frequency, the first conversion unit receiving the pulse-width modulated signal.
摘要翻译：将数字信号的转换器转换成脉冲宽度调制信号，包括第一转换单元，以第一频率接收每个具有第一确定数目的值之一的连续数字信号，并以第一频率提供第一中间信号，每个具有小于所述第一确定数量的第二确定数量的值中的一个; 执行对第一中间信号的抽取以使第二中间信号以等于第二确定数减去一的第一频率的第二频率的单元执行; 以及第二转换单元，从第二中间信号以第二频率提供具有等于第一频率的倒数的两个状态中的一个中的最小持续时间的两状态脉宽调制信号，第一转换接收脉冲宽度调制信号的单元。

2. 发明授权

US07253758B2 Third order sigma-delta modulator 有权
公开(公告)号：US07253758B2
公开(公告)日：2007-08-07
申请号：US11185287
申请日：2005-07-20
申请人： Long-Xi Chang , Chia-Chun Hung
发明人： Long-Xi Chang , Chia-Chun Hung
IPC分类号： H03M3/00
CPC分类号： H03M3/448 , H03M3/424 , H03M3/454 , H03M7/3026 , H03M7/3035
摘要： A third order sigma-delta modulator comprises a first summing unit for receiving an input signal, a first integrator network connected to an output of the first summing unit, a second integrator network for receiving an output of the first integrator network, a second summing unit connected to an output of the second integrator network, a third integrator network connected to an output of the second summing unit, and a feed-forward path from the output of the first integrator network to an input of the second summing unit.

3. 发明申请

US20070035425A1 HIGH SPEED DIGITAL DELTA-SIGMA MODULATOR WITH INTEGRATED UPSAMPLER 有权
标题翻译：高速数字三角形调制器与集成UPSAMPLER
公开(公告)号：US20070035425A1
公开(公告)日：2007-02-15
申请号：US11202307
申请日：2005-08-10
申请人： Jeffrey Hinrichs , Harry Harberts
发明人： Jeffrey Hinrichs , Harry Harberts
IPC分类号： H03M3/00
CPC分类号： H03H17/0657 , H03M3/508 , H03M7/3017 , H03M7/3035 , H03M7/304
摘要： Apparatus, and a related method, for converting digital signals directly to radio-frequency (RF) analog signals. The apparatus includes a single high-speed delta-sigma modulator and an integrated upsampler that increases the data rate of digital input samples by a selected factor, such as nine times. The delta-sigma modulator is configured to include a feedback multiplier coefficients that are selected to greatly facilitate operation of associated adders. At least one critical adder includes a carry-select adder modification that further speeds up the add operation and ensures that the apparatus operates at desirably high frequencies.
摘要翻译：用于将数字信号直接转换成射频（RF）模拟信号的装置和相关方法。该装置包括单个高速Δ-Σ调制器和集成上采样器，其通过选择的因子（例如九次）来增加数字输入样本的数据速率。 Δ-Σ调制器被配置为包括被选择以极大地促进相关加法器的操作的反馈乘法器系数。至少一个关键加法器包括进位选择加法器修改，进一步加速加法运算，并确保装置以期望的高频工作。

4. 发明申请

US20020041243A1 Noise shaper 有权
标题翻译：噪音整形器
公开(公告)号：US20020041243A1
公开(公告)日：2002-04-11
申请号：US09929171
申请日：2001-08-14
发明人： Yukio Fukuhara , Akira Toyama
IPC分类号： H03M001/20
CPC分类号： H03M3/328 , H03M3/43 , H03M3/448 , H03M3/454 , H03M7/3008 , H03M7/3028 , H03M7/3035 , H03M7/304
摘要： A pole-shifted noise shaper whose transfer function has a Z-plane in which the pole has been shifted out of the origin. The noise shaper suppresses idle pattern. The noise shaper has a dither adder (17) placed immediately before a quantizer (16) to add a dither signal to data about to be applied to the quantizer (16). This suppresses attenuation of the dither signal due to noise shaping. Therefore, the dither signal can be supplied effectively. The idle pattern appearing in the output signal can be suppressed. Since the pattern of the dither signal is varied at a frequency that is {fraction (1/16)} to null of the frequency of the operating clock signal, the frequency of noise component due to the dither signal lowers. The signal and the dither signal component can be easily separated in a rear stage.
摘要翻译：一个极移噪声整形器，其传输函数具有一个Z平面，其中极点已经移出原点。噪音整形器抑制空闲模式。噪声整形器具有放置在量化器（16）之前的抖动加法器（17），以将抖动信号添加到要被施加到量化器（16）的数据。这抑制了由于噪声整形引起的抖动信号的衰减。因此，可以有效地提供抖动信号。可以抑制出现在输出信号中的空闲模式。由于抖动信号的模式以操作时钟信号的频率为{分数（1/16）}至⅛的频率变化，所以由抖动信号引起的噪声分量的频率降低。信号和抖动信号分量可以容易地在后级分离。

5. 发明授权

US07630504B2 Microphone comprising integral multi-level quantizer and single-bit conversion means 有权
标题翻译：麦克风包括整体多电平量化器和单位转换装置
公开(公告)号：US07630504B2
公开(公告)日：2009-12-08
申请号：US10580505
申请日：2004-10-08
申请人： Jens Kristian Poulsen
发明人： Jens Kristian Poulsen
IPC分类号： H04R3/00
CPC分类号： H04R3/00 , H03M7/3015 , H03M7/3035 , H04R1/04 , H04R25/505
摘要： The invention relates to a digital microphone comprising an integral analog-to-digital converter based on a multi-level quantizer in cascade with a digital signal converter which is adapted to provide a single-bit output signal. Digital microphones in accordance with the invention are particularly well adapted for use in mobile terminals and compact portable communication equipment such as mobile or cellular phones, headsets, hearing prostheses etc.
摘要翻译：本发明涉及一种数字麦克风，其包括基于与数字信号转换器级联的多电平量化器的集成模数转换器，该数字信号转换器适于提供单位输出信号。根据本发明的数字麦克风特别适用于移动终端和小型便携式通信设备，例如移动或蜂窝电话，耳机，听觉假肢等。

6. 发明申请

US20090238379A1 APPARATUS AND METHOD FOR MINIMIZING QUANTIZATION NOISE AS MUTING 审中-公开
标题翻译：最小化量化噪声的装置和方法
公开(公告)号：US20090238379A1
公开(公告)日：2009-09-24
申请号：US12144464
申请日：2008-06-23
申请人： Lo-Tien FENG
发明人： Lo-Tien FENG
IPC分类号： H04B15/00
CPC分类号： H03M7/3006 , H03M7/3028 , H03M7/3035 , H03M7/304
摘要： An apparatus and method for minimizing the quantization noise as muting are provided, and particularly applied to a Delta-Sigma modulator that is used to process digital-to-analog conversion. By means of a zero-sampling detection circuit and a dynamic gain mechanism, a dynamic gain is introduced to minimize the quantization noise occurred as muting. The method preferably includes a first step for receiving the signals by the Delta-Sigma modulator inputted from an audio decoder, and a next step for detecting signal zero by a zero-sampling detection unit and counting the number of the signals with signal zero. The mute state is entered when the number of signal zeros reaches a pre-set number. At the moment, the signaling route is switched to another route with dynamic gain mechanism. Further, the dynamic gain mechanism is activated for producing a dynamic gain, which will be fed back to the input end of the modulator.
摘要翻译：提供了一种用于将量化噪声最小化为静音的装置和方法，特别适用于用于处理数模转换的Δ-Σ调制器。通过零采样检测电路和动态增益机制，引入动态增益以最小化作为静音发生的量化噪声。该方法优选地包括用于通过从音频解码器输入的Δ-Σ调制器接收信号的第一步骤，以及用于通过零采样检测单元检测信号零并且用信号零计数信号数的下一步骤。当信号零数达到预设值时，输入静音状态。目前，信令路由被切换到具有动态增益机制的另一路由。此外，动态增益机制被激活以产生将被反馈到调制器的输入端的动态增益。

7. 发明申请

US20080165042A1 Extended range delta-sigma modulator and delta-sigma power converter 有权
公开(公告)号：US20080165042A1
公开(公告)日：2008-07-10
申请号：US11651857
申请日：2007-01-10
申请人： James R. Hochschild
发明人： James R. Hochschild
IPC分类号： H03M3/02
CPC分类号： H03M3/362 , H03M3/448 , H03M3/45 , H03M3/454 , H03M7/3011 , H03M7/3033 , H03M7/3035 , H03M7/304
摘要： Devices, systems, and methods for providing delta-sigma modulation in conjunction with analog-to-digital or digital-to-analog signal conversion are disclosed. The delta-sigma modulator and delta-sigma converter include dynamically-scalable coefficients, which, at relatively low signal amplitudes, allow the delta-sigma modulator and delta-sigma converter to modulate the signals using a first noise transfer function and, at relatively greater signal amplitudes, allow the delta-sigma modulator and delta-sigma converter to modulate the signals using a second noise transfer function.

8. 发明授权

US07183956B1 High speed digital delta-sigma modulator with integrated upsampler 有权
标题翻译：具有集成上采样器的高速数字delta-sigma调制器
公开(公告)号：US07183956B1
公开(公告)日：2007-02-27
申请号：US11202307
申请日：2005-08-10
申请人： Jeffrey M. Hinrichs , Harry S. Harberts
发明人： Jeffrey M. Hinrichs , Harry S. Harberts
IPC分类号： H03M3/02
CPC分类号： H03H17/0657 , H03M3/508 , H03M7/3017 , H03M7/3035 , H03M7/304
摘要： Apparatus, and a related method, for converting digital signals directly to radio-frequency (RF) analog signals. The apparatus includes a single high-speed delta-sigma modulator and an integrated upsampler that increases the data rate of digital input samples by a selected factor, such as nine times. The delta-sigma modulator is configured to include a feedback multiplier coefficients that are selected to greatly facilitate operation of associated adders. At least one critical adder includes a carry-select adder modification that further speeds up the add operation and ensures that the apparatus operates at desirably high frequencies.
摘要翻译：用于将数字信号直接转换成射频（RF）模拟信号的装置和相关方法。该装置包括单个高速Δ-Σ调制器和集成上采样器，其通过选择的因子（例如九次）来增加数字输入样本的数据速率。 Δ-Σ调制器被配置为包括被选择以极大地促进相关加法器的操作的反馈乘法器系数。至少一个关键加法器包括进位选择加法器修改，进一步加速加法运算，并确保装置以期望的高频工作。

9. 发明授权

US06992606B2 Method and circuit for multi-standard sigma-delta modulator 有权
标题翻译：多标准Σ-Δ调制器的方法和电路
公开(公告)号：US06992606B2
公开(公告)日：2006-01-31
申请号：US10865275
申请日：2004-06-10
申请人： Thomas Nicholas Zogakis , Himamshu G. Khasnis , Baireddy Vijayavardhan
发明人： Thomas Nicholas Zogakis , Himamshu G. Khasnis , Baireddy Vijayavardhan
IPC分类号： H03M1/20 , H03M3/00
CPC分类号： H03M7/3008 , H03M7/3011 , H03M7/3028 , H03M7/3035 , H03M7/304
摘要： System and method for a multi-standard sigma-delta modulator. A preferred embodiment comprises an integrator coupled to a signal input, wherein the integrator is configured to sum a difference between an input signal and an output of the sigma-delta modulator. A dithering circuit, also coupled to the signal input, is used to produce a dithering sequence. A summing point combines an output of the integrator and the dithering circuit while a quantizer converts the combined outputs into one of several discrete levels. The sigma-delta modulator further comprises a reset circuit to reset the sigma-delta modulator if the integrator becomes saturated. The sigma-delta modulator, as described, is compatible with G.Lite, ADSL, and ADSL+ variants of the digital subscriber line technical standards.
摘要翻译：用于多标准Σ-Δ调制器的系统和方法。优选实施例包括耦合到信号输入的积分器，其中积分器被配置为对输入信号和Σ-Δ调制器的输出之间的差进行求和。也耦合到信号输入端的抖动电路用于产生抖动序列。求和点将积分器和抖动电路的输出相结合，而量化器将组合的输出转换成几个离散电平之一。 Σ-Δ调制器还包括复位电路，以便在积分器变饱和时复位Σ-Δ调制器。所描述的Σ-Δ调制器与数字用户线技术标准的G.Lite，ADSL和ADSL +变体兼容。

10. 发明授权

US07358881B2 Quantizer overload prevention for feed-back type delta-sigma modulators 有权
标题翻译：反馈型delta-sigma调制器的量化器过载预防
公开(公告)号：US07358881B2
公开(公告)日：2008-04-15
申请号：US11187415
申请日：2005-07-22
申请人： John L. Melanson
发明人： John L. Melanson
IPC分类号： H03M1/66
CPC分类号： H03M7/3035 , H03M7/3026 , H03M7/3028 , H03M7/304
摘要： A digital signal processing system includes a delta sigma modulator that maintains a low pass output during quantizer overload prevention conditions. In at least one embodiment, the delta sigma modulator includes a quantizer overload protected delta sigma modulator with an N-order feedback-type loop filter. A quantizer of the delta sigma modulator provides feedback to at least the first two filter stages of the loop filter. The loop filter includes at least N successive filter stages and limits an output of an initial filter stage during quantizer overload prevention conditions. If limiting the output of the initial filter stage is insufficient to prevent quantizer overload, the delta sigma modulator can progressively limit an output of at least the next successive filter stage to prevent quantizer overload, where N is a positive integer greater than or equal to two (2).
摘要翻译：数字信号处理系统包括在量化器过载预防条件下维持低通输出的Δ-Σ调制器。在至少一个实施例中，Δ-Σ调制器包括具有N阶反馈型环路滤波器的量化器过载保护的Δ-Σ调制器。 ΔΣ调制器的量化器向环路滤波器的至少前两个滤波器级提供反馈。环路滤波器包括至少N个连续的滤波器级，并且在量化器过载预防条件期间限制初始滤波器级的输出。如果限制初始滤波器级的输出不足以防止量化器过载，则ΔΣ调制器可以逐渐限制至少下一个连续滤波器级的输出，以防止量化器过载，其中N是大于或等于二的正整数（2）。

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