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1. 发明申请

US20060057046A1 Pressure-balanced, catalyzed soot filter 有权
标题翻译：压力平衡，催化烟灰过滤器
公开(公告)号：US20060057046A1
公开(公告)日：2006-03-16
申请号：US11218840
申请日：2005-09-02
申请人： Alfred Punke , Torsten Mueller , Michel Deeba , Kenneth Voss , John Steger , Yiu Lui
发明人： Alfred Punke , Torsten Mueller , Michel Deeba , Kenneth Voss , John Steger , Yiu Lui
IPC分类号： B01D47/00
CPC分类号： F01N3/0222 , B01D53/944 , B01D2255/1021 , B01D2255/2066 , B01D2255/407 , B01D2255/9022 , B01D2255/9155 , B01J23/40 , B01J23/42 , B01J23/63 , B01J29/068 , B01J35/0006 , B01J35/04 , B01J37/0248 , F01N3/035 , F01N2510/06
摘要： The invention provides a catalyzed soot filter formed on a wall flow substrate having internal walls coated with catalyst compositions. The soot filter maintains a homogeneous flow of the exhaust gases through the internal walls of the substrate along the length of the filter due to the coating design. Both the efficiency and the durability of the catalytic function are increased over conventionally designed catalyzed soot filters. The catalyzed soot filter provides an integrated function for simultaneously treating the gaseous components of the exhaust (e.g., CO and HC) and the particulate matter deposited in the filter.
摘要翻译：本发明提供一种形成在具有涂覆有催化剂组合物的内壁的壁流动基底上的催化烟灰过滤器。由于涂层设计，烟灰过滤器通过过滤器的长度保持排气的均匀流动通过衬底的内壁。催化功能的效率和耐久性都比常规设计的催化烟灰过滤器增加。催化烟灰过滤器提供了用于同时处理排气（例如CO和HC）的气体组分和沉积在过滤器中的颗粒物质的综合功能。

2. 发明申请

US20110044346A1 Network Bridge and a Method of Operating Thereof 有权
标题翻译：网桥及其操作方法
公开(公告)号：US20110044346A1
公开(公告)日：2011-02-24
申请号：US12527695
申请日：2007-02-28
申请人： Torsten Mueller , Herbert Leuwer , Thorsten Kaiser , Thomas Alberty
发明人： Torsten Mueller , Herbert Leuwer , Thorsten Kaiser , Thomas Alberty
IPC分类号： H04L12/56
CPC分类号： H04L12/4625 , H04L1/0003 , H04L45/123 , H04L45/48 , H04L2001/0092 , H04W40/12 , H04W40/248 , H04W92/02
摘要： A network bridge comprising two ports for connection to two networks, a spanning tree controller and a wireless bridge link controller for each port. The ports employ an adaptive modulation technique. The wireless bridge link controller is connected to the port to exchange physical layer information with said port. When the port detects a change of its PHY mode, it sets the path cost of the link to a value configured for the new PHY mode and forces the bridge to recalculate its spanning tree. The wireless bridge link controller is also connected to the spanning tree controller. If the bridge detects that it has not received BPDUs for a certain time period and the timer will expire soon, the bridge forces the port, via the wireless bridge link controller, to use a more robust PHY mode.
摘要翻译：包括用于连接到两个网络的两个端口的网桥，每个端口的生成树控制器和无线桥接链路控制器。端口采用自适应调制技术。无线桥接链路控制器连接到端口，与所述端口交换物理层信息。当端口检测到其PHY模式的变化时，它将链路的路径开销设置为为新的PHY模式配置的值，并强制桥重新计算其生成树。无线桥接链路控制器也连接到生成树控制器。如果桥接器检测到它在一段时间内没有接收到BPDU，并且定时器将很快到期，桥接器将通过无线桥接链路控制器强制端口使用更强大的PHY模式。

3. 发明申请

US20070001305A1 Method for forming a semiconductor product and semiconductor product 失效
标题翻译：用于形成半导体产品和半导体产品的方法
公开(公告)号：US20070001305A1
公开(公告)日：2007-01-04
申请号：US11172366
申请日：2005-06-30
申请人： Thomas Mikolajick , Torsten Mueller , Nicolas Nagel , Lars Bach , Dominik Olligs , Veronika Polei
发明人： Thomas Mikolajick , Torsten Mueller , Nicolas Nagel , Lars Bach , Dominik Olligs , Veronika Polei
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76838 , H01L27/115 , H01L27/11568
摘要： A semiconductor product includes, a substrate with a first dielectric layer having contact hole fillings for contacting active areas in the substrate. A second dielectric layer with contact holes is provided therein. The contact holes have a width in a first lateral direction. The product further includes conductive lines, each conductive line passing over contact holes in the second dielectric layer and contacting a plurality of contact hole fillings in the first dielectric layer. The conductive lines have a width, in the first lateral direction, that is smaller than the width of the contact holes of the second dielectric layer. The conductive lines are in direct mechanical contact with the contact hole fillings and thereby remove the need to provide any conventional “contact to interconnect” structures.
摘要翻译：半导体产品包括具有第一电介质层的衬底，该第一电介质层具有用于接触衬底中的有源区的接触孔填充物。在其中设置有具有接触孔的第二介质层。接触孔在第一横向具有宽度。该产品还包括导线，每个导线穿过第二介电层中的接触孔，并接触第一介电层中的多个接触孔填充物。导电线在第一横向方向上的宽度小于第二介电层的接触孔的宽度。导线与接触孔填充物直接机械接触，从而消除了提供任何传统的“接触互连”结构的需要。

4. 发明申请

US20060056137A1 Modules for a measuring devcie and measuring device 有权
标题翻译：用于测量设备和测量设备的模块
公开(公告)号：US20060056137A1
公开(公告)日：2006-03-16
申请号：US10534610
申请日：2003-12-05
申请人： Torsten Mueller , Birgit Seitz , Reiner Hausdorf , Rudolf Reckziegel
发明人： Torsten Mueller , Birgit Seitz , Reiner Hausdorf , Rudolf Reckziegel
IPC分类号： H02B1/00
CPC分类号： H05K7/1425 , H05K7/1424 , H05K7/1435 , H05K7/1461 , H05K9/0062
摘要： The invention relates to a module for a measuring device and to a measuring device. The inventive module for a measuring device is provided with a plug-in contact element for the electrical contact of the plug-and-socket plate of the measuring device which is used for data transfer. Said module for the measuring device comprises a main circuit card arranged in the first circuit card space. Said first circuit card space is formed by at least one first element of the body which encompasses the circuit card in a closed manner on the level of the external periphery thereof.
摘要翻译：本发明涉及一种用于测量装置和测量装置的模块。用于测量装置的本发明的模块设置有用于数据传输的测量装置的插头和插座板的电接触的插入式接触元件。所述测量装置的模块包括布置在第一电路卡空间中的主电路卡。所述第一电路卡空间由主体的至少一个第一元件形成，该第一元件围绕电路卡封闭地在其外周边的水平面上。

5. 发明授权

US5948328A Shaping of microparticles in electric-field cages 失效
标题翻译：电场笼中微粒的形成
公开(公告)号：US5948328A
公开(公告)日：1999-09-07
申请号：US700395
申请日：1996-08-23
申请人： Stefan Fiedler , Andreas Voigt , Thomas Schnelle , Guenter Fuhr , Torsten Mueller , Rolf Hagedorn , Jan Hornung , Henning Glasser , Bernd Wagner
发明人： Stefan Fiedler , Andreas Voigt , Thomas Schnelle , Guenter Fuhr , Torsten Mueller , Rolf Hagedorn , Jan Hornung , Henning Glasser , Bernd Wagner
IPC分类号： B01J2/00 , B01J13/02 , B01J19/08
CPC分类号： B01J13/02 , B01J19/087 , B01J2/00
摘要： In the method proposed, microparticles suspended in a liquid or droplets suspended in a liquid with which they are immiscible are shaped by high-frequency electric fields in a three-dimensional electrode array of a size in the micrometer or submicrometer range and subsequently consolidated by prior art chemical bonding procedures or by physical methods. The disposition, geometry and control of the electrodes determine the shape of the particles. The particles themselves must have a conductivity and/or relative dielectric constant lower than the solution surrounding them. For some, this can be achieved only at certain frequencies in the kHz and MHz band which are determined by the passive electrical properties of the particles and the surrounding solution. The particles or droplets are repelled by the electrodes so that they are shaped in the free solution without making contact with any surface and can then be consolidated. This makes it possible to shape micrometer and submicrometer size particles of the kind required in chromatography, affinity biochemistry and medicine, as well as for filter systems.
摘要翻译： PCT No.PCT / DE95 / 00237 Sec。 371日期：1996年8月23日 102（e）日期1996年8月23日PCT提交1995年2月23日PCT公布。 WO95 / 23020 PCT公开号日期1995年8月31日在所提出的方法中，悬浮在液体中的微粒悬浮在与其不混溶的液体中的微滴通过在微米或亚微米范围内的尺寸的三维电极阵列中的高频电场并随后通过现有技术的化学键合方法或通过物理方法进行固结。电极的布置，几何形状和控制决定了颗粒的形状。颗粒本身必须具有低于围绕它们的溶液的导电性和/或相对介电常数。对于一些，这只能在通过颗粒和周围溶液的被动电特性确定的kHz和MHz频带的某些频率下实现。颗粒或液滴被电极排斥，使得它们在游离溶液中成形，而不与任何表面接触，然后可以被固结。这使得可以形成色谱，亲和力生物化学和药物所需类型的微米和亚微米尺寸的颗粒，以及过滤系统。

6. 发明授权

US07368350B2 Memory cell arrays and methods for producing memory cell arrays 有权
标题翻译：用于产生存储单元阵列的存储单元阵列和方法
公开(公告)号：US07368350B2
公开(公告)日：2008-05-06
申请号：US11313247
申请日：2005-12-20
申请人： Dominik Olligs , Torsten Mueller , Karl-Heinz Kuesters , Veronika Polei , Thomas Mikolajick , Josef Willer
发明人： Dominik Olligs , Torsten Mueller , Karl-Heinz Kuesters , Veronika Polei , Thomas Mikolajick , Josef Willer
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L21/76831 , H01L21/76888 , H01L21/76897 , H01L27/11568
摘要： A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a charge-trapping layer and a conductive layer deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed into which a contact fill material is deposited. A further conductive layer is deposited on the surface of the semiconductor wafer and is patterned so as to form word lines. The contact fill material is connected to a contact plug using the contact holes with the contact fill material as a landing pad.
摘要翻译：公开了一种用于制造堆叠的非易失性存储单元和非易失性存储单元阵列的方法。提供半导体晶片，其具有沉积在半导体晶片的表面上的电荷捕获层和导电层。在导电层的顶部使用掩模层，形成接触填充材料沉积到其中的接触孔。另外的导电层沉积在半导体晶片的表面上并被图案化以形成字线。接触填充材料使用接触孔与接触填充材料作为着陆垫连接到接触塞。

7. 发明申请

US20070141799A1 Memory cell arrays and methods for producing memory cell arrays 有权
标题翻译：用于产生存储单元阵列的存储单元阵列和方法
公开(公告)号：US20070141799A1
公开(公告)日：2007-06-21
申请号：US11313247
申请日：2005-12-20
申请人： Dominik Olligs , Torsten Mueller , Karl-Heinz Kuesters , Veronika Polei , Thomas Mikolajick , Josef Willer
发明人： Dominik Olligs , Torsten Mueller , Karl-Heinz Kuesters , Veronika Polei , Thomas Mikolajick , Josef Willer
IPC分类号： H01L21/20
CPC分类号： H01L27/115 , H01L21/76831 , H01L21/76888 , H01L21/76897 , H01L27/11568
摘要： A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a charge-trapping layer and a conductive layer deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed into which a contact fill material is deposited. A further conductive layer is deposited on the surface of the semiconductor wafer and is patterned so as to form word lines. The contact fill material is connected to a contact plug using the contact holes with the contact fill material as a landing pad.
摘要翻译：公开了一种用于制造堆叠的非易失性存储单元和非易失性存储单元阵列的方法。提供半导体晶片，其具有沉积在半导体晶片的表面上的电荷捕获层和导电层。在导电层的顶部使用掩模层，形成接触填充材料沉积到其中的接触孔。另外的导电层沉积在半导体晶片的表面上并被图案化以形成字线。接触填充材料使用接触孔与接触填充材料作为着陆垫连接到接触塞。

8. 发明申请

US20070109754A1 MODULES FOR A MEASURING DEVICE AND MEASURING DEVICE 有权
公开(公告)号：US20070109754A1
公开(公告)日：2007-05-17
申请号：US11621490
申请日：2007-01-09
申请人： Torsten Mueller , Birgit Seitz , Reiner Hausdorf , Rudolf Reckziegel
发明人： Torsten Mueller , Birgit Seitz , Reiner Hausdorf , Rudolf Reckziegel
IPC分类号： H05K7/00
CPC分类号： H05K7/1425 , H05K7/1424 , H05K7/1435 , H05K7/1461 , H05K9/0062
摘要： The invention relates to a module for a measuring device and to a measuring device. The inventive module for a measuring device is provided with a plug-in contact element for the electrical contact of the plug-and-socket plate of the measuring device which is used for data transfer. Said module for the measuring device comprises a main circuit card arranged in the first circuit card space. Said first circuit card space is formed by at least one first element of the body which encompasses the circuit card in a closed manner on the level of the external periphery thereof.

9. 发明申请

US20070075381A1 Semiconductor memory device and method of production 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20070075381A1
公开(公告)日：2007-04-05
申请号：US11241878
申请日：2005-09-30
申请人： Stefano Parascandola , Roman Knoefler , Stephan Riedel , Dominik Olligs , Torsten Mueller , Dirk Caspary
发明人： Stefano Parascandola , Roman Knoefler , Stephan Riedel , Dominik Olligs , Torsten Mueller , Dirk Caspary
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11565 , H01L27/11568
摘要： The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are reserved by a blocking layer to be occupied by the bit line contacts. In these areas, the hard mask is used to form contact holes, which are self-aligned with the implanted buried bit lines. Between the blocked areas, the word lines are arranged normally to the bit lines.
摘要翻译：位线通过牺牲性硬掩模层的掺杂剂的注入而产生，牺牲性硬掩模层随后由存储单元阵列中由多晶硅形成的栅电极代替。横向于位线运行的存储单元阵列的条纹区域由阻塞层保留以被位线触点占据。在这些区域中，硬掩模用于形成与植入的掩埋位线自对准的接触孔。在阻塞区域之间，字线正常布置在位线上。

10. 发明申请

US20070057318A1 Semiconductor memory device and method of production 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20070057318A1
公开(公告)日：2007-03-15
申请号：US11228036
申请日：2005-09-15
申请人： Lars Bach , Dominik Olligs , Torsten Mueller , Veronika Polei
发明人： Lars Bach , Dominik Olligs , Torsten Mueller , Veronika Polei
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/7923 , H01L27/11568 , H01L29/40117 , H01L29/42352
摘要： A semiconductor substrate is provided with a recess. A memory layer or memory layer sequence is applied to sidewalls and the bottom of the recess. The memory layer is formed into two separate portions at opposite sidewalls of the recess either by reducing the memory layer to sidewall spacers or by forming sidewall spacers and removing portions of the memory layer that are not covered by the spacers. A gate electrode is applied into the recess, and source/drain regions are formed by an implantation of doping atoms adjacent to the sidewalls of the recess and the remaining portions of the memory layer. The memory layer can especially be a dielectric material suitable for charge-trapping.
摘要翻译：半导体衬底设置有凹部。存储层或存储器层序列被施加到凹槽的侧壁和底部。存储层通过将存储层减小到侧壁间隔物或通过形成侧壁间隔物和去除未被间隔物覆盖的存储层的部分而在凹槽的相对侧壁处形成两个分开的部分。栅电极被施加到凹槽中，并且通过注入与凹槽的侧壁和存储层的其余部分相邻的掺杂原子来形成源/漏区。存储层可以特别地是适用于电荷俘获的电介质材料。

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