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1. 发明授权

US07041589B2 Metal bump with an insulating sidewall and method of fabricating thereof 有权
公开(公告)号：US07041589B2
公开(公告)日：2006-05-09
申请号：US10656248
申请日：2003-09-08
申请人： Ming-Yi Lay , Yong-Fen Hsieh , Shang-Kung Tsai , Chin-Kun Lo
发明人： Ming-Yi Lay , Yong-Fen Hsieh , Shang-Kung Tsai , Chin-Kun Lo
IPC分类号： H01L21/4763
CPC分类号： H01L24/16 , H01L24/11 , H01L24/13 , H01L2224/05573 , H01L2224/10126 , H01L2224/1147 , H01L2224/1182 , H01L2224/11831 , H01L2224/11902 , H01L2224/13016 , H01L2224/13099 , H01L2224/131 , H01L2224/13565 , H01L2224/136 , H01L2224/2929 , H01L2224/293 , H01L2224/81903 , H01L2224/83851 , H01L2924/0001 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H05K3/323 , H05K2201/0367 , H05K2203/0597 , H01L2224/29099 , H01L2924/00 , H01L2224/05599
摘要： Metal bumps for connecting a nonconducting substrate and a chip without lateral shorting are provided. In a first preferred embodiment, an insulating layer covers the entire sidewalls of all the metal bumps. In a second preferred embodiment, predetermined portions of a first metal bump and a second metal bump are covered with an insulating layer. For example, a first predetermined portion of the sidewall of the first metal bump may be zcovered with an insulating layer, while a second predetermined portion of the sidewall of the second sidewall is also covered with an insulating layer.

2. 发明授权

US6093618A Method of fabricating a shallow trench isolation structure 失效
标题翻译：制造浅沟槽隔离结构的方法
公开(公告)号：US6093618A
公开(公告)日：2000-07-25
申请号：US98251
申请日：1998-06-16
申请人： Chih-Rong Chen , Yunn-Ming Tsou , Yong-Fen Hsieh
发明人： Chih-Rong Chen , Yunn-Ming Tsou , Yong-Fen Hsieh
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A method of fabricating a shallow trench isolation structure includes defining a shallow trench isolation region on a substrate covered by a first oxide layer and a mask layer. Then, covering the inner surface of the shallow trench with a silicon nitride layer. After a thermal treatment, two oxide layers are formed at the two sides of the silicon nitride layer, respectively. Then, another oxide layer is formed to fill the shallow trench. Next, a planarization process is performed until the mask layer is exposed. The mask layer and the first oxide layer and the oxide layer higher than the substrate are removed.
摘要翻译：制造浅沟槽隔离结构的方法包括在由第一氧化物层和掩模层覆盖的衬底上限定浅沟槽隔离区域。然后，用氮化硅层覆盖浅沟槽的内表面。在热处理之后，分别在氮化硅层的两侧形成两个氧化物层。然后，形成另一氧化物层以填充浅沟槽。接下来，进行平坦化处理，直到掩模层露出。除去掩模层和第一氧化物层和高于衬底的氧化物层。

3. 发明授权

US6022457A Method of manufacturing cobalt silicide layer 失效
标题翻译：钴硅化物层的制造方法
公开(公告)号：US6022457A
公开(公告)日：2000-02-08
申请号：US45980
申请日：1998-03-18
申请人： Hsin-Yuan Huang , Yuan-Ching Peng , Lih-Juann Chen , Yong-Fen Hsieh
发明人： Hsin-Yuan Huang , Yuan-Ching Peng , Lih-Juann Chen , Yong-Fen Hsieh
IPC分类号： H01L21/285 , C23C14/34
CPC分类号： H01L21/28518
摘要： A method of manufacturing a cobalt suicide layer in the present invention has a silicon layer formation step. The silicon layer is formed at the interface between the cobalt layer and titanium layer, therefore the interface is smoother in this invention than in other conventional methods, and there are no voids formed at the interface. Moreover, consumption of the silicon can be controlled by adjusting the thickness of the silicon layer.
摘要翻译：本发明的硅化钴层的制造方法具有硅层形成工序。硅层形成在钴层和钛层之间的界面处，因此本发明的界面比其它常规方法更平滑，并且在界面处没有形成空隙。此外，可以通过调整硅层的厚度来控制硅的消耗。

4. 发明授权

US5897373A Method of manufacturing semiconductor components having a titanium nitride layer 失效
标题翻译：制造具有氮化钛层的半导体部件的方法
公开(公告)号：US5897373A
公开(公告)日：1999-04-27
申请号：US870822
申请日：1997-06-06
申请人： Yuan-Ching Peng , Lih-Juann Chen , Wen-Yi Hsieh , Jenn-Tarng Lin , Yong-Fen Hsieh
发明人： Yuan-Ching Peng , Lih-Juann Chen , Wen-Yi Hsieh , Jenn-Tarng Lin , Yong-Fen Hsieh
IPC分类号： H01L21/285 , H01L21/283
CPC分类号： H01L21/28518
摘要： The present invention relates to a method of manufacturing semiconductor components having a titanium nitride layer including the steps of providing a semiconductor substrate with a transistor including a gate and source/drain regions, depositing an insulating layer above the semiconductor substrate, etching the insulating layer to form an opening exposing the source/drain region below, depositing an ultra-thin titanium nitride layer having a grainy particulate profile and a thickness of about 0.5 nm to 2 nm around the edge and at the bottom of the opening, depositing a metallic layer over various aforementioned layers, and forming a metal silicide layer by heating the semiconductor substrate to allow the metallic layer to react with silicon on the semiconductor substrate surface.
摘要翻译：本发明涉及一种制造具有氮化钛层的半导体元件的方法，包括以下步骤：向半导体衬底提供包括栅极和源/漏区的晶体管，在半导体衬底上沉积绝缘层，将绝缘层蚀刻到形成暴露下面的源极/漏极区域的开口，在开口的边缘和底部沉积具有粒状颗粒轮廓和约0.5nm至2nm的厚度的超薄氮化钛层，沉积金属层各种上述层，并且通过加热半导体衬底形成金属硅化物层，以允许金属层与半导体衬底表面上的硅反应。

5. 发明授权

US5482876A Field effect transistor without spacer mask edge defects 失效
标题翻译：场效应晶体管，无间隔掩模边缘缺陷
公开(公告)号：US5482876A
公开(公告)日：1996-01-09
申请号：US450266
申请日：1995-05-25
申请人： Yong-Fen Hsieh , Shu-Ying Lu , Wen-Ching Tsai
发明人： Yong-Fen Hsieh , Shu-Ying Lu , Wen-Ching Tsai
IPC分类号： H01L21/265 , H01L21/266 , H01L21/3105 , H01L21/336
CPC分类号： H01L29/66598 , H01L21/2652 , H01L21/266 , H01L21/3105 , H01L29/66575 , Y10S438/965
摘要： A field effect transistor which is not susceptible to mask edge defects at its gate spacer oxides. The transistor is formed upon a (100) silicon semiconductor substrate through successive layering of a gate oxide, and a gate electrode. A pair of gate spacer oxides is then formed covering opposite edges of the gate oxide and the gate electrode. A screen oxide is then formed over the surface of the semiconductor substrate, the gate and the gate spacer oxides. The upper surface of the screen oxide has an angle of elevation not exceeding 54.44 degrees with respect to the semiconductor substrate. The screen oxide also smoothly flows from thicker regions at the junctures of the gate spacer oxides and the semiconductor substrate to thinner regions over the surface of the semiconductor substrate. The semiconductor substrate adjoining the gate spacer oxides is then ion implanted through the screen oxide to form amorphous source/drain electrodes. The penetration depth of the ion implant is greater than the thickness of the thinner regions of the screen oxide and no greater than the thickness of the thicker regions of the screen oxide. Finally, the amorphous source/drain electrodes are annealed. In a second embodiment, a dopes glass screen layer is used in place of the screen oxide layer. The glass layer must be removed prior to annealing the amorphous source/drain electrodes.
摘要翻译：场效应晶体管，其栅极间隔氧化物不易受掩模边缘缺陷的影响。晶体管通过栅极氧化物和栅极电极的连续分层形成在（100）硅半导体衬底上。然后形成一对栅极间隔氧化物，覆盖栅极氧化物和栅电极的相对边缘。然后在半导体衬底，栅极和栅极间隔物氧化物的表面上形成屏幕氧化物。屏幕氧化物的上表面相对于半导体衬底具有不超过54.44度的仰角。屏蔽氧化物也从栅极间隔物氧化物和半导体衬底的接合处的较厚区域平滑地流过半导体衬底的表面上较薄的区域。然后，与栅极间隔物氧化物相邻的半导体衬底通过荧光体氧化物离子注入，以形成无定形源/漏电极。离子注入的穿透深度大于屏幕氧化物的较薄区域的厚度，并且不大于屏幕氧化物较厚区域的厚度。最后，对非晶态/漏极进行退火。在第二实施例中，使用掺杂玻璃屏幕层代替屏幕氧化物层。必须在退火非晶态/漏极之前去除玻璃层。

6. 发明申请

US20140007709A1 SPECIMEN PREPARATION FOR TEM 有权
标题翻译： TEM样品制备
公开(公告)号：US20140007709A1
公开(公告)日：2014-01-09
申请号：US13544019
申请日：2012-07-09
申请人： Yong-Fen HSIEH , Chih-Hsun CHU , Pradeep SHARMA , Yu-Feng KO , Chung-Shi YANG , Lin-Ai TAI , Yu-Ching CHEN
发明人： Yong-Fen HSIEH , Chih-Hsun CHU , Pradeep SHARMA , Yu-Feng KO , Chung-Shi YANG , Lin-Ai TAI , Yu-Ching CHEN
IPC分类号： B01L3/00 , G01N1/28
CPC分类号： H01J37/261 , B01L3/508 , B01L2200/0678 , B01L2300/0822 , G01N1/28 , G01N1/4022 , G01N23/02 , G01N2001/4027 , H01J37/16 , H01J37/20 , H01J37/222 , H01J37/3178 , H01J2237/2007 , H01J2237/2602 , H01J2237/2802
摘要： A specimen kit having a tiny chamber is disclosed for a specimen preparation for TEM. The space height of the chamber is far smaller than dimensions of blood cells and therefore is adapted to sort nanoparticles from the blood cells. The specimen prepared under this invention is suitable for TEM observation over a true distribution status of nanoparticles in blood. The extremely tiny space height in Z direction eliminates the possibility of aggregation of the nanoparticles and/or agglomeration in Z direction during drying; therefore, a specimen prepared under this invention is suitable for TEM observation over the dispersion and/or agglomeration of nanoparticles in a blood.
摘要翻译：公开了一种用于TEM的样品制备的具有微小室的标本试剂盒。室的空间高度远小于血细胞的尺寸，因此适于从血细胞分选纳米颗粒。根据本发明制备的样品适用于在血液中纳米颗粒的真实分布状态的TEM观察。在Z方向极微小的空间高度消除了在干燥过程中纳米颗粒聚集和/或Z方向附聚的可能性; 因此，根据本发明制备的样品适用于在血液中纳米颗粒的分散和/或附聚的TEM观察。

7. 发明授权

US06958539B2 Metal bump with an insulating sidewall and method of fabricating thereof 有权
标题翻译：具有绝缘侧壁的金属凸块及其制造方法
公开(公告)号：US06958539B2
公开(公告)日：2005-10-25
申请号：US09764207
申请日：2001-01-19
申请人： Ming-Yi Lay , Yong-Fen Hsieh , Shang-Kung Tsai , Chin-Kun Lo
发明人： Ming-Yi Lay , Yong-Fen Hsieh , Shang-Kung Tsai , Chin-Kun Lo
IPC分类号： H01L21/60 , H01L23/485 , H05K3/32 , H01L29/41
CPC分类号： H01L24/16 , H01L24/11 , H01L24/13 , H01L2224/05573 , H01L2224/10126 , H01L2224/1147 , H01L2224/1182 , H01L2224/11831 , H01L2224/11902 , H01L2224/13016 , H01L2224/13099 , H01L2224/131 , H01L2224/13565 , H01L2224/136 , H01L2224/2929 , H01L2224/293 , H01L2224/81903 , H01L2224/83851 , H01L2924/0001 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H05K3/323 , H05K2201/0367 , H05K2203/0597 , H01L2224/29099 , H01L2924/00 , H01L2224/05599
摘要： Metal bumps for connecting a nonconducting substrate and a chip without lateral shorting are provided. In a first preferred embodiment, an insulating layer covers the entire sidewalls of all the metal bumps. In a second preferred embodiment, predetermined portions of a first metal bump and a second metal bump are covered with an insulating layer. For example, a first predetermined portion of the sidewall of the first metal bump may be zcovered with an insulating layer, while a second predetermined portion of the sidewall of the second sidewall is also covered with an insulating layer.
摘要翻译：提供用于连接不导电基板和不具有侧向短路的芯片的金属凸块。在第一优选实施例中，绝缘层覆盖所有金属凸块的整个侧壁。在第二优选实施例中，第一金属凸块和第二金属凸块的预定部分被绝缘层覆盖。例如，第一金属凸块的侧壁的第一预定部分可以被绝缘层覆盖，而第二侧壁的侧壁的第二预定部分也被绝缘层覆盖。

8. 发明授权

US06228711B1 Method of fabricating dynamic random access memory 失效
标题翻译：制作动态随机存取存储器的方法
公开(公告)号：US06228711B1
公开(公告)日：2001-05-08
申请号：US09451426
申请日：1999-11-30
申请人： Yong-Fen Hsieh
发明人： Yong-Fen Hsieh
IPC分类号： H01L218242
CPC分类号： H01L28/91 , H01L27/10814 , H01L28/84
摘要： The present invention is a method of fabricating a dynamic random access memory. The node contact opening and the capacitor opening are combined in a step of the dual damascene opening process during the capacitor formation. The bottom of the capacitor is embedded in the dual damascene opening. The conducting layer used for forming the bottom plates is polished by chemical mechanical polishing to form the bottom plates that are separated each other. Therefore, patterning of bottom plate by photolithography and etching is not necessary in the present invention.
摘要翻译：本发明是制造动态随机存取存储器的方法。在电容器形成期间，在双镶嵌开口工艺的步骤中组合节点接触开口和电容器开口。电容器的底部嵌入双镶嵌开口。用于形成底板的导电层通过化学机械抛光抛光，形成彼此分离的底板。因此，在本发明中不需要通过光刻和蚀刻对底板进行图案化。

9. 发明授权

US08969827B2 Specimen preparation for transmission electron microscopy 有权
标题翻译：透射电子显微镜样品制备
公开(公告)号：US08969827B2
公开(公告)日：2015-03-03
申请号：US13544019
申请日：2012-07-09
申请人： Yong-Fen Hsieh , Chih-Hsun Chu , Pradeep Sharma , Yu-Feng Ko , Chung-Shi Yang , Lin-Ai Tai , Yu-Ching Chen
发明人： Yong-Fen Hsieh , Chih-Hsun Chu , Pradeep Sharma , Yu-Feng Ko , Chung-Shi Yang , Lin-Ai Tai , Yu-Ching Chen
IPC分类号： B82Y35/00 , G01N1/40 , G01N23/02 , G01N33/49
CPC分类号： H01J37/261 , B01L3/508 , B01L2200/0678 , B01L2300/0822 , G01N1/28 , G01N1/4022 , G01N23/02 , G01N2001/4027 , H01J37/16 , H01J37/20 , H01J37/222 , H01J37/3178 , H01J2237/2007 , H01J2237/2602 , H01J2237/2802
摘要： A specimen kit having a tiny chamber is disclosed for a specimen preparation for TEM. The space height of the chamber is far smaller than dimensions of blood cells and therefore is adapted to sort nanoparticles from the blood cells. The specimen prepared under this invention is suitable for TEM observation over a true distribution status of nanoparticles in blood. The extremely tiny space height in Z direction eliminates the possibility of aggregation of the nanoparticles and/or agglomeration in Z direction during drying; therefore, a specimen prepared under this invention is suitable for TEM observation over the dispersion and/or agglomeration of nanoparticles in a blood.
摘要翻译：公开了一种用于TEM的样品制备的具有微小室的标本试剂盒。室的空间高度远小于血细胞的尺寸，因此适于从血细胞分选纳米颗粒。根据本发明制备的样品适用于在血液中纳米颗粒的真实分布状态的TEM观察。在Z方向极微小的空间高度消除了在干燥过程中纳米颗粒聚集和/或Z方向附聚的可能性; 因此，根据本发明制备的样品适用于在血液中纳米颗粒的分散和/或附聚的TEM观察。

10. 发明授权

US6043148A Method of fabricating contact plug 失效
标题翻译：制造接触塞的方法
公开(公告)号：US6043148A
公开(公告)日：2000-03-28
申请号：US61613
申请日：1998-04-16
申请人： Yuan-Ching Peng , Lih-Juann Chen , Yu-Ru Yang , Win-Yi Hsieh , Yong-Fen Hsieh
发明人： Yuan-Ching Peng , Lih-Juann Chen , Yu-Ru Yang , Win-Yi Hsieh , Yong-Fen Hsieh
IPC分类号： H01L21/768 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/76856 , H01L21/76843
摘要： A method of fabricating a metal plug. On a semiconductor substrate comprising a MOS device, a dielectric layer, and a via hole penetrating though the dielectric layer, a conformal titanium layer is formed on the dielectric layer and the via hole. A low temperature annealing is formed in a nitrogen environment, so that a surface of the titanium layer is transformed into a first thin titanium nitride layer. A conformal second titanium nitride layer is formed on the first thin titanium nitride layer by using collimator sputtering. A metal layer is formed and etched back on the second titanium nitride layer to form a metal plug.
摘要翻译：一种制造金属插头的方法。在包括MOS器件，电介质层和穿过电介质层的通孔的半导体衬底上，在电介质层和通孔上形成共形钛层。在氮气环境中形成低温退火，使得钛层的表面转变为第一薄氮化钛层。通过使用准直器溅射在第一薄氮化钛层上形成保形第二氮化钛层。在第二氮化钛层上形成金属层并回蚀刻以形成金属塞。

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