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1. 发明授权

US6093618A Method of fabricating a shallow trench isolation structure 失效
标题翻译：制造浅沟槽隔离结构的方法
公开(公告)号：US6093618A
公开(公告)日：2000-07-25
申请号：US98251
申请日：1998-06-16
申请人： Chih-Rong Chen , Yunn-Ming Tsou , Yong-Fen Hsieh
发明人： Chih-Rong Chen , Yunn-Ming Tsou , Yong-Fen Hsieh
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A method of fabricating a shallow trench isolation structure includes defining a shallow trench isolation region on a substrate covered by a first oxide layer and a mask layer. Then, covering the inner surface of the shallow trench with a silicon nitride layer. After a thermal treatment, two oxide layers are formed at the two sides of the silicon nitride layer, respectively. Then, another oxide layer is formed to fill the shallow trench. Next, a planarization process is performed until the mask layer is exposed. The mask layer and the first oxide layer and the oxide layer higher than the substrate are removed.
摘要翻译：制造浅沟槽隔离结构的方法包括在由第一氧化物层和掩模层覆盖的衬底上限定浅沟槽隔离区域。然后，用氮化硅层覆盖浅沟槽的内表面。在热处理之后，分别在氮化硅层的两侧形成两个氧化物层。然后，形成另一氧化物层以填充浅沟槽。接下来，进行平坦化处理，直到掩模层露出。除去掩模层和第一氧化物层和高于衬底的氧化物层。

2. 发明授权

US06080663A Dual damascene 失效
标题翻译：双镶嵌
公开(公告)号：US06080663A
公开(公告)日：2000-06-27
申请号：US191297
申请日：1998-11-13
申请人： Chih-Rong Chen , Wen-Yuan Huang
发明人： Chih-Rong Chen , Wen-Yuan Huang
IPC分类号： H01L21/3115 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76825 , H01L21/76813 , H01L21/31155
摘要： A dual damascene process is provided. A dielectric layer is formed on a substrate having a conductive region. The dielectric layer is selectively doped to form a doped region aligned over the conductive region. The doped region, the dielectric layer underlying the doped region, and another part of the undoped dielectric layer are etched until the conductive region is exposed, so that a dual damascene opening exposing the conductive region and a trench are formed, wherein the dual damascene opening comprising a upper trench and a lower via hole. The dual damascene opening and the trench are filled with a conductive layer.
摘要翻译：提供了双镶嵌工艺。在具有导电区域的基板上形成介电层。电介质层被选择性地掺杂以形成在导电区域上对准的掺杂区域。蚀刻掺杂区域，掺杂区域下面的电介质层和未掺杂电介质层的另一部分，直到导电区域被暴露，从而形成露出导电区域和沟槽的双镶嵌开口，其中双镶嵌开口包括上沟槽和下通孔。双镶嵌开口和沟槽填充有导电层。

3. 发明授权

US6156655A Retardation layer for preventing diffusion of metal layer and fabrication method thereof 失效
标题翻译：用于防止金属层扩散的延迟层及其制造方法
公开(公告)号：US6156655A
公开(公告)日：2000-12-05
申请号：US408612
申请日：1999-09-30
申请人： Ming-Ching Huang , Chih-Rong Chen , Kuai-Jung Ho , Wen-Yuan Huang , Chi-Chin Yeh
发明人： Ming-Ching Huang , Chih-Rong Chen , Kuai-Jung Ho , Wen-Yuan Huang , Chi-Chin Yeh
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76855 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L23/5226 , H01L23/53238 , H01L2924/0002
摘要： A retardation layer of a copper damascene process and the fabrication method thereof, to replace the conventional barrier layer with a laminated layer. The laminated layer combines the conventional barrier layer with a porous layer, wherein the porous layer can be formed either above or below the barrier layer to improve the retardation of the copper atom diffusion. Preferably, the porous layer is formed above the barrier layer.
摘要翻译：铜镶嵌工艺的延迟层及其制造方法，以层压层代替传统的阻挡层。层叠层将常规阻挡层与多孔层组合，其中多孔层可以形成在阻挡层的上方或下方，以改善铜原子扩散的延迟。优选地，多孔层形成在阻挡层上方。

4. 发明授权

US06214709B1 Method of fabricating self-aligned silicide 失效
标题翻译：制造自对准硅化物的方法
公开(公告)号：US06214709B1
公开(公告)日：2001-04-10
申请号：US09129460
申请日：1998-08-04
申请人： Chih-Rong Chen
发明人： Chih-Rong Chen
IPC分类号： H01L213205
CPC分类号： H01L21/28518
摘要： A method of fabricating salicide. A metal layer is formed on a substrate with a polysilicon gate and a source/drain region. A material layer is then formed on the metal layer, wherein the material is selected to produce compressive stress as compressive stress is produced on the substrate and to produce tensile stress as tensile stress is produced in the substrate. The material layer needs to be chosen with the same stress produced by the metal layer. A thermal process is then performed on the substrate to form a silicide on the polysilicon gate and the source/drain region. The material layer and the unreacted metal layer are removed and therefore the salicide process is accomplished.
摘要翻译：一种制造自杀剂的方法。在具有多晶硅栅极和源极/漏极区域的衬底上形成金属层。然后在金属层上形成材料层，其中选择材料以产生压缩应力，因为在衬底上产生压应力并产生拉伸应力，因为在衬底中产生拉伸应力。材料层需要用金属层产生的相同的应力来选择。然后在衬底上进行热处理，以在多晶硅栅极和源极/漏极区域上形成硅化物。去除材料层和未反应的金属层，因此完成自对准硅化物工艺。

5. 发明授权

US06171732B2 Method of manufacturing and application of dual alignment photomask 失效
标题翻译：双取向光掩模的制造和应用方法
公开(公告)号：US06171732B2
公开(公告)日：2001-01-09
申请号：US09304627
申请日：1999-05-04
申请人： Chih-Rong Chen , Wen-Yuan Huang
发明人： Chih-Rong Chen , Wen-Yuan Huang
IPC分类号： G03F900
CPC分类号： G03F1/38 , G03F7/70291
摘要： A method of forming a dual alignment photomask. The method includes the steps of depositing a light-blocking layer over a glass plate, and then patterning the light-blocking layer. Next, a switchable mask layer is deposited over the light-blocking layer and the glass plate, after which the switchable mask layer is patterned. Finally, a protective layer is formed over the switchable mask layer, the light-blocking layer and the glass plate. The switchable mask layer can be changed from a light-passing state to a light-blocking state by simply changing the surrounding temperature. Therefore, through proper setting the temperature, the same photomask can be used to form trenches and vias of dual damascene structures. Thus, some mask-making cost can be saved and errors due to mask misalignment can be avoided.
摘要翻译：形成双重取向光掩模的方法。该方法包括以下步骤：在玻璃板上沉积遮光层，然后对遮光层进行图案化。接下来，在遮光层和玻璃板上沉积可切割掩模层，然后对可切换掩模层进行图案化。最后，在可切换掩模层，遮光层和玻璃板上形成保护层。通过简单地改变周围温度，可切换掩模层可以从光通过状态变为遮光状态。因此，通过适当设定温度，可以使用相同的光掩模来形成双镶嵌结构的沟槽和通孔。因此，可以节省一些掩模制造成本，并且可以避免由于掩模不对准引起的误差。

6. 发明授权

US6066532A Method of fabricating embedded gate electrodes 失效
标题翻译：嵌入式栅电极的制造方法
公开(公告)号：US6066532A
公开(公告)日：2000-05-23
申请号：US419434
申请日：1999-10-18
申请人： Chih-Rong Chen , Chi-Chin Yeh
发明人： Chih-Rong Chen , Chi-Chin Yeh
IPC分类号： H01L21/336 , H01L29/423
CPC分类号： H01L29/66621 , H01L29/665 , H01L29/78
摘要： A method of fabricating an embedded gate electrode is disclosed. The method includes the steps of: Providing a semiconductor substrate; forming a patterned etch resistant mask layer over the semiconductor substrate, wherein the patterned etch resistant mask layer has a first opening for a desired location of a trench; anisotropically etching through the patterned etch resistant mask layer and into the semiconductor substrate, hence forming the trench at the desired location; removing the patterned etch resistant mask layer; depositing a first insulating layer over the semiconductor substrate and filling up the trench; patterning a planarized first insulating layer to define a second opening for the embedded gate electrode; forming a second insulating layer at the bottom of the second opening; depositing a conductive layer over the second insulating layer and filling up the second opening, hence forming the embedded gate electrode; ion implanting the semiconductor substrate to form source/drain regions; forming a spacer on the sidewall of the embedded gate electrode; depositing a refractory metal layer over the entire exposing surface of a resulting structure; and annealing the refractory metal layer to form a silicide layer on the embedded gate electrode and elsewhere on the source/drain regions.
摘要翻译：公开了一种制造嵌入式栅电极的方法。该方法包括以下步骤：提供半导体衬底; 在所述半导体衬底上形成图案化的耐蚀刻掩模层，其中所述图案化耐蚀刻掩模层具有用于沟槽的期望位置的第一开口; 各向异性蚀刻通过图案化的耐蚀刻掩模层并进入半导体衬底，从而在期望的位置形成沟槽; 去除图案化的抗蚀刻掩模层; 在所述半导体衬底上沉积第一绝缘层并填充所述沟槽; 图案化平坦化的第一绝缘层以限定用于嵌入式栅电极的第二开口; 在所述第二开口的底部形成第二绝缘层; 在第二绝缘层上沉积导电层并填充第二开口，从而形成嵌入式栅电极; 离子注入半导体衬底以形成源/漏区; 在嵌入式栅电极的侧壁上形成间隔物; 在所得结构的整个暴露表面上沉积难熔金属层; 并对难熔金属层进行退火，以在嵌入式栅极电极和源极/漏极区域上的其它地方形成硅化物层。

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