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1. 发明授权

US09246015B2 Vertical channel transistor structure and manufacturing method thereof 有权
标题翻译：垂直沟道晶体管结构及其制造方法
公开(公告)号：US09246015B2
公开(公告)日：2016-01-26
申请号：US12892044
申请日：2010-09-28
申请人： Tzu-Hsuan Hsu , Yen-Hao Shih , Chia-Wei Wu
发明人： Tzu-Hsuan Hsu , Yen-Hao Shih , Chia-Wei Wu
IPC分类号： H01L29/66 , H01L29/792 , H01L27/115 , H01L29/423 , H01L27/12
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/42352
摘要： A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate.
摘要翻译：提供了垂直沟道晶体管结构。该结构包括基板，通道，盖层，电荷捕获层，源极和漏极。通道形成为从基板突出的鳍状结构。盖层沉积在鳍状结构上。盖层和鳍状结构具有基本上相同的宽度。电荷俘获层沉积在盖层上和鳍状结构的两个垂直表面上。栅极沉积在电荷捕获层上并在鳍状结构的两个垂直表面上沉积。源极和漏极分别位于鳍状结构的两侧并与栅极相对。

2. 发明授权

US08816423B2 Semiconducting multi-layer structure and method for manufacturing the same 有权
标题翻译：半导体多层结构及其制造方法
公开(公告)号：US08816423B2
公开(公告)日：2014-08-26
申请号：US13584366
申请日：2012-08-13
申请人： Erh-Kun Lai , Yen-Hao Shih
发明人： Erh-Kun Lai , Yen-Hao Shih
IPC分类号： H01L29/792
CPC分类号： H01L27/11582 , H01L27/11529 , H01L27/11548 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： A semiconducting multi-layer structure comprising a plurality of first conductive layers, a plurality of first insulating layers and a second conductive layer is disclosed. The first conductive layers are separately disposed. Each of the first conductive layers has an upper surface, a bottom surface opposite to the upper surface and a lateral surface. The first insulating layers surround the peripherals of the first conductive layers. Each of the first insulating layers covers at least a part of the upper surface of each of the first conductive layers, at least a part of the bottom surface of each of the first conductive layers and the two lateral surface of each of the first conductive layers. The second conductive layer covers the first conductive layers and the first insulating layers.
摘要翻译：公开了一种包括多个第一导电层，多个第一绝缘层和第二导电层的半导体多层结构。第一导电层分开设置。每个第一导电层具有上表面，与上表面相对的底表面和侧表面。第一绝缘层围绕第一导电层的外围设备。每个第一绝缘层覆盖每个第一导电层的上表面的至少一部分，每个第一导电层的底表面的至少一部分和每个第一导电层的两个侧表面。第二导电层覆盖第一导电层和第一绝缘层。

3. 发明申请

US20140197516A1 INTEGRATION OF 3D STACKED IC DEVICE WITH PERIPHERAL CIRCUITS 有权
标题翻译： 3D堆叠IC器件与外围电路的集成
公开(公告)号：US20140197516A1
公开(公告)日：2014-07-17
申请号：US13739914
申请日：2013-01-11
申请人： Hang-Ting Lue , Yi-Hsuan Hsiao , Shih-Hung Chen , Yen-Hao Shih
发明人： Hang-Ting Lue , Yi-Hsuan Hsiao , Shih-Hung Chen , Yen-Hao Shih
IPC分类号： H01L21/66 , H01L29/06
CPC分类号： H01L22/12 , H01L22/20 , H01L27/11531 , H01L27/11556 , H01L27/11573 , H01L27/11582 , H01L29/0649
摘要： An integrated circuit device includes a substrate including a first region and a second region. A pit is formed in the first region. A stack of active layers alternating with insulating layers is deposited in the pit. The stack includes a particular insulating layer. The particular insulating layer has a first thickness, where a sum of the first thickness, thickness of active layers, and thicknesses of other insulating layers is essentially equal to a depth of the pit. The first thickness is different than the thicknesses of the other insulating layers by an amount within a range of process variations for the depth of the pit, for the thicknesses of the active layers, and for the thicknesses of other insulating layers. The device includes a planarized surface over the first and second regions, where an uppermost one of the active layers has a top surface below the planarized surface.
摘要翻译：集成电路器件包括包括第一区域和第二区域的衬底。在第一区域形成凹坑。与绝缘层交替的一叠有源层沉积在凹坑中。堆叠包括特定的绝缘层。特定绝缘层具有第一厚度，其中第一厚度，有源层的厚度和其它绝缘层的厚度之和基本上等于凹坑的深度。第一厚度不同于其它绝缘层的厚度，在凹坑的深度，有源层的厚度和其它绝缘层的厚度的工艺变化范围内的量。该装置包括在第一和第二区域之上的平坦化表面，其中最上面的一个活性层在平坦化表面下方具有顶表面。

4. 发明申请

US20140140131A1 THREE DIMENSIONAL GATE STRUCTURES WITH HORIZONTAL EXTENSIONS 有权
标题翻译：三维门结构与水平扩展
公开(公告)号：US20140140131A1
公开(公告)日：2014-05-22
申请号：US13681133
申请日：2012-11-19
申请人： Teng-Hao Yeh , Yen-Hao Shih , Yan-Ru Chen
发明人： Teng-Hao Yeh , Yen-Hao Shih , Yan-Ru Chen
IPC分类号： H01L29/788 , G11C5/06 , G11C16/04 , H01L21/28
CPC分类号： G11C5/06 , G11C5/063 , G11C16/0483 , G11C2213/71 , H01L21/28282 , H01L27/1157 , H01L27/11582 , H01L29/7926
摘要： A device on an integrated circuit includes a stack of alternating semiconductor lines and insulating lines, and a gate structure over the stack of semiconductor lines. The gate structure includes a vertical portion adjacent the stack on the at least one side, and horizontal extension portions between the semiconductor lines. Sides of the insulating lines can be recessed relative to sides of the semiconductor lines, so at least one side of the stack includes recesses between semiconductor lines. The horizontal extension portions can be in the recesses. The horizontal extension portions have inside surfaces adjacent the sides of the insulating lines, and outside surfaces that can be flush with the sides of the semiconductor lines. The device may include a second gate structure spaced away from the first mentioned gate structure, and an insulating element between horizontal extension portions of the second gate structure and the first mentioned gate structure.
摘要翻译：集成电路中的器件包括交替的半导体线路和绝缘线路的堆叠以及在半导体线路堆叠上的栅极结构。栅极结构包括在至少一个侧面上与堆叠相邻的垂直部分和半导体线之间的水平延伸部分。绝缘线的边可以相对于半导体线的侧面凹陷，因此堆叠的至少一侧包括半导体线之间的凹槽。水平延伸部分可以在凹槽中。水平延伸部具有与绝缘线的侧面相邻的内表面以及可与半导体线的侧面齐平的外表面。器件可以包括与第一提到的栅极结构间隔开的第二栅极结构，以及在第二栅极结构的水平延伸部分和第一个提到的栅极结构之间的绝缘元件。

5. 发明申请

US20130119455A1 NAND FLASH WITH NON-TRAPPING SWITCH TRANSISTORS 有权
标题翻译：具有非捕获开关晶体管的NAND闪存
公开(公告)号：US20130119455A1
公开(公告)日：2013-05-16
申请号：US13294852
申请日：2011-11-11
申请人： SHIH-HUNG CHEN , Hang-Ting Lue , Yen-Hao Shih
发明人： SHIH-HUNG CHEN , Hang-Ting Lue , Yen-Hao Shih
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/1157 , H01L27/11578
摘要： A manufacturing method for a memory array includes first forming a multilayer stack of dielectric material on a plurality of semiconductor strips, and then exposing the multilayer stack in switch transistor regions. The multilayer stacks exposed in the switch transistor regions are processed to form gate dielectric structures that are different than the dielectric charge trapping structures. Word lines and select lines are then formed. A 3D array of dielectric charge trapping memory cells includes stacks of NAND strings of memory cells. A plurality of switch transistors are coupled to the NAND strings, the switch transistors including gate dielectric structures wherein the gate dielectric structures are different than the dielectric charge trapping structures.
摘要翻译：一种用于存储器阵列的制造方法包括首先在多个半导体条上形成多层电介质材料，然后在开关晶体管区域中暴露多层叠层。在开关晶体管区域中暴露的多层堆叠被处理以形成不同于介电电荷俘获结构的栅介质结构。然后形成字线和选择线。介质电荷俘获存储器单元的3D阵列包括存储器单元的NAND串的堆叠。多个开关晶体管耦合到NAND串，开关晶体管包括栅极电介质结构，其中栅极电介质结构不同于介电电荷俘获结构。

6. 发明授权

US08437192B2 3D two bit-per-cell NAND flash memory 有权
标题翻译： 3D双比特单元NAND闪存
公开(公告)号：US08437192B2
公开(公告)日：2013-05-07
申请号：US12785291
申请日：2010-05-21
申请人： Hsiang-Lan Lung , Hang-Ting Lue , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee , Tien-Yen Wang
发明人： Hsiang-Lan Lung , Hang-Ting Lue , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee , Tien-Yen Wang
IPC分类号： G11C16/00 , G11C16/02 , G11C16/04 , G11C5/02 , G11C5/06
CPC分类号： H01L27/11578 , G11C16/0483 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： A 3D memory device includes bottom and top memory cubes having respective arrays of vertical NAND string structures. A common source plane comprising a layer of conductive material is between the top and bottom memory cubes. The source plane is supplied a bias voltage such as ground, and is selectively coupled to an end of the vertical NAND string structures of the bottom and top memory cubes. Memory cells in a particular memory cube are read using current through the particular vertical NAND string between the source plane and a corresponding bit line coupled to another end of the particular vertical NAND string.
摘要翻译： 3D存储器件包括具有垂直NAND串结构的相应阵列的底部和顶部存储立方体。包括导电材料层的共同源平面位于顶部和底部存储立方体之间。源平面被提供诸如地的偏置电压，并且选择性地耦合到底部和顶部存储立方体的垂直NAND串结构的一端。通过源平面与耦合到特定垂直NAND串的另一端的对应位线之间的特定垂直NAND串的电流来读取特定存储器立方体中的存储单元。

7. 发明授权

US08374019B2 Phase change memory with fast write characteristics 有权
标题翻译：具有快速写入特性的相变存储器
公开(公告)号：US08374019B2
公开(公告)日：2013-02-12
申请号：US12985253
申请日：2011-01-05
申请人： Chao-I Wu , Yen-Hao Shih , Ming-Hsiu Lee
发明人： Chao-I Wu , Yen-Hao Shih , Ming-Hsiu Lee
IPC分类号： G11C11/00
CPC分类号： H01L45/06 , G11C11/005 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C14/00 , G11C2013/0083 , G11C2013/0092 , H01L27/2463 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1641
摘要： A memory device including programmable resistance memory cells, including electrically pre-stressed target memory cells. The pre-stressed target memory cells have one of a lower voltage transition threshold, a shorter duration set interval and a longer reset state retention characteristic. Biasing circuitry is included on the device configured to control the pre-stressing operations, and to apply read, set and reset operations that can be modified for the pre-stressed memory cells.
摘要翻译：一种包括可编程电阻存储单元的存储器件，包括电预应力目标存储单元。预应力目标存储单元具有较低电压转变阈值，较短持续时间设定间隔和较长复位状态保持特性之一。设备上包括偏置电路，用于控制预应力操作，以及应用对预应力存储单元进行修改的读取，置位和复位操作。

8. 发明申请

US20120193595A1 COMPOSITE TARGET SPUTTERING FOR FORMING DOPED PHASE CHANGE MATERIALS 有权
标题翻译：用于形成相变材料的复合靶材溅射
公开(公告)号：US20120193595A1
公开(公告)日：2012-08-02
申请号：US13076169
申请日：2011-03-30
申请人： Huai-Yu Cheng , Chieh-Fang Chen , Hsiang-Lan Lung , Yen-Hao Shih , Simone Raoux , Matthew J. Breitwisch
发明人： Huai-Yu Cheng , Chieh-Fang Chen , Hsiang-Lan Lung , Yen-Hao Shih , Simone Raoux , Matthew J. Breitwisch
IPC分类号： H01L45/00 , C23C14/14 , C23C14/34
CPC分类号： H01L47/00 , C23C14/06 , C23C14/0623 , C23C14/3414 , H01L21/06 , H01L27/24 , H01L45/144 , H01L45/1625
摘要： A layer of phase change material with silicon or another semiconductor, or a silicon-based or other semiconductor-based additive, is formed using a composite sputter target including the silicon or other semiconductor, and the phase change material. The concentration of silicon or other semiconductor is more than five times greater than the specified concentration of silicon or other semiconductor in the layer being formed. For silicon-based additive in GST-type phase change materials, sputter target may comprise more than 40 at % silicon. Silicon-based or other semiconductor-based additives can be formed using the composite sputter target with a flow of reactive gases, such as oxygen or nitrogen, in the sputter chamber during the deposition.
摘要翻译：使用包括硅或其它半导体的复合溅射靶和相变材料形成具有硅或另一半导体或硅基或其它基于半导体的添加剂的相变材料层。硅或其他半导体的浓度比正在形成的层中规定浓度的硅或其它半导体的浓度高五倍以上。对于GST型相变材料中的硅基添加剂，溅射靶可以包含超过40at％的硅。可以在沉积期间使用复合溅射靶在溅射室中形成具有诸如氧或氮的反应气体流的硅基或其它基于半导体的添加剂。

9. 发明授权

US08026136B2 Methods of forming low hydrogen concentration charge-trapping layer structures for non-volatile memory 有权
标题翻译：形成用于非挥发性记忆体的低氢浓度电荷捕获层结构的方法
公开(公告)号：US08026136B2
公开(公告)日：2011-09-27
申请号：US11964322
申请日：2007-12-26
申请人： Yen-Hao Shih , Min-Ta Wu , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Yen-Hao Shih , Min-Ta Wu , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L21/8238 , H01L21/311
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/513 , H01L29/518
摘要： Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×1011/cm−2, and methods for forming such memory cells.
摘要翻译：存储单元包括：半导体衬底，具有由沟道区分开的至少两个源极/漏极区域; 设置在通道区域上方的电荷捕获结构; 以及设置在电荷捕获结构上方的栅极; 其中所述电荷捕获结构包括底部绝缘层，第一电荷俘获层和第二电荷俘获层，其中所述底部绝缘层和所述基底之间的界面的氢浓度小于约3×1011 / cm -2，以及形成这种记忆单元的方法。

10. 发明授权

US07911856B2 Three-dimensional memory devices and methods of manufacturing and operating the same 有权
标题翻译：三维存储器件及其制造和操作方法
公开(公告)号：US07911856B2
公开(公告)日：2011-03-22
申请号：US12471411
申请日：2009-05-25
申请人： Ming-Hsiu Lee , Yen-Hao Shih
发明人： Ming-Hsiu Lee , Yen-Hao Shih
IPC分类号： G11C7/00
CPC分类号： G11C13/0023 , G11C13/00 , G11C13/0004 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L21/84 , H01L27/0688 , H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/1203 , H01L29/66833 , H01L29/792
摘要： A method of accessing memory cells is disclosed. A first signal is sent to at least one layer select transistor. The at least one layer select transistor is activated based on the first signal. Signals are communicated to or from one or more memory cells based on the activated at least layer select transistor.
摘要翻译：公开了访问存储器单元的方法。第一信号被发送到至少一个层选择晶体管。基于第一信号激活至少一个层选择晶体管。基于激活的至少层选择晶体管将信号传送到或来自一个或多个存储器单元。

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