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1. 发明授权

US08987098B2 Damascene word line 有权
标题翻译：大马士革字线
公开(公告)号：US08987098B2
公开(公告)日：2015-03-24
申请号：US13527259
申请日：2012-06-19
申请人： Shih-Hung Chen , Yen-Hao Shih , Hang-Ting Lue
发明人： Shih-Hung Chen , Yen-Hao Shih , Hang-Ting Lue
IPC分类号： H01L21/336 , H01L27/115
CPC分类号： H01L27/11578 , H01L27/11565
摘要： The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Partly oxidized lines of material such as silicon are made over a plurality of stacked nonvolatile memory structures. Word line trenches are made in the partly oxidized lines, by removing the unoxidized lines from the intermediate parts of the partly oxidized lines, leaving the plurality of oxidized lines at the outer parts of the plurality of partly oxidized lines. Word lines are made in the word line trenches over the plurality of stacked nonvolatile memory structures.
摘要翻译：该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。在多个堆叠的非易失性存储器结构上制造部分氧化的材料线如硅。通过从部分氧化的线的中间部分去除未氧化的线，在多个部分氧化的线的外部部分留下多条氧化线，在部分氧化的线中形成字线沟槽。在多个堆叠的非易失性存储器结构中的字线沟槽中形成字线。

2. 发明授权

US08759899B1 Integration of 3D stacked IC device with peripheral circuits 有权
标题翻译：集成3D堆叠式IC器件与外围电路
公开(公告)号：US08759899B1
公开(公告)日：2014-06-24
申请号：US13739914
申请日：2013-01-11
申请人： Hang-Ting Lue , Yi-Hsuan Hsiao , Shih-Hung Chen , Yen-Hao Shih
发明人： Hang-Ting Lue , Yi-Hsuan Hsiao , Shih-Hung Chen , Yen-Hao Shih
IPC分类号： H01L29/788
CPC分类号： H01L22/12 , H01L22/20 , H01L27/11531 , H01L27/11556 , H01L27/11573 , H01L27/11582 , H01L29/0649
摘要： An integrated circuit device includes a substrate including a first region and a second region. A pit is formed in the first region. A stack of active layers alternating with insulating layers is deposited in the pit. The stack includes a particular insulating layer. The particular insulating layer has a first thickness, where a sum of the first thickness, thickness of active layers, and thicknesses of other insulating layers is essentially equal to a depth of the pit. The first thickness is different than the thicknesses of the other insulating layers by an amount within a range of process variations for the depth of the pit, for the thicknesses of the active layers, and for the thicknesses of other insulating layers. The device includes a planarized surface over the first and second regions, where an uppermost one of the active layers has a top surface below the planarized surface.
摘要翻译：集成电路器件包括包括第一区域和第二区域的衬底。在第一区域形成凹坑。与绝缘层交替的一叠有源层沉积在凹坑中。堆叠包括特定的绝缘层。特定绝缘层具有第一厚度，其中第一厚度，有源层的厚度和其它绝缘层的厚度之和基本上等于凹坑的深度。第一厚度不同于其它绝缘层的厚度，在凹坑的深度，有源层的厚度和其它绝缘层的厚度的工艺变化范围内的量。该装置包括在第一和第二区域之上的平坦化表面，其中最上面的一个活性层在平坦化表面下方具有顶表面。

3. 发明申请

US20130175598A1 Damascene Word Line 有权
标题翻译：大马士革字线
公开(公告)号：US20130175598A1
公开(公告)日：2013-07-11
申请号：US13347331
申请日：2012-01-10
申请人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
IPC分类号： H01L29/792 , H01L21/8239
CPC分类号： H01L27/11582 , H01L29/7926
摘要： The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Conductive lines such as silicon are formed over stacked nonvolatile memory structures. Word line trenches separate neighboring ones of the silicon lines. The silicon lines separated by the word line trenches are oxidized, making insulating surfaces in the word line trenches. Word lines are made in the word line trenches.
摘要翻译：该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。诸如硅的导电线形成在堆叠的非易失性存储器结构之上。字线沟槽分离出相邻的硅线。由字线沟槽分隔的硅线被氧化，在字线沟槽中形成绝缘表面。字线是在字线沟中制作的。

4. 发明授权

US09082656B2 NAND flash with non-trapping switch transistors 有权
标题翻译： NAND闪存与非陷阱开关晶体管
公开(公告)号：US09082656B2
公开(公告)日：2015-07-14
申请号：US13294852
申请日：2011-11-11
申请人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
IPC分类号： H01L27/115
CPC分类号： H01L27/1157 , H01L27/11578
摘要： A manufacturing method for a memory array includes first forming a multilayer stack of dielectric material on a plurality of semiconductor strips, and then exposing the multilayer stack in switch transistor regions. The multilayer stacks exposed in the switch transistor regions are processed to form gate dielectric structures that are different than the dielectric charge trapping structures. Word lines and select lines are then formed. A 3D array of dielectric charge trapping memory cells includes stacks of NAND strings of memory cells. A plurality of switch transistors are coupled to the NAND strings, the switch transistors including gate dielectric structures wherein the gate dielectric structures are different than the dielectric charge trapping structures.
摘要翻译：一种用于存储器阵列的制造方法包括首先在多个半导体条上形成多层电介质材料，然后在开关晶体管区域中暴露多层叠层。在开关晶体管区域中暴露的多层堆叠被处理以形成不同于介电电荷俘获结构的栅介质结构。然后形成字线和选择线。介质电荷俘获存储器单元的3D阵列包括存储器单元的NAND串的堆叠。多个开关晶体管耦合到NAND串，开关晶体管包括栅极电介质结构，其中栅极电介质结构不同于介电电荷俘获结构。

5. 发明授权

US08951862B2 Damascene word line 有权
标题翻译：大马士革字线
公开(公告)号：US08951862B2
公开(公告)日：2015-02-10
申请号：US13347331
申请日：2012-01-10
申请人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
IPC分类号： H01L21/336
CPC分类号： H01L27/11582 , H01L29/7926
摘要： The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Conductive lines such as silicon are formed over stacked nonvolatile memory structures. Word line trenches separate neighboring ones of the silicon lines. The silicon lines separated by the word line trenches are oxidized, making insulating surfaces in the word line trenches. Word lines are made in the word line trenches.
摘要翻译：该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。诸如硅的导电线形成在堆叠的非易失性存储器结构之上。字线沟槽分离出相邻的硅线。由字线沟槽分隔的硅线被氧化，在字线沟槽中形成绝缘表面。字线是在字线沟中制作的。

6. 发明申请

US20130334575A1 Damascene Word Line 有权
标题翻译：大马士革字线
公开(公告)号：US20130334575A1
公开(公告)日：2013-12-19
申请号：US13527259
申请日：2012-06-19
申请人： Shih-Hung Chen , Yen-Hao Shih , Hang-Ting Lue
发明人： Shih-Hung Chen , Yen-Hao Shih , Hang-Ting Lue
IPC分类号： H01L27/10 , H01L21/768
CPC分类号： H01L27/11578 , H01L27/11565
摘要： The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Partly oxidized lines of material such as silicon are made over a plurality of stacked nonvolatile memory structures. Word line trenches are made in the partly oxidized lines, by removing the unoxidized lines from the intermediate parts of the partly oxidized lines, leaving the plurality of oxidized lines at the outer parts of the plurality of partly oxidized lines. Word lines are made in the word line trenches over the plurality of stacked nonvolatile memory structures.
摘要翻译：该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。在多个堆叠的非易失性存储器结构上制造部分氧化的材料线如硅。通过从部分氧化的线的中间部分去除未氧化的线，在多个部分氧化的线的外部部分留下多条氧化线，在部分氧化的线中形成字线沟槽。在多个堆叠的非易失性存储器结构中的字线沟槽中形成字线。

7. 发明申请

US20130214340A1 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：其半导体结构及其制造方法
公开(公告)号：US20130214340A1
公开(公告)日：2013-08-22
申请号：US13401634
申请日：2012-02-21
申请人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
IPC分类号： H01L29/68 , H01L21/283
CPC分类号： H01L27/11524 , H01L27/11551 , H01L27/1157 , H01L27/11578 , H01L29/7881 , H01L29/792
摘要： A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first stacked structure, and a first conductive layer. The first stacked structure is formed on the substrate and includes a conductive structure and an insulating structure, and the conductive structure is disposed adjacent to the insulating structure. The first conductive layer is formed on the substrate and surrounds two side walls and a part of the top portion of the first stacked structure for exposing a portion of the first stacked structure.
摘要翻译：提供了一种半导体结构及其制造方法。半导体结构包括基板，第一堆叠结构和第一导电层。第一堆叠结构形成在基板上，并且包括导电结构和绝缘结构，并且导电结构邻近于绝缘结构设置。第一导电层形成在基板上并且包围第一层叠结构的两个侧壁和顶部的一部分，用于暴露第一堆叠结构的一部分。

8. 发明申请

US20140197516A1 INTEGRATION OF 3D STACKED IC DEVICE WITH PERIPHERAL CIRCUITS 有权
标题翻译： 3D堆叠IC器件与外围电路的集成
公开(公告)号：US20140197516A1
公开(公告)日：2014-07-17
申请号：US13739914
申请日：2013-01-11
申请人： Hang-Ting Lue , Yi-Hsuan Hsiao , Shih-Hung Chen , Yen-Hao Shih
发明人： Hang-Ting Lue , Yi-Hsuan Hsiao , Shih-Hung Chen , Yen-Hao Shih
IPC分类号： H01L21/66 , H01L29/06
CPC分类号： H01L22/12 , H01L22/20 , H01L27/11531 , H01L27/11556 , H01L27/11573 , H01L27/11582 , H01L29/0649
摘要： An integrated circuit device includes a substrate including a first region and a second region. A pit is formed in the first region. A stack of active layers alternating with insulating layers is deposited in the pit. The stack includes a particular insulating layer. The particular insulating layer has a first thickness, where a sum of the first thickness, thickness of active layers, and thicknesses of other insulating layers is essentially equal to a depth of the pit. The first thickness is different than the thicknesses of the other insulating layers by an amount within a range of process variations for the depth of the pit, for the thicknesses of the active layers, and for the thicknesses of other insulating layers. The device includes a planarized surface over the first and second regions, where an uppermost one of the active layers has a top surface below the planarized surface.
摘要翻译：集成电路器件包括包括第一区域和第二区域的衬底。在第一区域形成凹坑。与绝缘层交替的一叠有源层沉积在凹坑中。堆叠包括特定的绝缘层。特定绝缘层具有第一厚度，其中第一厚度，有源层的厚度和其它绝缘层的厚度之和基本上等于凹坑的深度。第一厚度不同于其它绝缘层的厚度，在凹坑的深度，有源层的厚度和其它绝缘层的厚度的工艺变化范围内的量。该装置包括在第一和第二区域之上的平坦化表面，其中最上面的一个活性层在平坦化表面下方具有顶表面。

9. 发明申请

US20130119455A1 NAND FLASH WITH NON-TRAPPING SWITCH TRANSISTORS 有权
标题翻译：具有非捕获开关晶体管的NAND闪存
公开(公告)号：US20130119455A1
公开(公告)日：2013-05-16
申请号：US13294852
申请日：2011-11-11
申请人： SHIH-HUNG CHEN , Hang-Ting Lue , Yen-Hao Shih
发明人： SHIH-HUNG CHEN , Hang-Ting Lue , Yen-Hao Shih
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/1157 , H01L27/11578
摘要： A manufacturing method for a memory array includes first forming a multilayer stack of dielectric material on a plurality of semiconductor strips, and then exposing the multilayer stack in switch transistor regions. The multilayer stacks exposed in the switch transistor regions are processed to form gate dielectric structures that are different than the dielectric charge trapping structures. Word lines and select lines are then formed. A 3D array of dielectric charge trapping memory cells includes stacks of NAND strings of memory cells. A plurality of switch transistors are coupled to the NAND strings, the switch transistors including gate dielectric structures wherein the gate dielectric structures are different than the dielectric charge trapping structures.
摘要翻译：一种用于存储器阵列的制造方法包括首先在多个半导体条上形成多层电介质材料，然后在开关晶体管区域中暴露多层叠层。在开关晶体管区域中暴露的多层堆叠被处理以形成不同于介电电荷俘获结构的栅介质结构。然后形成字线和选择线。介质电荷俘获存储器单元的3D阵列包括存储器单元的NAND串的堆叠。多个开关晶体管耦合到NAND串，开关晶体管包括栅极电介质结构，其中栅极电介质结构不同于介电电荷俘获结构。

10. 发明授权

US09035369B2 Semiconductor structure and manufacturing method of the same 有权
标题翻译：半导体结构及其制造方法相同
公开(公告)号：US09035369B2
公开(公告)日：2015-05-19
申请号：US13401634
申请日：2012-02-21
申请人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
IPC分类号： H01L29/68 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11524 , H01L27/11551 , H01L27/1157 , H01L27/11578 , H01L29/7881 , H01L29/792
摘要： A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first stacked structure, and a first conductive layer. The first stacked structure is formed on the substrate and includes a conductive structure and an insulating structure, and the conductive structure is disposed adjacent to the insulating structure. The first conductive layer is formed on the substrate and surrounds two side walls and a part of the top portion of the first stacked structure for exposing a portion of the first stacked structure.
摘要翻译：提供了一种半导体结构及其制造方法。半导体结构包括基板，第一堆叠结构和第一导电层。第一堆叠结构形成在基板上，并且包括导电结构和绝缘结构，并且导电结构邻近于绝缘结构设置。第一导电层形成在基板上并且包围第一层叠结构的两个侧壁和顶部的一部分，用于暴露第一堆叠结构的一部分。

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