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1. 发明授权

US08211806B2 Method of fabricating integrated circuit with small pitch 有权
标题翻译：制造小间距集成电路的方法
公开(公告)号：US08211806B2
公开(公告)日：2012-07-03
申请号：US11846900
申请日：2007-08-29
申请人： Chia-Wei Wu , Ling-Wu Yang
发明人： Chia-Wei Wu , Ling-Wu Yang
IPC分类号： H01L21/302
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： A method of manufacturing an integrated circuit with a small pitch comprises providing a second material layer patterned to form at least two features with an opening between the features. The second material layer is formed over a first material layer and the first material layer is over a substrate. The method also comprises providing a first oxide layer to form a first sidewall surrounding each of the features, and providing a second oxide layer over the first sidewalls and the first material layer. A second sidewall is formed surrounding each of the features. The method further comprises providing a conductive layer over the second oxide layer and removing the conductive layer, the second sidewalls and the first material underneath the second sidewalls.
摘要翻译：制造具有小间距的集成电路的方法包括提供图案化以形成具有特征之间的开口的至少两个特征的第二材料层。第二材料层形成在第一材料层上并且第一材料层在衬底之上。该方法还包括提供第一氧化物层以形成围绕每个特征的第一侧壁，以及在第一侧壁和第一材料层之上提供第二氧化物层。形成围绕每个特征的第二侧壁。该方法还包括在第二氧化物层上提供导电层，并移除第二侧壁下方的导电层，第二侧壁和第一材料。

2. 发明申请

US20110012192A1 Vertical Channel Transistor Structure and Manufacturing Method Thereof 审中-公开
标题翻译：垂直沟道晶体管的结构及制造方法
公开(公告)号：US20110012192A1
公开(公告)日：2011-01-20
申请号：US12892044
申请日：2010-09-28
申请人： Tzu-Hsuan Hsu , Yen-Hao Shih , Chia-Wei Wu
发明人： Tzu-Hsuan Hsu , Yen-Hao Shih , Chia-Wei Wu
IPC分类号： H01L29/78
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/42352
摘要： A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate.
摘要翻译：提供了垂直沟道晶体管结构。该结构包括基板，通道，盖层，电荷捕获层，源极和漏极。通道形成为从基板突出的鳍状结构。盖层沉积在鳍状结构上。盖层和鳍状结构具有基本上相同的宽度。电荷俘获层沉积在盖层上和鳍状结构的两个垂直表面上。栅极沉积在电荷捕获层上并在鳍状结构的两个垂直表面上沉积。源极和漏极分别位于鳍状结构的两侧并与栅极相对。

3. 发明授权

US07811890B2 Vertical channel transistor structure and manufacturing method thereof 有权
标题翻译：垂直沟道晶体管结构及其制造方法
公开(公告)号：US07811890B2
公开(公告)日：2010-10-12
申请号：US11545575
申请日：2006-10-11
申请人： Tzu-Hsuan Hsu , Yen-Hao Shih , Chia-Wei Wu
发明人： Tzu-Hsuan Hsu , Yen-Hao Shih , Chia-Wei Wu
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/42352
摘要： A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate.
摘要翻译：提供了垂直沟道晶体管结构。该结构包括基板，通道，盖层，电荷捕获层，源极和漏极。通道形成为从基板突出的鳍状结构。盖层沉积在鳍状结构上。盖层和鳍状结构具有基本上相同的宽度。电荷俘获层沉积在盖层上和鳍状结构的两个垂直表面上。栅极沉积在电荷捕获层上并在鳍状结构的两个垂直表面上沉积。源极和漏极分别位于鳍状结构的两侧并与栅极相对。

4. 发明授权

US07795891B2 Tester with low signal attenuation 有权
标题翻译：测试仪具有低信号衰减
公开(公告)号：US07795891B2
公开(公告)日：2010-09-14
申请号：US12534868
申请日：2009-08-04
申请人： Chia-Wei Wu
发明人： Chia-Wei Wu
IPC分类号： G01R31/02
CPC分类号： G01R1/06772 , G01R1/06727 , G01R1/06733
摘要： A tester with low signal attenuation and suitable for measuring an electrical characteristic of a subject to be tested includes a circuit board and a first probe. The circuit board has a first surface and a second surface respectively having a first signal transmission line and a second signal transmission line. The first probe has a contact end contacting the subject to be tested and a first signal end and a second signal end respectively connecting the first signal transmission line and the second signal transmission line. The first probe receives a testing signal from the first signal transmission line through the first signal end and transmits the testing signal from the contact end to the subject to be tested, such that the subject to be tested generates a response signal, and the first probe transmits the response signal to the second signal transmission line through the second signal end.
摘要翻译：具有低信号衰减并且适于测量待测试对象的电特性的测试仪包括电路板和第一探针。电路板具有分别具有第一信号传输线和第二信号传输线的第一表面和第二表面。第一探针具有接触端接触被测试对象和分别连接第一信号传输线和第二信号传输线的第一信号端和第二信号端。第一探测器通过第一信号端接收来自第一信号传输线的测试信号，并将测试信号从接触端传送到要测试的对象，使得被测试对象产生响应信号，并且第一探针通过第二信号端将响应信号发送到第二信号传输线。

5. 发明授权

US07776713B2 Etching solution, method of surface modification of semiconductor substrate and method of forming shallow trench isolation 有权
标题翻译：蚀刻溶液，半导体衬底的表面改性方法和形成浅沟槽隔离的方法
公开(公告)号：US07776713B2
公开(公告)日：2010-08-17
申请号：US11806186
申请日：2007-05-30
申请人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wu Yang
发明人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wu Yang
IPC分类号： H01L21/465
CPC分类号： H01L21/30604 , C09K13/08 , H01L21/30608 , H01L21/76232
摘要： An etching solution, a method of surface modification of a semiconductor substrate and a method of forming shallow trench isolation are provided. The etching solution is used for surface modifying the semiconductor substrate. The etching solution includes an oxidant and an oxide remover. The semiconductor substrate is oxidized to a semiconductor oxide by the oxidant, and the oxide remover subtracts the semiconductor oxide.
摘要翻译：提供蚀刻溶液，半导体衬底的表面改性方法和形成浅沟槽隔离的方法。蚀刻溶液用于表面改性半导体衬底。蚀刻溶液包括氧化剂和氧化物去除剂。半导体衬底被氧化剂氧化成半导体氧化物，并且氧化物去除器减去半导体氧化物。

6. 发明申请

US20090289649A1 TESTER WITH LOW SIGNAL ATTENUATION 有权
标题翻译：具有低信号衰减的测试仪
公开(公告)号：US20090289649A1
公开(公告)日：2009-11-26
申请号：US12534868
申请日：2009-08-04
申请人： Chia-Wei Wu
发明人： Chia-Wei Wu
IPC分类号： G01R31/26 , G01R31/02
CPC分类号： G01R1/06772 , G01R1/06727 , G01R1/06733
摘要： A tester with low signal attenuation and suitable for measuring an electrical characteristic of a subject to be tested includes a circuit board and a first probe. The circuit board has a first surface and a second surface respectively having a first signal transmission line and a second signal transmission line. The first probe has a contact end contacting the subject to be tested and a first signal end and a second signal end respectively connecting the first signal transmission line and the second signal transmission line. The first probe receives a testing signal from the first signal transmission line through the first signal end and transmits the testing signal from the contact end to the subject to be tested, such that the subject to be tested generates a response signal, and the first probe transmits the response signal to the second signal transmission line through the second signal end.
摘要翻译：具有低信号衰减并且适于测量待测试对象的电特性的测试仪包括电路板和第一探针。电路板具有分别具有第一信号传输线和第二信号传输线的第一表面和第二表面。第一探针具有接触端接触被测试对象和分别连接第一信号传输线和第二信号传输线的第一信号端和第二信号端。第一探测器通过第一信号端接收来自第一信号传输线的测试信号，并将测试信号从接触端传送到要测试的对象，使得被测试对象产生响应信号，并且第一探针通过第二信号端将响应信号发送到第二信号传输线。

7. 发明申请

US20090091983A1 NON-VOLATILE MEMORY STRUCTURE AND ARRAY THEREOF 有权
标题翻译：非易失性存储器结构及其阵列
公开(公告)号：US20090091983A1
公开(公告)日：2009-04-09
申请号：US11866756
申请日：2007-10-03
申请人： Shaw-Hung Ku , Shih-Chin Lee , Chia-Wei Wu , Shang-Wei Lin , Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu
发明人： Shaw-Hung Ku , Shih-Chin Lee , Chia-Wei Wu , Shang-Wei Lin , Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , H01L27/11521
摘要： A non-volatile memory structure including a substrate, stacked patterns and stress patterns is provided. The stacked patterns are disposed on the substrate. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top. Here, the charge storage structure at least includes a charge storage layer. The stress patterns are disposed on the substrate between the two adjacent stacked patterns, respectively.
摘要翻译：提供了包括基板，堆叠图案和应力图案的非易失性存储器结构。层叠图案设置在基板上。每个堆叠图案包括电荷存储结构和从底部到顶部的栅极。这里，电荷存储结构至少包括电荷存储层。应力图案分别设置在两个相邻堆叠图案之间的基板上。

8. 发明申请

US20070287260A1 METHODS FOR FORMING AN ISOLATION STRUCTURE IN A SILICON SUBSTRATE 有权
标题翻译：在硅衬底中形成隔离结构的方法
公开(公告)号：US20070287260A1
公开(公告)日：2007-12-13
申请号：US11423859
申请日：2006-06-13
申请人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wuu Yang
发明人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wuu Yang
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： A process for forming STI regions comprises performing an In Situ Steam Generation (ISSG) radical conversion on a SiN liner layer within an STI trench in order to expose the top corner of the trench and simultaneously cause rounding the top corner of a liner oxide layer within the trench. The rounding of the liner oxide layer can prevent thinning of a subsequently formed gate oxide.
摘要翻译：用于形成STI区域的方法包括在STI沟槽内的SiN衬垫层上进行原位蒸汽发生（ISSG）自由基转化，以暴露沟槽的顶角，并且同时引起衬里氧化物层的顶角四周沟渠。衬垫氧化物层的四舍五入可防止随后形成的栅极氧化物的变薄。

9. 发明申请

US20050139525A1 Chip sorting apparatus and method for fabricating the same 审中-公开
标题翻译：芯片分选装置及其制造方法
公开(公告)号：US20050139525A1
公开(公告)日：2005-06-30
申请号：US10722507
申请日：2003-11-28
申请人： Tung-Hung Tsai , Shyang-Li Wang , Chia-Wei Wu , Jhih-Jhong Huang
发明人： Tung-Hung Tsai , Shyang-Li Wang , Chia-Wei Wu , Jhih-Jhong Huang
IPC分类号： B07C5/344 , B07C5/00
CPC分类号： B07C5/344
摘要： A chip sorting apparatus and a method for fabricating the same are applicable to the chip pick-up sorting process after chip formation. By using the chip sorting apparatus and the method for fabricating the same in the chip pick-up process, it can directly inspect the chip without multiple chip movements for implementing the chip inspection. The chip sorting apparatus and the method for fabricating the same use a positioning axis to directly process inspection on the chip before picking up the chip. This, therefore, can avoid the complicated process causing from multiple chip pick-up positions. Further, it can enhance the chip pick-up efficiency.
摘要翻译：芯片分选装置及其制造方法适用于芯片形成后的芯片拾取分拣处理。通过在芯片拾取过程中使用芯片分选装置及其制造方法，可以直接检查芯片而不需要多个芯片移动来实现芯片检查。芯片分选装置及其制造方法使用定位轴来直接处理在拾取芯片之前的芯片上的检查。因此，可以避免由多个芯片拾取位置引起的复杂过程。此外，它可以提高芯片拾取效率。

10. 发明授权

US07889556B2 Flash memory having insulating liners between source/drain lines and channels 有权
标题翻译：闪存在源极/漏极线和通道之间具有绝缘衬垫
公开(公告)号：US07889556B2
公开(公告)日：2011-02-15
申请号：US12690582
申请日：2010-01-20
申请人： Shaw Hung Ku , Ten Hao Yeh , Shih Chin Lee , Shang Wei Lin , Chia Wei Wu , Tzung Ting Han , Ming Shang Chen , Wenpin Lu
发明人： Shaw Hung Ku , Ten Hao Yeh , Shih Chin Lee , Shang Wei Lin , Chia Wei Wu , Tzung Ting Han , Ming Shang Chen , Wenpin Lu
IPC分类号： G11C16/00
CPC分类号： H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.
摘要翻译：存储器阵列包括具有大致平行对准的多个沟槽的半导体本体。沟槽包含诸如掺杂非晶硅的半导体材料，并且用作存储器阵列的源极/漏极线。绝缘衬垫位于沟槽内的半导体材料和半导体本体之间。多个字线以交叉点的阵列覆盖半导体本体中的多个沟槽和沟道区域。电荷捕获结构位于字线和交叉点处的通道区之间，提供闪存单元阵列。电荷捕获结构包括适于编程和擦除以存储数据的介电电荷俘获结构。制造这种器件的方法包括在通道区域上形成电荷俘获结构之前，利用绝缘衬垫图案化和形成源极/漏极线。

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