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1. 发明授权

US08437192B2 3D two bit-per-cell NAND flash memory 有权
标题翻译： 3D双比特单元NAND闪存
公开(公告)号：US08437192B2
公开(公告)日：2013-05-07
申请号：US12785291
申请日：2010-05-21
申请人： Hsiang-Lan Lung , Hang-Ting Lue , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee , Tien-Yen Wang
发明人： Hsiang-Lan Lung , Hang-Ting Lue , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee , Tien-Yen Wang
IPC分类号： G11C16/00 , G11C16/02 , G11C16/04 , G11C5/02 , G11C5/06
CPC分类号： H01L27/11578 , G11C16/0483 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： A 3D memory device includes bottom and top memory cubes having respective arrays of vertical NAND string structures. A common source plane comprising a layer of conductive material is between the top and bottom memory cubes. The source plane is supplied a bias voltage such as ground, and is selectively coupled to an end of the vertical NAND string structures of the bottom and top memory cubes. Memory cells in a particular memory cube are read using current through the particular vertical NAND string between the source plane and a corresponding bit line coupled to another end of the particular vertical NAND string.
摘要翻译： 3D存储器件包括具有垂直NAND串结构的相应阵列的底部和顶部存储立方体。包括导电材料层的共同源平面位于顶部和底部存储立方体之间。源平面被提供诸如地的偏置电压，并且选择性地耦合到底部和顶部存储立方体的垂直NAND串结构的一端。通过源平面与耦合到特定垂直NAND串的另一端的对应位线之间的特定垂直NAND串的电流来读取特定存储器立方体中的存储单元。

2. 发明授权

US08374019B2 Phase change memory with fast write characteristics 有权
标题翻译：具有快速写入特性的相变存储器
公开(公告)号：US08374019B2
公开(公告)日：2013-02-12
申请号：US12985253
申请日：2011-01-05
申请人： Chao-I Wu , Yen-Hao Shih , Ming-Hsiu Lee
发明人： Chao-I Wu , Yen-Hao Shih , Ming-Hsiu Lee
IPC分类号： G11C11/00
CPC分类号： H01L45/06 , G11C11/005 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C14/00 , G11C2013/0083 , G11C2013/0092 , H01L27/2463 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1641
摘要： A memory device including programmable resistance memory cells, including electrically pre-stressed target memory cells. The pre-stressed target memory cells have one of a lower voltage transition threshold, a shorter duration set interval and a longer reset state retention characteristic. Biasing circuitry is included on the device configured to control the pre-stressing operations, and to apply read, set and reset operations that can be modified for the pre-stressed memory cells.
摘要翻译：一种包括可编程电阻存储单元的存储器件，包括电预应力目标存储单元。预应力目标存储单元具有较低电压转变阈值，较短持续时间设定间隔和较长复位状态保持特性之一。设备上包括偏置电路，用于控制预应力操作，以及应用对预应力存储单元进行修改的读取，置位和复位操作。

3. 发明授权

US07911856B2 Three-dimensional memory devices and methods of manufacturing and operating the same 有权
标题翻译：三维存储器件及其制造和操作方法
公开(公告)号：US07911856B2
公开(公告)日：2011-03-22
申请号：US12471411
申请日：2009-05-25
申请人： Ming-Hsiu Lee , Yen-Hao Shih
发明人： Ming-Hsiu Lee , Yen-Hao Shih
IPC分类号： G11C7/00
CPC分类号： G11C13/0023 , G11C13/00 , G11C13/0004 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L21/84 , H01L27/0688 , H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/1203 , H01L29/66833 , H01L29/792
摘要： A method of accessing memory cells is disclosed. A first signal is sent to at least one layer select transistor. The at least one layer select transistor is activated based on the first signal. Signals are communicated to or from one or more memory cells based on the activated at least layer select transistor.
摘要翻译：公开了访问存储器单元的方法。第一信号被发送到至少一个层选择晶体管。基于第一信号激活至少一个层选择晶体管。基于激活的至少层选择晶体管将信号传送到或来自一个或多个存储器单元。

4. 发明申请

US20060284243A1 Electrically erasable programmable read only memory (EEPROM) cell and method for making the same 有权
标题翻译：电可擦除可编程只读存储器（EEPROM）单元及其制作方法
公开(公告)号：US20060284243A1
公开(公告)日：2006-12-21
申请号：US11146777
申请日：2005-06-06
申请人： Tzu-Hsuan Hsu , Yen-Hao Shih , Ming-Hsiu Lee
发明人： Tzu-Hsuan Hsu , Yen-Hao Shih , Ming-Hsiu Lee
IPC分类号： H01L29/792
CPC分类号： H01L29/7885 , H01L29/7887 , H01L29/7923 , Y10S257/90
摘要： An asymmetrically doped memory cell has first and second N+ doped junctions on a P substrate. A composite charge trapping layer is disposed over the P substrate and between the first and the second N+ doped junctions. A N− doped region is positioned adjacent to the first N+ doped junction and under the composite charge trapping layer. A P− doped region is positioned adjacent to the second N+ doped junction and under the composite charge trapping layer. The asymmetrically doped memory cell will store charges at the end of the composite charge trapping layer that is above the P− doped region. The asymmetrically doped memory cell can function as an electrically erasable programmable read only memory cell, and is capable of multiple level cell operations. A method for making an asymmetrically doped memory cell is also described.
摘要翻译：不对称掺杂的存储单元在P衬底上具有第一和第二N +掺杂结。复合电荷捕获层设置在P衬底上并且在第一和第二N +掺杂结之间。 N掺杂区域邻近第一N +掺杂结并位于复合电荷俘获层下方。 P-掺杂区域邻近第二N +掺杂结并位于复合电荷俘获层下方。非对称掺杂的存储单元将在复合电荷捕获层的末端在P掺杂区域之上存储电荷。非对称掺杂的存储单元可以用作电可擦除可编程只读存储器单元，并且能够进行多级单元操作。还描述了制造非对称掺杂的存储单元的方法。

5. 发明授权

US08363463B2 Phase change memory having one or more non-constant doping profiles 有权
标题翻译：具有一个或多个非恒定掺杂分布的相变存储器
公开(公告)号：US08363463B2
公开(公告)日：2013-01-29
申请号：US12729837
申请日：2010-03-23
申请人： Yen-Hao Shih , Huai-Yu Cheng , Chieh-Fang Chen , Chao-I Wu , Ming Hsiu Lee , Hsiang-Lan Lung , Matthew J. Breitwisch , Simone Raoux , Chung H Lam
发明人： Yen-Hao Shih , Huai-Yu Cheng , Chieh-Fang Chen , Chao-I Wu , Ming Hsiu Lee , Hsiang-Lan Lung , Matthew J. Breitwisch , Simone Raoux , Chung H Lam
IPC分类号： G11C11/00
CPC分类号： H01L45/1625 , G11C13/0004 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/144 , H01L45/1641
摘要： A phase change memory device with a memory element including a basis phase change material, such as a chalcogenide, and one or more additives, where the additive or additives have a non-constant concentration profile along an inter-electrode current path through a memory element. The use of “non-constant” concentration profiles for additives enables doping the different zones with different materials and concentrations, according to the different crystallographic, thermal and electrical conditions, and different phase transition conditions.
摘要翻译：一种具有存储元件的相变存储器件，该存储元件包括诸如硫族化物的基本相变材料和一种或多种添加剂，其中所述添加剂或添加剂沿着穿过存储元件的电极间电流路径具有非恒定浓度分布。根据不同的晶体学，热学和电学条件以及不同的相变条件，使用非恒定浓度分布的添加剂可以使用不同的材料和浓度掺杂不同的区域。

6. 发明授权

US08324605B2 Dielectric mesh isolated phase change structure for phase change memory 有权
标题翻译：介质网隔离相变结构相变记忆
公开(公告)号：US08324605B2
公开(公告)日：2012-12-04
申请号：US12286874
申请日：2008-10-02
申请人： Hsiang-Lan Lung , Chieh-Fang Chen , Yen-Hao Shih , Ming-Hsiu Lee , Matthew J. Breitwisch , Chung Hon Lam , Frieder H. Baumann , Philip Flaitz , Simone Raoux
发明人： Hsiang-Lan Lung , Chieh-Fang Chen , Yen-Hao Shih , Ming-Hsiu Lee , Matthew J. Breitwisch , Chung Hon Lam , Frieder H. Baumann , Philip Flaitz , Simone Raoux
IPC分类号： H01L47/00 , H01L21/06
CPC分类号： H01L45/1226 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/1625 , H01L45/1641
摘要： A method for manufacturing a memory device, and a resulting device, is described using silicon oxide doped chalcogenide material. A first electrode having a contact surface; a body of phase change memory material in a polycrystalline state including a portion in contact with the contact surface of the first electrode, and a second electrode in contact with the body of phase change material are formed. The process includes melting and cooling the phase change memory material one or more times within an active region in the body of phase change material without disturbing the polycrystalline state outside the active region. A mesh of silicon oxide in the active region with at least one domain of chalcogenide material results. Also, the grain size of the phase change material in the polycrystalline state outside the active region is small, resulting in a more uniform structure.
摘要翻译：使用氧化硅掺杂的硫族化物材料来描述用于制造存储器件的方法和所得到的器件。具有接触表面的第一电极; 形成包括与第一电极的接触表面接触的部分的多晶状态的相变记忆材料体以及与相变材料体接触的第二电极。该方法包括在相变材料体内的有源区内熔化和冷却相变存储材料一次或多次，而不会干扰有源区外的多晶态。导致活性区域中的氧化硅网格与至少一个硫族化物材料结构域形成。此外，活性区域外的多晶态的相变材料的晶粒尺寸小，结果更均匀。

7. 发明申请

US20110317480A1 PHASE CHANGE MEMORY CODING 有权
标题翻译：相变存储器编码
公开(公告)号：US20110317480A1
公开(公告)日：2011-12-29
申请号：US12823508
申请日：2010-06-25
申请人： HSIANG-LAN LUNG , Ming Hsiu Lee , Yen-Hao Shih , Tien-Yen Wang , Chao-I Wu
发明人： HSIANG-LAN LUNG , Ming Hsiu Lee , Yen-Hao Shih , Tien-Yen Wang , Chao-I Wu
IPC分类号： G11C11/00 , H01L21/06
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/004 , G11C13/0069 , G11C2013/0092
摘要： An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit.
摘要翻译：集成电路相变存储器可以通过在一些单元和存储器中引起第一电阻状态以及存储器中的第二电阻状态以及存储器中的一些其他单元来表示数据集而被预编码。在对数据集进行编码之后，将集成电路相变存储器安装在基板上。在安装集成电路相变存储器之后，通过感测第一和第二电阻状态以及将第一电阻状态下的单元改变为第三电阻状态并将第二电阻状态的单元改变为第四电阻状态来读取数据组。第一和第二电阻状态在焊接或其他热循环过程之后保持感测裕度。第三和第四电阻状态的特征在于能够使用更高速度和更低功率的转换，适用于电路的任务功能。

8. 发明申请

US20100084624A1 Dielectric mesh isolated phase change structure for phase change memory 有权
标题翻译：介质网隔离相变结构相变记忆
公开(公告)号：US20100084624A1
公开(公告)日：2010-04-08
申请号：US12286874
申请日：2008-10-02
申请人： Hsiang-Lan Lung , Chieh Fang Chen , Yen-Hao Shih , Ming Hsiu Lee , Matthew J. Breitwisch , Chung Hon Lam , Frieder H. Baumann , Philip Flaitz , Simone Raoux
发明人： Hsiang-Lan Lung , Chieh Fang Chen , Yen-Hao Shih , Ming Hsiu Lee , Matthew J. Breitwisch , Chung Hon Lam , Frieder H. Baumann , Philip Flaitz , Simone Raoux
IPC分类号： H01L47/00 , H01L21/06
CPC分类号： H01L45/1226 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/1625 , H01L45/1641
摘要： A method for manufacturing a memory device, and a resulting device, is described using silicon oxide doped chalcogenide material. A first electrode having a contact surface; a body of phase change memory material in a polycrystalline state including a portion in contact with the contact surface of the first electrode, and a second electrode in contact with the body of phase change material are formed. The process includes melting and cooling the phase change memory material one or more times within an active region in the body of phase change material without disturbing the polycrystalline state outside the active region. A mesh of silicon oxide in the active region with at least one domain of chalcogenide material results. Also, the grain size of the phase change material in the polycrystalline state outside the active region is small, resulting in a more uniform structure.
摘要翻译：使用氧化硅掺杂的硫族化物材料来描述用于制造存储器件的方法和所得到的器件。具有接触表面的第一电极; 形成包括与第一电极的接触表面接触的部分的多晶状态的相变记忆材料体以及与相变材料体接触的第二电极。该方法包括在相变材料体内的有源区内熔化和冷却相变存储材料一次或多次，而不会干扰有源区外的多晶态。导致活性区域中的氧化硅网格与至少一个硫族化物材料结构域形成。此外，活性区域外的多晶态的相变材料的晶粒尺寸小，结果更均匀。

9. 发明授权

US09019771B2 Dielectric charge trapping memory cells with redundancy 有权
标题翻译：介质电荷捕获具有冗余的存储单元
公开(公告)号：US09019771B2
公开(公告)日：2015-04-28
申请号：US13661723
申请日：2012-10-26
申请人： Hsiang-Lan Lung , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee
发明人： Hsiang-Lan Lung , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee
IPC分类号： G11C16/06 , G11C16/04 , G11C16/10
CPC分类号： G11C16/0475 , G11C16/10
摘要： A memory cell array of dielectric charge trapping memory cells and method for performing program, read and erase operations on the memory cell array that includes bits stored at charge trapping sites in adjacent memory cells. A bit of information is stored at a first charge trapping site in a first memory cell and a second charge trapping site in a second adjacent memory cell. Storing charge at two trapping sites in adjacent memory cells increases data retention rates of the array of memory cells as each charge trapping site can be read to represent the data that is stored at the data site. Each corresponding charge trapping site can be read independently and in parallel so that the results can be compared to determine the data value that is stored at the data site in an array of dielectric charge trapping memory cells.
摘要翻译：介质电荷俘获存储器单元的存储单元阵列和用于对存储在相邻存储器单元中的电荷俘获位置处存储的位的存储单元阵列执行编程，读取和擦除操作的方法。一些信息存储在第一存储单元中的第一电荷捕获位点和第二相邻存储单元中的第二电荷捕获位点。在相邻存储器单元中的两个捕获位置处存储电荷增加了存储器单元阵列的数据保留率，因为可以读取每个电荷捕获位点以表示存储在数据站点的数据。可以独立地并行地读取每个对应的电荷俘获位点，以便比较结果以确定存储在介电电荷俘获存储器单元阵列中的数据位置处的数据值。

10. 发明授权

US08634235B2 Phase change memory coding 有权
标题翻译：相变存储器编码
公开(公告)号：US08634235B2
公开(公告)日：2014-01-21
申请号：US12823508
申请日：2010-06-25
申请人： Hsiang-Lan Lung , Ming Hsiu Lee , Yen-Hao Shih , Tien-Yen Wang , Chao-I Wu
发明人： Hsiang-Lan Lung , Ming Hsiu Lee , Yen-Hao Shih , Tien-Yen Wang , Chao-I Wu
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/004 , G11C13/0069 , G11C2013/0092
摘要： An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit.
摘要翻译：集成电路相变存储器可以通过在一些单元和存储器中引起第一电阻状态以及存储器中的第二电阻状态以及存储器中的一些其他单元来表示数据集而被预编码。在对数据集进行编码之后，将集成电路相变存储器安装在基板上。在安装集成电路相变存储器之后，通过感测第一和第二电阻状态以及将第一电阻状态下的单元改变为第三电阻状态并将第二电阻状态的单元改变为第四电阻状态来读取数据组。第一和第二电阻状态在焊接或其他热循环过程之后保持感测裕度。第三和第四电阻状态的特征在于能够使用更高速度和更低功率的转换，适用于电路的任务功能。

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