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1. 发明授权

US5029323A Semiconductor device 失效
公开(公告)号：US5029323A
公开(公告)日：1991-07-02
申请号：US399952
申请日：1989-08-29
申请人： Shinji Nakazato , Hideaki Uchida , Nobuo Tanba , Nobuyuki Gotoo , Kazunori Onozawa , Atsushi Hiraishi
发明人： Shinji Nakazato , Hideaki Uchida , Nobuo Tanba , Nobuyuki Gotoo , Kazunori Onozawa , Atsushi Hiraishi
IPC分类号： H01L27/082 , H01L21/331 , H01L21/8222 , H01L21/8249 , H01L27/06 , H01L27/10 , H01L29/73 , H01L29/732
CPC分类号： H01L27/0623 , Y10S257/903
摘要： A semiconductor device facilitates keeping all parasitic resistance values between contact portion of a common source (V.sub.cc) line and intrinsic collector operation regions of respective transistors small enough so as not to exceed predetermined values and so as to be nearly identical. The parasitic resistance values are made small and nearly identical by disposing collector electrode connecting layers between base impurity introducing layers of respective transistors provided with predetermined intervals in a semiconductor substrate. Because of this arrangement to minimize and equalize resistances, the voltage drops generated by the parasitic resistances applied to respective transistors are suppressed so as to be lower than or not substantially exceed the operation threshold voltages of the parasitic transistors.

2. 发明授权

US4748487A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4748487A
公开(公告)日：1988-05-31
申请号：US053479
申请日：1987-05-26
申请人： Hideaki Uchida , Kinya Mitsumoto , Yoshiaki Yazawa , Shinji Nakazato , Masanori Odaka
发明人： Hideaki Uchida , Kinya Mitsumoto , Yoshiaki Yazawa , Shinji Nakazato , Masanori Odaka
IPC分类号： H01L21/8238 , G11C11/34 , G11C11/419 , H01L21/8234 , H01L21/8244 , H01L27/088 , H01L27/092 , H01L27/10 , H01L27/11 , H01L27/02
CPC分类号： G11C11/419 , H01L27/11
摘要： A semiconductor memory device wherein the equivalent series resistances that are interposed in series in the pairs of complementary data lines D, D, are substantially the same as one another among the individual complementary data lines D, D. The equivalent series resistance is comprised of pull-up MISFET's and column switching MISFET's that exist between the power source V.sub.CC and the sense circuit. Parity is maintained for the pull-up MISFET's (Q.sub.p, Q.sub.p) and the column switching MISFET's (Q.sub.y, Q.sub.y) that exist on the pairs of complementary data lines D, D. To maintain this parity, the two MISFET's are formed to have the same shape. In addition, the arrangement of contacts to the transistors are set so that the directions in which the currents flow and lengths of current paths are also the same. In other words, contact portions between aluminum electrode and source and drain regions are formed at the same positions in the two MISFET's.
摘要翻译：一种半导体存储器件，其中在互补数据线对D，＆amp; D和D中的串联插入的等效串联电阻在各个互补数据线D，＆amp; L和D之间彼此基本相同。等效串联电阻包括上拉MISFET和列切换MISFET存在于电源VCC和感测电路之间。维持上拉MISFET（Qp，Qp）和在互补数据线D和上拉和下降D上存在的列切换MISFET（Qy，Qy）的奇偶校验。为了保持这个奇偶校验，两个MISFET的形成是相同的形状。此外，设置与晶体管的接触的布置，使得电流流动的方向和电流路径的长度也相同。换句话说，铝电极和源极和漏极区域之间的接触部分形成在两个MISFET的相同位置处。

3. 发明授权

US07808107B2 Semiconductor integrated circuit device 有权
公开(公告)号：US07808107B2
公开(公告)日：2010-10-05
申请号：US12453383
申请日：2009-05-08
申请人： Masao Shinozaki , Kenji Nishimoto , Takashi Akioka , Yutaka Kohara , Sanae Asari , Shusaku Miyata , Shinji Nakazato
发明人： Masao Shinozaki , Kenji Nishimoto , Takashi Akioka , Yutaka Kohara , Sanae Asari , Shusaku Miyata , Shinji Nakazato
IPC分类号： H01L23/48
CPC分类号： H01L23/5286 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05671 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/12044 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00014 , H01L2924/013 , H01L2924/01027
摘要： Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.

4. 发明授权

US06740958B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06740958B2
公开(公告)日：2004-05-25
申请号：US10115101
申请日：2002-04-04
申请人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
发明人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
IPC分类号： H01L2900
CPC分类号： H01L27/0623 , H01L27/0214 , H01L27/0218 , H01L27/0922 , H01L27/105 , H01L27/10805
摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.
摘要翻译：公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域，在另一。

5. 发明授权

US5386135A Semiconductor CMOS memory device with separately biased wells 失效
标题翻译：半导体CMOS存储器件具有单独偏置的阱
公开(公告)号：US5386135A
公开(公告)日：1995-01-31
申请号：US229340
申请日：1994-04-12
申请人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
发明人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
IPC分类号： H01L27/02 , H01L27/06 , H01L27/092 , H01L27/105 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10805 , H01L27/0214 , H01L27/0623 , H01L27/0922 , H01L27/0218 , H01L27/105 , Y10S257/901 , Y10S257/904
摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.
摘要翻译：公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域，在另一。

6. 发明授权

US5148255A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5148255A
公开(公告)日：1992-09-15
申请号：US645351
申请日：1991-01-23
申请人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
发明人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
IPC分类号： H01L27/02 , H01L27/06 , H01L27/092 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10805 , H01L27/0214 , H01L27/0623 , H01L27/0922 , H01L27/0218 , H01L27/105
摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.
摘要翻译：公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域，在另一。

7. 发明授权

US07982314B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07982314B2
公开(公告)日：2011-07-19
申请号：US12805261
申请日：2010-07-21
申请人： Masao Shinozaki , Kenji Nishimoto , Takashi Akioka , Yutaka Kohara , Sanae Asari , Shusaku Miyata , Shinji Nakazato
发明人： Masao Shinozaki , Kenji Nishimoto , Takashi Akioka , Yutaka Kohara , Sanae Asari , Shusaku Miyata , Shinji Nakazato
IPC分类号： H01L23/48
CPC分类号： H01L23/5286 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05671 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/12044 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00014 , H01L2924/013 , H01L2924/01027
摘要： Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.
摘要翻译：构成电路的电路元件和布线以及与这种电路电连接的第一电极设置在半导体衬底的一个主表面上。除了第一电极的表面上的开口之外，在电路上形成有机绝缘膜。第一和第二外部连接电极设置在有机绝缘膜上。用于将第一和第二外部连接电极和第一电极电连接的至少一个导电层被放置在有机绝缘膜上。

8. 发明申请

US20100308458A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20100308458A1
公开(公告)日：2010-12-09
申请号：US12805261
申请日：2010-07-21
申请人： Masao Shinozaki , Kenji Nishimoto , Takashi Akioka , Yutaka Kohara , Sanae Asari , Shusaku Miyata , Shinji Nakazato
发明人： Masao Shinozaki , Kenji Nishimoto , Takashi Akioka , Yutaka Kohara , Sanae Asari , Shusaku Miyata , Shinji Nakazato
IPC分类号： H01L23/498
CPC分类号： H01L23/5286 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05671 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/12044 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00014 , H01L2924/013 , H01L2924/01027
摘要： Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.
摘要翻译：构成电路的电路元件和布线以及与这种电路电连接的第一电极设置在半导体衬底的一个主表面上。除了第一电极的表面上的开口之外，在电路上形成有机绝缘膜。第一和第二外部连接电极设置在有机绝缘膜上。用于将第一和第二外部连接电极和第一电极电连接的至少一个导电层被放置在有机绝缘膜上。

9. 发明授权

US07547971B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07547971B2
公开(公告)日：2009-06-16
申请号：US11202352
申请日：2005-08-12
申请人： Masao Shinozaki , Kenji Nishimoto , Takashi Akioka , Yutaka Kohara , Sanae Asari , Shusaku Miyata , Shinji Nakazato
发明人： Masao Shinozaki , Kenji Nishimoto , Takashi Akioka , Yutaka Kohara , Sanae Asari , Shusaku Miyata , Shinji Nakazato
IPC分类号： H01L23/48
CPC分类号： H01L23/5286 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05671 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/12044 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00014 , H01L2924/013 , H01L2924/01027
摘要： Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.
摘要翻译：构成电路的电路元件和布线以及与这种电路电连接的第一电极设置在半导体衬底的一个主表面上。除了第一电极的表面上的开口之外，在电路上形成有机绝缘膜。第一和第二外部连接电极设置在有机绝缘膜上。用于将第一和第二外部连接电极和第一电极电连接的至少一个导电层被放置在有机绝缘膜上。

10. 发明授权

US5324982A Semiconductor memory device having bipolar transistor and structure to avoid soft error 失效
标题翻译：半导体存储器件具有双极晶体管和结构，以避免软错误
公开(公告)号：US5324982A
公开(公告)日：1994-06-28
申请号：US769680
申请日：1991-10-02
申请人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
发明人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
IPC分类号： H01L27/02 , H01L27/06 , H01L27/092 , H01L27/105 , H01L27/108 , H01L27/04 , H01L29/70
CPC分类号： H01L27/10805 , H01L27/0214 , H01L27/0623 , H01L27/0922 , H01L27/0218 , H01L27/105 , Y10S257/901 , Y10S257/904
摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.
摘要翻译：公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域，在另一。

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