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    • 2. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US4748487A
    • 1988-05-31
    • US053479
    • 1987-05-26
    • Hideaki UchidaKinya MitsumotoYoshiaki YazawaShinji NakazatoMasanori Odaka
    • Hideaki UchidaKinya MitsumotoYoshiaki YazawaShinji NakazatoMasanori Odaka
    • H01L21/8238G11C11/34G11C11/419H01L21/8234H01L21/8244H01L27/088H01L27/092H01L27/10H01L27/11H01L27/02
    • G11C11/419H01L27/11
    • A semiconductor memory device wherein the equivalent series resistances that are interposed in series in the pairs of complementary data lines D, D, are substantially the same as one another among the individual complementary data lines D, D. The equivalent series resistance is comprised of pull-up MISFET's and column switching MISFET's that exist between the power source V.sub.CC and the sense circuit. Parity is maintained for the pull-up MISFET's (Q.sub.p, Q.sub.p) and the column switching MISFET's (Q.sub.y, Q.sub.y) that exist on the pairs of complementary data lines D, D. To maintain this parity, the two MISFET's are formed to have the same shape. In addition, the arrangement of contacts to the transistors are set so that the directions in which the currents flow and lengths of current paths are also the same. In other words, contact portions between aluminum electrode and source and drain regions are formed at the same positions in the two MISFET's.
    • 一种半导体存储器件,其中在互补数据线对D,& D和D中的串联插入的等效串联电阻在各个互补数据线D,& L和D之间彼此基本相同。等效串联电阻包括 上拉MISFET和列切换MISFET存在于电源VCC和感测电路之间。 维持上拉MISFET(Qp,Qp)和在互补数据线D和上拉和下降D上存在的列切换MISFET(Qy,Qy)的奇偶校验。为了保持这个奇偶校验,两个MISFET的形成是 相同的形状。 此外,设置与晶体管的接触的布置,使得电流流动的方向和电流路径的长度也相同。 换句话说,铝电极和源极和漏极区域之间的接触部分形成在两个MISFET的相同位置处。
    • 4. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US06740958B2
    • 2004-05-25
    • US10115101
    • 2002-04-04
    • Shinji NakazatoHideaki UchidaYoshikazu SaitoMasahiro YamamuraYutaka KobayashiTakahide IkedaRyoichi HoriGoro KitsukawaKiyoo ItohNobuo TanbaTakao WatanabeKatsuhiro ShimohigashiNoriyuki Homma
    • Shinji NakazatoHideaki UchidaYoshikazu SaitoMasahiro YamamuraYutaka KobayashiTakahide IkedaRyoichi HoriGoro KitsukawaKiyoo ItohNobuo TanbaTakao WatanabeKatsuhiro ShimohigashiNoriyuki Homma
    • H01L2900
    • H01L27/0623H01L27/0214H01L27/0218H01L27/0922H01L27/105H01L27/10805
    • Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.
    • 公开了一种半导体器件,例如半导体存储器件,其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。 半导体存储器件例如可以是SRAM或DRAM,并且在衬底上包括存储器阵列和外围电路。 在本发明的一个方面中,在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。 另外的区域可以例如从掩埋层延伸到半导体衬底的表面,掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。 作为本发明的第二方面,第一载流子吸收区域(以吸收少数载流子)位于存储器阵列和外围电路的开关电路之间,并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。 作为本发明的第三实施例,提供了相同导电类型的多个隔离区域,一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域, 在另一。
    • 6. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US5148255A
    • 1992-09-15
    • US645351
    • 1991-01-23
    • Shinji NakazatoHideaki UchidaYoshikazu SaitoMasahiro YamamuraYutaka KobayashiTakahide IkedaRyoichi HoriGoro KitsukawaKiyoo ItohNobuo TanbaTakao WatanabeKatsuhiro ShimohigashiNoriyuki Homma
    • Shinji NakazatoHideaki UchidaYoshikazu SaitoMasahiro YamamuraYutaka KobayashiTakahide IkedaRyoichi HoriGoro KitsukawaKiyoo ItohNobuo TanbaTakao WatanabeKatsuhiro ShimohigashiNoriyuki Homma
    • H01L27/02H01L27/06H01L27/092H01L27/105H01L27/108
    • H01L27/10805H01L27/0214H01L27/0623H01L27/0922H01L27/0218H01L27/105
    • Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.
    • 公开了一种半导体器件,例如半导体存储器件,其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。 半导体存储器件例如可以是SRAM或DRAM,并且在衬底上包括存储器阵列和外围电路。 在本发明的一个方面中,在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。 另外的区域可以例如从掩埋层延伸到半导体衬底的表面,掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。 作为本发明的第二方面,第一载流子吸收区域(以吸收少数载流子)位于存储器阵列和外围电路的开关电路之间,并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。 作为本发明的第三实施例,提供了相同导电类型的多个隔离区域,一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域, 在另一。