会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 6. 发明申请
    • SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    • 半导体集成电路设备
    • US20090116282A1
    • 2009-05-07
    • US12348524
    • 2009-01-05
    • Kenichi OSADAMasataka MinamiShuji IkedaKoichiro Ishibashi
    • Kenichi OSADAMasataka MinamiShuji IkedaKoichiro Ishibashi
    • G11C11/40
    • H01L27/1104G11C11/412G11C11/417H01L27/11H01L29/4916H01L29/783Y10S257/904
    • Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.
    • 现有的已知的静态随机存取存储器(SRAM)单元需要将扩散层弯曲成键状形状,以便与其中形成有P型阱区的衬底进行电接触,这将导致 不对称性导致了微图案化困难的问题的发生。 为了避免这个问题,构成SRAM单元的逆变器的P型阱区被细分成两部分,它们设置在N型阱区NW1的相对侧上,并形成为扩散 形成晶体管的层没有曲率,同时使得布局方向在平行于阱边界线和位线的方向上运行。 在阵列的中间位置处,以与字线平行的方式形成用于向基板供电的区域,以每组三十二个存储单元行或六十四个单元行提供一个区域。
    • 7. 发明申请
    • METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    • 制造半导体集成电路器件的方法
    • US20080286928A1
    • 2008-11-20
    • US12098312
    • 2008-04-04
    • Masataka MINAMI
    • Masataka MINAMI
    • H01L21/8234
    • H01L21/823807H01L21/823814
    • In the chip with which a plurality of MISFET from which threshold value voltage differs is intermingled, leakage current, such as GIDL current and BTBT current, is suppressed, inhibiting the short channel effect of MISFET. The concentration of the impurity for threshold value voltage adjustment implanted to the region in which n channel type MISFET with relatively low threshold value voltage is formed is made lower than the concentration of the impurity for threshold value voltage adjustment implanted to the region in which n channel type MISFET with relatively high threshold value voltage is formed. Implantation amount of the impurity at the time of forming n− type semiconductor region 19 and punch-through stopper layer 20 in region ALTN is made larger than the implantation amount of the impurity at the time of forming n− type semiconductor region 16 and punch-through stopper layer 17 in region AHTN, respectively.
    • 在其中阈值电压不同的多个MISFET与其混合的芯片中,抑制了诸如GIDL电流和BTBT电流的漏电流,从而抑制了MISFET的短沟道效应。 将形成阈值电压相对较低的n沟道型MISFET的区域中注入的阈值电压调整用杂质浓度设定为比n沟道区域注入的阈值电压调整用杂质浓度低 形成具有相对高阈值电压的MISFET型。 使区域ALTN中形成n + - 型半导体区域19和穿通阻止层20时的杂质的植入量大于形成n < 分别为区域AHTN中的SUP→ - 型半导体区域16和穿通阻挡层17。