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1. 发明授权

US07807543B2 Methods of manufacturing trench isolation structures using selective plasma ion immersion implantation and deposition (PIIID) 有权
标题翻译：使用选择性等离子体离子浸入和沉积（PIIID）制造沟槽隔离结构的方法
公开(公告)号：US07807543B2
公开(公告)日：2010-10-05
申请号：US12134760
申请日：2008-06-06
申请人： Dong-woon Shin , Tai-su Park , Si-young Choi , Soo-jin Hong , Mi-jin Kim
发明人： Dong-woon Shin , Tai-su Park , Si-young Choi , Soo-jin Hong , Mi-jin Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/823481 , H01L21/76229 , H01L21/823456 , H01L27/0921 , H01L27/105
摘要： A semiconductor device is manufactured by forming trenches in a substrate and selectively performing Plasma Ion Immersion Implantation and Deposition (PIIID) on a subset of the trenches in the substrate. The PIIID may be performed on only a portion of a surface of at least one of the trenches in the substrate. Semiconductor devices can include a semiconductor substrate having first, second and third trenches therein, and an oxide liner layer that fully lines the first trenches, that does not line the second trenches and that partially lines the third trenches.
摘要翻译：通过在衬底中形成沟槽并且在衬底中的沟槽的子集上选择性地执行等离子体离子注入植入和沉积（PIIID）来制造半导体器件。 PIIID可以仅在衬底中的至少一个沟槽的表面的一部分上进行。半导体器件可以包括其中具有第一，第二和第三沟槽的半导体衬底以及不对第一沟槽进行线条化的氧化物衬层，其不线性化第二沟槽并且部分地对第三沟槽进行排列。

2. 发明授权

US07785985B2 Methods of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07785985B2
公开(公告)日：2010-08-31
申请号：US12133772
申请日：2008-06-05
申请人： Dong-woon Shin , Tai-su Park , Si-young Choi , Soo-jin Hong , Mi-jin Kim
发明人： Dong-woon Shin , Tai-su Park , Si-young Choi , Soo-jin Hong , Mi-jin Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/823481 , H01L21/76229 , H01L21/823456 , H01L27/0921 , H01L27/105
摘要： Methods of manufacturing a semiconductor device, which can reduce hot electron induced punchthrough (HEIP) and/or improve the operating characteristics of the device include selectively forming an oxynitride layer in a device isolation layer according to the characteristics of transistors isolated by the device isolation layer. The methods include forming first trenches and second trenches on a substrate, forming an oxide layer on the surfaces of the first trenches and the second trenches, selectively forming an oxynitride layer on the second trenches by using plasma ion immersion implantation (PIII), and forming a buried insulating layer in the first trenches and the second trenches. The buried insulating layer may be planarized to form a first device isolation layer in the first trenches and a second device isolation layer in the second trenches.
摘要翻译：可以减少热电子穿透（HEIP）和/或改善器件的工作特性的半导体器件的制造方法包括根据器件隔离层隔离的晶体管的特性选择性地在器件隔离层中形成氧氮化物层。所述方法包括在衬底上形成第一沟槽和第二沟槽，在第一沟槽和第二沟槽的表面上形成氧化物层，通过使用等离子体离子浸没注入（PIII）在第二沟槽上选择性地形成氧氮化物层，并形成在第一沟槽和第二沟槽中的掩埋绝缘层。掩埋绝缘层可以被平坦化以在第一沟槽中形成第一器件隔离层，在第二沟槽中形成第二器件隔离层。

3. 发明申请

US20090203189A1 METHODS OF MANUFACTURING TRENCH ISOLATION STRUCTURES USING SELECTIVE PLASMA ION IMMERSION IMPLANTATION AND DEPOSITION (PIIID) 有权
标题翻译：使用选择性等离子体离子注入和沉积（PIIID）制造TRENCH隔离结构的方法
公开(公告)号：US20090203189A1
公开(公告)日：2009-08-13
申请号：US12134760
申请日：2008-06-06
申请人： Dong-woon Shin , Tai-su Park , Si-Young Choi , Soo-Jin Hong , Mi-Jin Kim
发明人： Dong-woon Shin , Tai-su Park , Si-Young Choi , Soo-Jin Hong , Mi-Jin Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/823481 , H01L21/76229 , H01L21/823456 , H01L27/0921 , H01L27/105
摘要： A semiconductor device is manufactured by forming trenches in a substrate and selectively performing Plasma Ion Immersion Implantation and Deposition (PIIID) on a subset of the trenches in the substrate. The PIIID may be performed on only a portion of a surface of at least one of the trenches in the substrate. Semiconductor devices can include a semiconductor substrate having first, second and third trenches therein, and an oxide liner layer that fully lines the first trenches, that does not line the second trenches and that partially lines the third trenches.
摘要翻译：通过在衬底中形成沟槽并且在衬底中的沟槽的子集上选择性地执行等离子体离子注入植入和沉积（PIIID）来制造半导体器件。 PIIID可以仅在衬底中的至少一个沟槽的表面的一部分上进行。半导体器件可以包括其中具有第一，第二和第三沟槽的半导体衬底以及不对第一沟槽进行线条化的氧化物衬层，其不线性化第二沟槽并且部分地对第三沟槽进行排列。

4. 发明申请

US20090203188A1 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090203188A1
公开(公告)日：2009-08-13
申请号：US12133772
申请日：2008-06-05
申请人： Dong-woon Shin , Tai-su Park , Si-young Choi , Soo-jin Hong , Mi-jin Kim
发明人： Dong-woon Shin , Tai-su Park , Si-young Choi , Soo-jin Hong , Mi-jin Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/823481 , H01L21/76229 , H01L21/823456 , H01L27/0921 , H01L27/105
摘要： Methods of manufacturing a semiconductor device, which can reduce hot electron induced punchthrough (HEIP) and/or improve the operating characteristics of the device include selectively forming an oxynitride layer in a device isolation layer according to the characteristics of transistors isolated by the device isolation layer. The methods include forming first trenches and second trenches on a substrate, forming an oxide layer on the surfaces of the first trenches and the second trenches, selectively forming an oxynitride layer on the second trenches by using plasma ion immersion implantation (PIII), and forming a buried insulating layer in the first trenches and the second trenches. The buried insulating layer may be planarized to form a first device isolation layer in the first trenches and a second device isolation layer in the second trenches.
摘要翻译：可以减少热电子穿透（HEIP）和/或改善器件的工作特性的半导体器件的制造方法包括根据器件隔离层隔离的晶体管的特性选择性地在器件隔离层中形成氧氮化物层。所述方法包括在衬底上形成第一沟槽和第二沟槽，在第一沟槽和第二沟槽的表面上形成氧化物层，通过使用等离子体离子浸没注入（PIII）在第二沟槽上选择性地形成氧氮化物层，并形成在第一沟槽和第二沟槽中的掩埋绝缘层。掩埋绝缘层可以被平坦化以在第一沟槽中形成第一器件隔离层，在第二沟槽中形成第二器件隔离层。

5. 发明申请

US20080176387A1 PLASMA DOPING METHODS USING MULTIPLE SOURCE GASES 审中-公开
标题翻译：使用多种源气体的等离子体掺杂方法
公开(公告)号：US20080176387A1
公开(公告)日：2008-07-24
申请号：US11753791
申请日：2007-05-25
申请人： Jong-hoon Kang , Tai-su Park , Si-young Choi , Min-jin Kim
发明人： Jong-hoon Kang , Tai-su Park , Si-young Choi , Min-jin Kim
IPC分类号： H01L21/265
CPC分类号： H01L21/2236 , H01L21/28035 , H01L21/3215 , H01L21/32155 , H01L29/4916
摘要： A plasma doping method includes providing a substrate including a layer to be doped inside a chamber, and supplying first and second source gases to the layer to achieve a desired doping concentration. The first source gas includes a component configured to increase a thickness of the layer, and the second gas includes a component configured to reduce a thickness of the layer.
摘要翻译：等离子体掺杂方法包括提供包括在室内掺杂的层的衬底，以及将第一和第二源气体供应到层以实现期望的掺杂浓度。第一源气体包括构造成增加层的厚度的部件，并且第二气体包括构造成减小层的厚度的部件。

6. 发明申请

US20050145932A1 Vertical channel field effect transistors having insulating layers thereon and methods of fabricating the same 有权
标题翻译：具有绝缘层的垂直沟道场效应晶体管及其制造方法
公开(公告)号：US20050145932A1
公开(公告)日：2005-07-07
申请号：US10780067
申请日：2004-02-17
申请人： Tai-su Park , Eui-Joon Yoon , U-In Chung , Si-Young Choi , Jong-Ho Lee
发明人： Tai-su Park , Eui-Joon Yoon , U-In Chung , Si-Young Choi , Jong-Ho Lee
IPC分类号： H01L29/78 , H01L21/336 , H01L29/786 , H01L29/10
CPC分类号： H01L29/7851 , H01L29/66795 , H01L29/7854
摘要： A field effect transistor can include a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The transistor can also include a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction. Related methods are also disclosed.
摘要翻译：场效应晶体管可以包括从包括垂直沟道和衬底之间的源极/漏极区域的衬底突出的垂直沟道，以及在垂直沟道的侧壁上朝衬底延伸超过源/漏极的绝缘层区域交界处晶体管还可以包括在离开衬底的侧壁上延伸超过绝缘层的氮化物层，在侧壁上延伸的第二绝缘层，其通过氮化物层与沟道分离，以及栅电极侧壁朝向衬底以超出源/漏区结。还公开了相关方法。

7. 发明授权

US07148541B2 Vertical channel field effect transistors having insulating layers thereon 有权
标题翻译：其上具有绝缘层的垂直沟道场效应晶体管
公开(公告)号：US07148541B2
公开(公告)日：2006-12-12
申请号：US10780067
申请日：2004-02-17
申请人： Tai-su Park , Eui-Joon Yoon , U-In Chung , Si-Young Choi , Jong-Ho Lee
发明人： Tai-su Park , Eui-Joon Yoon , U-In Chung , Si-Young Choi , Jong-Ho Lee
IPC分类号： H01L27/01
CPC分类号： H01L29/7851 , H01L29/66795 , H01L29/7854
摘要： A field effect transistor can include a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The transistor can also include a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction. Related methods are also disclosed.
摘要翻译：场效应晶体管可以包括从包括垂直沟道和衬底之间的源极/漏极区域的衬底突出的垂直沟道，以及在垂直沟道的侧壁上朝向衬底延伸到源极/漏极区域交界处晶体管还可以包括在离开衬底的侧壁上延伸超过绝缘层的氮化物层，在侧壁上延伸的第二绝缘层，其通过氮化物层与沟道分离，以及栅电极侧壁朝向衬底以超出源/漏区结。还公开了相关方法。

8. 发明授权

US06511888B1 Method of fabricating a semiconductor device using trench isolation method including hydrogen annealing step 失效
公开(公告)号：US06511888B1
公开(公告)日：2003-01-28
申请号：US09697302
申请日：2000-10-27
申请人： Tai-su Park , Kyung-won Park , Jung-woo Park , Won-sang Song
发明人： Tai-su Park , Kyung-won Park , Jung-woo Park , Won-sang Song
IPC分类号： H01L21336
CPC分类号： H01L21/76224 , Y10S438/958
摘要： A method of fabricating a semiconductor device using a trench isolation method including a hydrogen annealing step, wherein a photoresist pattern is formed on a semiconductor substrate, a pad insulating layer may be formed before forming the photoresist pattern, the semiconductor substrate is etched using the photoresist pattern as an etching mask to form a trench, and an isolation layer is formed in the trench. To remove damages created in an active region defined by the isolation layer, the semiconductor substrate having the isolation layer is annealed in a hydrogen atmosphere.

9. 发明授权

US07015106B2 Double gate field effect transistor and method of manufacturing the same 失效
公开(公告)号：US07015106B2
公开(公告)日：2006-03-21
申请号：US10917026
申请日：2004-08-11
申请人： Jae-Man Yoon , Dong-gun Park , Gyo-young Jin , Yoshida Makoto , Tai-su Park
发明人： Jae-Man Yoon , Dong-gun Park , Gyo-young Jin , Yoshida Makoto , Tai-su Park
IPC分类号： H01L21/336 , H01L21/00 , H01L21/338
CPC分类号： H01L29/7851 , H01L21/823437 , H01L21/823481 , H01L21/84 , H01L27/1203 , H01L29/66795
摘要： Provided is a double gate field effect transistor and a method of manufacturing the same. The method of manufacturing the double gate field effect transistor comprises forming as many fins as required by etching a silicon substrate, masking the resultant product by an insulating material such as silicon nitride, forming trench regions for device isolation and STI film by using the silicon nitride mask, forming gate oxide films on both faces of the fins after removing the hard mask, and forming a gate line. As such, unnecessary channel formation under the silicon oxide film, when a voltage higher than a threshold voltage is applied to the substrate, is prevented by forming a thick silicon oxide film on the substrate on which no protruding fins are formed.

10. 发明授权

US06537914B1 Integrated circuit device isolation methods using high selectivity chemical-mechanical polishing 有权
标题翻译：集成电路器件隔离方法采用高选择性化学机械抛光
公开(公告)号：US06537914B1
公开(公告)日：2003-03-25
申请号：US09570225
申请日：2000-05-12
申请人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee , Jung-yup Kim , Chang-ki Hong , Ho-kyu Kang
发明人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee , Jung-yup Kim , Chang-ki Hong , Ho-kyu Kang
IPC分类号： H01L21302
CPC分类号： C09G1/02 , C09K3/1463 , H01L21/31053 , H01L21/76224
摘要： Trench isolation methods for integrated circuits may reduce irregularities in the formation of an isolation layer through use of a high selectivity chemical-mechanical polishing (CMP) operation. In particular, a substrate surface is etched to form a trench. An insulation layer is then formed on the substrate surface and in the trench. The insulation layer is chemical-mechanical polished using a slurry that includes a CeO2 group abrasive to form an isolation layer in the trench. The CMP selectivity ratio of a slurry that includes a CeO2 group abrasive may be sufficient to allow the substrate surface to be used as a CMP stop. As a result, a more consistent level of polishing may be maintained over the substrate surface, which may result in a more uniform thickness in the isolation layer.
摘要翻译：用于集成电路的沟槽隔离方法可以通过使用高选择性化学机械抛光（CMP）操作来减少形成隔离层的不规则性。特别地，蚀刻衬底表面以形成沟槽。然后在衬底表面和沟槽中形成绝缘层。绝缘层使用包含CeO 2基团研磨剂的浆料进行化学机械抛光，以在沟槽中形成隔离层。包括CeO 2基研磨剂的浆料的CMP选择比可能足以使基板表面用作CMP停止。结果，可以在衬底表面上保持更一致的抛光水平，这可能导致隔离层中更均匀的厚度。

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