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1. 再颁专利

USRE40311E1 Zero-power programmable memory cell 有权
标题翻译：零功率可编程存储单元
公开(公告)号：USRE40311E1
公开(公告)日：2008-05-13
申请号：US11206282
申请日：2005-08-17
申请人： Sunil D. Mehta , Fabiano Fontana
发明人： Sunil D. Mehta , Fabiano Fontana
IPC分类号： G11C16/04
CPC分类号： G11C16/045 , G11C16/0441
摘要： A zero-power electrically erasable and programmable memory cell is implemented in CMOS (complementary metal oxide semiconductor) technology. A P-channel sense transistor has a source coupled to a first voltage generator, and an N-channel sense transistor has a source coupled to a second voltage generator. The drains of the P-channel and N-channel sense transistors are coupled together to form an output of the memory cell, and the gates of the P-channel and N-channel sense transistor are coupled together to form a floating gate of the memory cell. In an example embodiment of the present invention, each of the first and second voltage generators are variable voltage generators that apply a positive voltage at the respective source of each of the P-channel and N-channel sense transistors during the erase operation and/or that apply a ground or negative voltage at the respective source of each of the P-channel and N-channel sense transistors during the program operation. In another embodiment of the present invention, a magnitude of the respective threshold voltage of each of the P-channel and N-channel sense transistors is higher than a magnitude of a threshold voltage of standard process P-channel and N-channel transistors. With such a higher threshold voltage, the P-channel and N-channel sense transistors do not erroneously turn on to dissipate power during the read operation, to ensure that the memory cell is a zero-power memory cell.
摘要翻译：在CMOS（互补金属氧化物半导体）技术中实现零功率电可擦除和可编程存储器单元。 P沟道感测晶体管具有耦合到第一电压发生器的源极，并且N沟道感测晶体管具有耦合到第二电压发生器的源极。 P沟道和N沟道感测晶体管的漏极耦合在一起以形成存储单元的输出，并且P沟道和N沟道读出晶体管的栅极耦合在一起以形成存储器的浮置栅极细胞。在本发明的示例性实施例中，第一和第二电压发生器中的每一个是在擦除操作期间在每个P沟道和N沟道读出晶体管的各个源处施加正电压的可变电压发生器和/或其在编程操作期间在每个P沟道和N沟道感测晶体管的相应源处施加接地或负电压。在本发明的另一个实施例中，每个P沟道和N沟道检测晶体管的相应阈值电压的大小都高于标准工艺P沟道和N沟道晶体管的阈值电压的幅度。利用这种较高的阈值电压，P信道和N沟道检测晶体管在读取操作期间不会错误地导通以耗散功率，以确保存储器单元是零功率存储单元。

2. 发明授权

US06846714B1 Voltage limited EEPROM device and process for fabricating the device 失效
标题翻译：电压限制EEPROM器件和制造器件的工艺
公开(公告)号：US06846714B1
公开(公告)日：2005-01-25
申请号：US10263507
申请日：2002-10-03
申请人： Sunil D. Mehta , Kerry Ilgenstein
发明人： Sunil D. Mehta , Kerry Ilgenstein
IPC分类号： G11C16/30 , H01L21/336 , H01L21/8247 , H01L27/105 , H01L27/115
CPC分类号： H01L27/105 , G11C16/30 , H01L27/115 , H01L27/11521 , H01L27/11558 , Y10S438/981
摘要： An EEPROM device having voltage limiting charge pumping circuitry includes charge pumping circuitry that limits the voltage supplied to the high voltage transistors to levels below the breakdown field of the tunnel oxide layer. The EEPROM device includes a substrate having a programming region, a tunnel region, a sensing region, and a low voltage region. A first oxide layer having a first thickness overlies the tunnel region and the sensing region. A second oxide layer having a second thickness overlies the low voltage region. The first oxide thickness is greater than the second oxide thickness. A charge pumping circuit is coupled to the programming region and to the tunnel region. The charge pumping circuit impresses a voltage level across the first oxide layer that is below the field breakdown voltage of first oxide layer. A process for fabricating the device is also provided.
摘要翻译：具有电压限制电荷泵浦电路的EEPROM器件包括电荷泵浦电路，其将提供给高压晶体管的电压限制在低于隧道氧化物层的击穿场的水平。 EEPROM器件包括具有编程区域，隧道区域，感测区域和低电压区域的衬底。具有第一厚度的第一氧化物层覆盖隧道区域和感测区域。具有第二厚度的第二氧化物层覆盖在低电压区域上。第一氧化物厚度大于第二氧化物厚度。电荷泵浦电路耦合到编程区域和隧道区域。电荷泵浦电路使第一氧化物层的电压电平低于第一氧化物层的场击穿电压。还提供了一种用于制造该装置的工艺。

3. 发明授权

US06600188B1 EEPROM with a neutralized doping at tunnel window edge 失效
标题翻译：在隧道窗边缘具有中和掺杂的EEPROM
公开(公告)号：US06600188B1
公开(公告)日：2003-07-29
申请号：US10083728
申请日：2002-02-26
申请人： Chun Jiang , Sunil D. Mehta
发明人： Chun Jiang , Sunil D. Mehta
IPC分类号： H01L27108
CPC分类号： H01L29/0847 , H01L21/28273 , H01L29/66825 , H01L29/7883
摘要： An improved method for fabricating a tunnel oxide window for use in an EEPROM memory cell is provided so as to produce better programming endurance. P-type lightly-doped drain regions are located at the polysilicon edges of the tunnel window. During the programming operation, the P-type lightly-doped drain regions are in contacting with the polysilicon edges. As a result, there is reduced or suppressed the tunneling current to the program junction region so as to improve the efficiency of programming.
摘要翻译：提供了一种用于制造用于EEPROM存储单元的隧道氧化物窗口的改进方法，以便产生更好的编程耐久性。 P型轻掺杂漏极区位于隧道窗的多晶硅边缘处。在编程操作期间，P型轻掺杂漏极区域与多晶硅边缘接触。结果，减少或抑制了到程序结区域的隧穿电流，从而提高编程效率。

4. 发明授权

US06455375B1 Eeprom tunnel window for program injection via P+ contacted inversion 失效
标题翻译： Eeprom隧道窗口通过P +接触反转进行程序注入
公开(公告)号：US06455375B1
公开(公告)日：2002-09-24
申请号：US09870541
申请日：2001-06-01
申请人： Chun Jiang , Robert Tu , Sunil D. Mehta
发明人： Chun Jiang , Robert Tu , Sunil D. Mehta
IPC分类号： H01L218247
CPC分类号： H01L21/28273
摘要： An improved method for fabricating a tunnel oxide window for use in an EEPROM memory cell is provided so as to produce better programming endurance. A P+ implant is provided at the tunnel window edge. During the programming operation, the P+ contacted inversion layer is used instead of the program junction. As a result, there is eliminated the voltage drop in the program junction region so as to improve the efficiency of programming.
摘要翻译：提供了一种用于制造用于EEPROM存储单元的隧道氧化物窗口的改进方法，以便产生更好的编程耐久性。在隧道窗边缘提供P +植入物。在编程操作期间，使用P +接触反转层代替程序结。结果，消除了程序结区域中的电压降，从而提高编程效率。

5. 发明授权

US06309942B1 STI punch-through defects and stress reduction by high temperature oxide reflow process 有权
标题翻译： STI穿透缺陷和通过高温氧化物回流工艺的应力降低
公开(公告)号：US06309942B1
公开(公告)日：2001-10-30
申请号：US09245161
申请日：1999-02-04
申请人： Ting Y. Tsui , Robert H. Tu , Xiao-Yu Li , Sunil D. Mehta
发明人： Ting Y. Tsui , Robert H. Tu , Xiao-Yu Li , Sunil D. Mehta
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： A method of manufacturing a semiconductor device with reduced shallow trench isolation defects and stress is disclosed. The disclosed method begins by providing a silicon substrate including a capping layer. A plurality of isolation trenches are then etched through the capping layer and into the silicon substrate to form a plurality of isolation regions in the silicon substrate. The isolation trenches are then filled with an oxide layer. The oxide layer and the capping layer are then polished back using techniques known in the art. After polishing, the semiconductor device is annealed between a temperature range of about 1150° C. to about 1200° C.
摘要翻译：公开了一种制造具有减小的浅沟槽隔离缺陷和应力的半导体器件的方法。所公开的方法开始于提供包括封盖层的硅衬底。然后通过覆盖层蚀刻多个隔离沟槽并进入硅衬底，以在硅衬底中形成多个隔离区域。然后用氧化物层填充隔离沟槽。然后使用本领域已知的技术将氧化物层和覆盖层进行抛光。在抛光之后，半导体器件在约1150℃至约1200℃的温度范围内退火

6. 发明授权

US06297128B1 Process for manufacturing shallow trenches filled with dielectric material having low mechanical stress 失效
标题翻译：用于制造具有低机械应力的电介质材料的浅沟槽的制造方法
公开(公告)号：US06297128B1
公开(公告)日：2001-10-02
申请号：US09240560
申请日：1999-01-29
申请人： Hyeon-Seag Kim , Sunil D. Mehta
发明人： Hyeon-Seag Kim , Sunil D. Mehta
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： This invention provides methods for reducing the mechanical stresses within dielectric layers filling the gaps in shallow trench isolation (STI) regions on semiconductor wafers. The methods include the sequential deposition of alternating layers of dielectric materials having tensile stress and compressive stress, respectively. The invention also provides methods for adjusting the residual stress in a dielectric film by controlling the relative thicknesses of the alternating layers of dielectric material to provide bilayers having minimal overall stress. Additionally, the invention provides semiconductor devices having the reduced stress dielectric materials within the shallow isolation trenches of the semiconductor wafer. The reduction in stress within and between trenches decreases defects in the shallow isolation materials and thereby decreases source-drain and trench—trench short circuiting. The improved electrical and mechanical properties of the shallow trench filling materials makes practical the manufacture of more reliable, smaller semiconductor devices.
摘要翻译：本发明提供了减少填充半导体晶片上的浅沟槽隔离（STI）区域中的间隙的电介质层内的机械应力的方法。这些方法包括分别具有拉伸应力和压缩应力的交替层的介电材料的顺序沉积。本发明还提供了通过控制介电材料的交替层的相对厚度以提供具有最小总应力的双层来调节电介质膜中的残余应力的方法。此外，本发明提供了在半导体晶片的浅隔离沟槽内具有减小的应力介电材料的半导体器件。沟槽内和沟槽之间的应力减小降低了浅隔离材料的缺陷，从而减少了源极 - 漏极和沟槽沟槽短路。浅沟槽填充材料的改进的电气和机械性能使得制造更可靠，更小的半导体器件成为可能。

7. 发明授权

US06261944B1 Method for forming a semiconductor device having high reliability passivation overlying a multi-level interconnect 有权
标题翻译：用于形成具有高可靠性钝化的半导体器件的方法，覆盖多层互连
公开(公告)号：US06261944B1
公开(公告)日：2001-07-17
申请号：US09200395
申请日：1998-11-24
申请人： Sunil D. Mehta , Xiao-Yu Li
发明人： Sunil D. Mehta , Xiao-Yu Li
IPC分类号： H01L214763
CPC分类号： H01L21/316 , H01L21/76819 , H01L21/76825 , H01L23/3192 , H01L24/48 , H01L2224/05599 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2924/00012
摘要： A semiconductor device having a high reliability passivation includes a planarization layer overlying a multi-level interconnect layer. The passivation layer has a planar surface upon which additional passivation layers are formed. Openings in the overlying passivation layers and the planarization layer expose bonding pads in the multi-level interconnect layer. In a process for fabricating the device, the planarization layer is preferably formed by dispensing a siloxane spin-on-glass (SOG) material onto the surface of the multi-level interconnect layer. The SOG is subsequently planarized to form a substantially planar surface.
摘要翻译：具有高可靠性钝化的半导体器件包括覆盖多层互连层的平坦化层。钝化层具有平坦表面，在其上形成附加的钝化层。上覆钝化层和平坦化层中的开口暴露多层互连层中的焊盘。在制造该器件的过程中，平坦化层优选通过将硅氧烷旋涂玻璃（SOG）材料分配到多层互连层的表面上而形成。 SOG随后被平坦化以形成基本平坦的表面。

8. 发明授权

US06232223B1 High integrity borderless vias with protective sidewall spacer 有权
标题翻译：高完整性无边界通孔与保护性侧壁间隔
公开(公告)号：US06232223B1
公开(公告)日：2001-05-15
申请号：US09406835
申请日：1999-09-28
申请人： Khanh Q. Tran , Sunil D. Mehta
发明人： Khanh Q. Tran , Sunil D. Mehta
IPC分类号： H01L214763
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： High integrity borderless vias are formed with a protective sidewall spacer on the exposed side surface of the underlying metal feature before depositing a barrier layer. Embodiments include depositing a dielectric capping layer on a metal feature having an ARC, e.g., TiN, etching to form a through-hole stopping on the capping layer, and then etching the exposed capping layer to form the protective sidewall spacer. Other embodiments include depositing a hard inorganic mask layer on the upper surface of the metal feature before depositing the capping layer, forming the through-hole, and sequentially etching the exposed capping layer to form the protective sidewall spacer and then the inorganic hard mask layer. Further embodiments include metal features without an ARC and retaining the inorganic mask layer on the upper surface of the metal feature.
摘要翻译：高度完整的无边界通孔在沉积阻挡层之前在底层金属特征的暴露的侧表面上形成有保护性侧壁间隔物。实施例包括在具有ARC的金属特征（例如TiN）上沉积介电覆盖层，以蚀刻以形成在封盖层上停止的通孔，然后蚀刻暴露的封盖层以形成保护性侧壁间隔物。其他实施方案包括在沉积覆盖层之前在金属特征的上表面上沉积硬无机掩模层，形成通孔，并且依次蚀刻暴露的覆盖层以形成保护性侧壁间隔物，然后形成无机硬掩模层。另外的实施例包括没有ARC并且将无机掩模层保持在金属特征的上表面上的金属特征。

9. 发明授权

US06215700B1 PMOS avalanche programmed floating gate memory cell structure 失效
标题翻译： PMOS雪崩编程浮栅存储单元结构
公开(公告)号：US06215700B1
公开(公告)日：2001-04-10
申请号：US09226702
申请日：1999-01-07
申请人： Steven J. Fong , Stewart G. Logie , Sunil D. Mehta
发明人： Steven J. Fong , Stewart G. Logie , Sunil D. Mehta
IPC分类号： G11C1604
CPC分类号： H01L27/115 , G11C16/0433 , G11C2216/10
摘要： A non-volatile memory cell structure which includes a floating gate, a reverse breakdown element and a read transistor. The reverse breakdown element is at least partially formed in a first region of a first conductivity type in a semiconductor substrate, and underlies a portion of the floating gate; and the read transistor is at least partially formed in the first region and connected to the reverse breakdown element. In a further embodiment a control gate is capacitively coupled to the floating gate and is formed in a second region of the substrate, outside the well region.
摘要翻译：一种包括浮动栅极，反向击穿元件和读取晶体管的非易失性存储单元结构。反向击穿元件至少部分地形成在半导体衬底中的第一导电类型的第一区域中，并且位于浮置栅极的一部分下方; 并且读取晶体管至少部分地形成在第一区域中并连接到反向击穿元件。在另一个实施例中，控制栅极电容耦合到浮置栅极，并且形成在衬底的第二区域中，在阱区域外部。

10. 发明授权

US06184105B2 Method for post transistor isolation 失效
标题翻译：后晶体管隔离的方法
公开(公告)号：US06184105B2
公开(公告)日：2001-02-06
申请号：US08861553
申请日：1997-05-22
申请人： Yowjuang W. Liu , Sunil D. Mehta
发明人： Yowjuang W. Liu , Sunil D. Mehta
IPC分类号： H01L2176
CPC分类号： H01L21/76235 , H01L21/76202 , H01L29/0649
摘要： A method of fabricating integrated circuit including field effect transistors (FET) having source and drain regions and a gate and with LOCOS isolation by selectively forming, after the FETs are fabricated, trench openings in the source or drain regions or in the LOCOS isolation to maximize the isolation in selected areas while reducing the amount of silicon used by the isolation.
摘要翻译：一种制造集成电路的方法，其包括具有源极和漏极区域以及栅极和FETOS隔离的场效应晶体管（FET），其通过在FET被制造之后通过选择性地形成在源极或漏极区域中或在LOCOS隔离中的最大化在选择的区域进行隔离，同时减少隔离使用的硅的量。

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