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1. 发明授权

US6064595A Floating gate memory apparatus and method for selected programming thereof 有权
标题翻译：浮栅存储装置及其选择编程方法
公开(公告)号：US6064595A
公开(公告)日：2000-05-16
申请号：US220201
申请日：1998-12-23
申请人： Stewart G. Logie , Sunil D. Mehta , Steven J. Fong
发明人： Stewart G. Logie , Sunil D. Mehta , Steven J. Fong
IPC分类号： H01L21/8247 , G11C16/04 , G11C16/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： G11C16/0441 , G11C16/10 , H01L29/7886
摘要： A method of creating a reverse breakdown condition in an array of memory cells arranged in columns and rows in the array, and an array structure are provided. The method comprises the steps of applying a first voltage on a first column connection coupling a first column of said cells, and a second voltage on a second column connection coupling a second column of said cells; and applying a third voltage on a first row connection coupling a first row of said cells, and applying said second voltage on a second row connection coupling a second row of said cells. In this aspect, the difference between the first voltage and the third voltage creates said reverse breakdown condition in at least one cell occupying said first column and first row. In a further aspect, each cell includes a floating gate and the method of the invention includes the step of programming one of said cells by coupling a control voltage to each floating gate. The structure includes a substrate having formed therein at least an Nth or Mth row-wise oriented well, each well isolated from adjacent ones of said wells. Also provided are at least an Nth and Mth word bit line formed by an Nth and Mth impurity regions in said substrate and at least an Nth and Mth array control gate lines. A plurality of memory cells, each cell formed in at least said Nth or Mth row-wise well, is further provided. Each cell comprises a drain, a floating gate, a drain connection one of said Nth or Mth word bit line (WBL), and a substrate well connection to one of said Nth or Mth wells, and a control gate connection to one of said Nth or Mth array control gate lines(ACG).
摘要翻译：提供了在阵列中以行和列排列的存储单元阵列中产生反向故障条件的方法，以及阵列结构。该方法包括以下步骤：在耦合所述单元的第一列的第一列连接上施加第一电压，以及在耦合所述单元的第二列的第二列连接上施加第二电压; 以及在耦合所述单元的第一行的第一行连接上施加第三电压，以及将耦合所述单元的第二行的第二行连接上施加所述第二电压。在这方面，第一电压和第三电压之间的差异在占据所述第一列和第一行的至少一个单元中产生所述反向击穿条件。在另一方面，每个单元包括浮动栅极，并且本发明的方法包括通过将控制电压耦合到每个浮动栅极来编程所述单元之一的步骤。该结构包括在其中形成有至少第N或第M行行取向阱的衬底，每个阱与相邻的所述阱分离。还提供了由所述衬底中的第N和第M杂质区形成的至少第N和第M字位线以及至少第N和第M阵列控制栅极线。还提供多个存储单元，每个单元形成在至少所述第N或第M行列井中。每个单元包括所述第N或第M字位线（WBL）之一的漏极，浮置栅极，漏极连接以及与所述第N或第M阱之一的衬底阱连接，以及到所述第N个或第M阵列控制栅极线（ACG）。

2. 发明授权

US06215700B1 PMOS avalanche programmed floating gate memory cell structure 失效
标题翻译： PMOS雪崩编程浮栅存储单元结构
公开(公告)号：US06215700B1
公开(公告)日：2001-04-10
申请号：US09226702
申请日：1999-01-07
申请人： Steven J. Fong , Stewart G. Logie , Sunil D. Mehta
发明人： Steven J. Fong , Stewart G. Logie , Sunil D. Mehta
IPC分类号： G11C1604
CPC分类号： H01L27/115 , G11C16/0433 , G11C2216/10
摘要： A non-volatile memory cell structure which includes a floating gate, a reverse breakdown element and a read transistor. The reverse breakdown element is at least partially formed in a first region of a first conductivity type in a semiconductor substrate, and underlies a portion of the floating gate; and the read transistor is at least partially formed in the first region and connected to the reverse breakdown element. In a further embodiment a control gate is capacitively coupled to the floating gate and is formed in a second region of the substrate, outside the well region.
摘要翻译：一种包括浮动栅极，反向击穿元件和读取晶体管的非易失性存储单元结构。反向击穿元件至少部分地形成在半导体衬底中的第一导电类型的第一区域中，并且位于浮置栅极的一部分下方; 并且读取晶体管至少部分地形成在第一区域中并连接到反向击穿元件。在另一个实施例中，控制栅极电容耦合到浮置栅极，并且形成在衬底的第二区域中，在阱区域外部。

3. 发明授权

US06294809B1 Avalanche programmed floating gate memory cell structure with program element in polysilicon 失效
标题翻译：雪崩编程的浮栅存储单元结构与多晶硅中的程序元素
公开(公告)号：US06294809B1
公开(公告)日：2001-09-25
申请号：US09221360
申请日：1998-12-28
申请人： Stewart G. Logie
发明人： Stewart G. Logie
IPC分类号： H01L29788
CPC分类号： H01L27/115
摘要： A non-volatile memory cell structure comprises a floating gate, a reverse breakdown injection element at least partially formed in a polysilicon layer and operatively coupled to the floating gate, and a transistor at least partially formed in a region of a semiconductor substrate, operatively coupled to the floating gate. In a further aspect, a control gate is capacitively coupled to the floating gate and is formed in said polysilicon layer. The reverse breakdown electron injection element comprises a first, second, and third active regions, the first and second regions comprising a first p/n junction, the second and third active regions comprising a second p/n junction.
摘要翻译：非易失性存储单元结构包括浮置栅极，至少部分地形成在多晶硅层中并且可操作地耦合到浮置栅极的反向击穿注入元件，以及至少部分地形成在半导体衬底的区域中的晶体管，操作耦合到浮动门。在另一方面，控制栅极电容耦合到浮置栅极，并形成在所述多晶硅层中。反向击穿电子注入元件包括第一，第二和第三有源区，第一和第二区包括第一p / n结，第二和第三有源区包括第二p / n结。

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