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1. 发明授权

US6097090A High integrity vias 失效
标题翻译：高完整性通孔
公开(公告)号：US6097090A
公开(公告)日：2000-08-01
申请号：US102893
申请日：1998-06-23
申请人： Khanh Q. Tran , Sunil D. Mehta , Andre Stolmeijer
发明人： Khanh Q. Tran , Sunil D. Mehta , Andre Stolmeijer
IPC分类号： H01L21/60 , H01L23/522 , H01L23/532 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5226 , H01L21/76897 , H01L23/53223 , H01L2924/0002
摘要： Vias are formed by depositing a hard dielectric mask layer on the upper surface of a lower metal feature and forming sidewall spacers on the side surfaces of the metal feature and mask layer. Embodiments include depositing a dielectric interlayer and forming a misaligned through-hole therein by etching. The dielectric material of the sidewall spacer and dielectric material of the dielectric interlayer are different. The etchant employed to form the through-hole exhibits a high selectivity with respect to the sidewall spacer material. The dielectric mask layer enables the formation of a sidewall spacer extending above the metal feature such that, after etching to form the misaligned through-hole, the sidewall spacer covers the side surface of the metal feature.
摘要翻译：通过在下金属特征的上表面上沉积硬介电掩模层并在金属特征和掩模层的侧表面上形成侧壁间隔而形成通孔。实施例包括沉积电介质中间层并通过蚀刻在其中形成不对准的通孔。电介质中间层的侧壁间隔物和电介质材料的电介质材料是不同的。用于形成通孔的蚀刻剂相对于侧壁间隔物材料显示出高选择性。电介质掩模层能够形成在金属特征之上延伸的侧壁间隔，使得在蚀刻以形成未对准的通孔之后，侧壁间隔物覆盖金属特征的侧表面。

2. 发明授权

US06232223B1 High integrity borderless vias with protective sidewall spacer 有权
标题翻译：高完整性无边界通孔与保护性侧壁间隔
公开(公告)号：US06232223B1
公开(公告)日：2001-05-15
申请号：US09406835
申请日：1999-09-28
申请人： Khanh Q. Tran , Sunil D. Mehta
发明人： Khanh Q. Tran , Sunil D. Mehta
IPC分类号： H01L214763
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： High integrity borderless vias are formed with a protective sidewall spacer on the exposed side surface of the underlying metal feature before depositing a barrier layer. Embodiments include depositing a dielectric capping layer on a metal feature having an ARC, e.g., TiN, etching to form a through-hole stopping on the capping layer, and then etching the exposed capping layer to form the protective sidewall spacer. Other embodiments include depositing a hard inorganic mask layer on the upper surface of the metal feature before depositing the capping layer, forming the through-hole, and sequentially etching the exposed capping layer to form the protective sidewall spacer and then the inorganic hard mask layer. Further embodiments include metal features without an ARC and retaining the inorganic mask layer on the upper surface of the metal feature.
摘要翻译：高度完整的无边界通孔在沉积阻挡层之前在底层金属特征的暴露的侧表面上形成有保护性侧壁间隔物。实施例包括在具有ARC的金属特征（例如TiN）上沉积介电覆盖层，以蚀刻以形成在封盖层上停止的通孔，然后蚀刻暴露的封盖层以形成保护性侧壁间隔物。其他实施方案包括在沉积覆盖层之前在金属特征的上表面上沉积硬无机掩模层，形成通孔，并且依次蚀刻暴露的覆盖层以形成保护性侧壁间隔物，然后形成无机硬掩模层。另外的实施例包括没有ARC并且将无机掩模层保持在金属特征的上表面上的金属特征。

3. 发明授权

US5982035A High integrity borderless vias with protective sidewall spacer 失效
标题翻译：高完整性无边界通孔与保护性侧壁间隔
公开(公告)号：US5982035A
公开(公告)日：1999-11-09
申请号：US94726
申请日：1998-06-15
申请人： Khanh Q. Tran , Sunil D. Mehta
发明人： Khanh Q. Tran , Sunil D. Mehta
IPC分类号： H01L23/522 , H01L23/48
CPC分类号： H01L23/5226 , H01L2924/0002
摘要： High integrity borderless vias are formed with a protective sidewall spacer on the exposed side surface of the underlying metal feature before depositing a barrier layer. Embodiments include depositing a dielectric capping layer on a metal feature having an ARC, e.g., TiN, etching to form a through-hole stopping on the capping layer, and then etching the exposed capping layer to form the protective sidewall spacer. Other embodiments include depositing a hard inorganic mask layer on the upper surface of the metal feature before depositing the capping layer, forming the through-hole, and sequentially etching the exposed capping layer to form the protective sidewall spacer and then the inorganic hard mask layer. Further embodiments include metal features without an ARC and retaining the inorganic mask layer on the upper surface of the metal feature.
摘要翻译：高度完整的无边界通孔在沉积阻挡层之前在底层金属特征的暴露的侧表面上形成有保护性侧壁间隔物。实施例包括在具有ARC的金属特征（例如TiN）上沉积介电覆盖层，以蚀刻以形成在封盖层上停止的通孔，然后蚀刻暴露的封盖层以形成保护性侧壁间隔物。其他实施方案包括在沉积覆盖层之前在金属特征的上表面上沉积硬无机掩模层，形成通孔，并且依次蚀刻暴露的覆盖层以形成保护性侧壁间隔物，然后形成无机硬掩模层。另外的实施例包括没有ARC并且将无机掩模层保持在金属特征的上表面上的金属特征。

4. 发明授权

US5942801A Borderless vias with HSQ gap filled metal patterns having high etching resistance 失效
标题翻译：具有高耐蚀刻性的HSQ间隙填充金属图案的无边界通孔
公开(公告)号：US5942801A
公开(公告)日：1999-08-24
申请号：US992430
申请日：1997-12-18
申请人： Khanh Q. Tran
发明人： Khanh Q. Tran
IPC分类号： H01L21/312 , H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5226 , H01L21/76801 , H01L21/76802 , H01L21/76828 , H01L21/76834 , H01L23/5329 , H01L21/3124 , H01L2924/0002
摘要： Spacings between metal features are gap filled with HSQ. Portions of the deposited HSQ adjoining the side surfaces and upper surface of a metal feature are selectively heated to increase the density and etch resistance of the adjoining HSQ portions, thereby enabling formation of reliable, voidless, low resistance, borderless vias. In an embodiment of the present invention, selective heating is effected by heating a metal line to indirectly heat the adjoining portions of the HSQ layer, as by infrared heating.
摘要翻译：金属特征之间的间距充满了HSQ。选择性地加热与金属特征的侧表面和上表面相邻的沉积的HSQ的部分以增加邻接的HSQ部分的密度和耐蚀刻性，从而形成可靠的无空隙低电阻的无边界通孔。在本发明的一个实施例中，通过加热金属线来间接加热HSQ层的相邻部分，如通过红外加热来进行选择性加热。

5. 发明授权

US6046106A High density plasma oxide gap filled patterned metal layers with improved electromigration resistance 失效
标题翻译：具有改善的电迁移阻力的高密度等离子体氧化物间隙填充图案化金属层
公开(公告)号：US6046106A
公开(公告)日：2000-04-04
申请号：US924133
申请日：1997-09-05
申请人： Khanh Q. Tran , Paul R. Besser , Guarionex Morales , Shekhar Pramanick
发明人： Khanh Q. Tran , Paul R. Besser , Guarionex Morales , Shekhar Pramanick
IPC分类号： H01L21/321 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76838 , H01L21/321 , H01L21/76801 , H01L21/76834
摘要： Borderless submicron vias are formed between patterned metal layers gap filled with a high density plasma oxide. Heat treatment is conducted after chemical vapor deposition of the high density plasma oxide to substantially increase the grain size of the patterned metal layers, thereby improving electromigration resistance.
摘要翻译：在被填充有高密度等离子体氧化物的图案化金属层间隙之间形成无边界的亚微米通孔。在高密度等离子体氧化物的化学气相沉积之后进行热处理，以显着增加图案化金属层的晶粒尺寸，从而提高抗电迁移性。

6. 发明授权

US6163818A Streaming memory controller for a PCI bus 有权
标题翻译：用于PCI总线的流式存储控制器
公开(公告)号：US6163818A
公开(公告)日：2000-12-19
申请号：US141398
申请日：1998-08-27
申请人： Uoc H. Nguyen , Otto Sperber , Khanh Q. Tran , David K. Bovaird
发明人： Uoc H. Nguyen , Otto Sperber , Khanh Q. Tran , David K. Bovaird
IPC分类号： G06F3/12 , B41J21/00 , G06F13/28 , G06F13/36 , G06F13/00
CPC分类号： G06F13/28
摘要： In a system having a PCI bus, an additional memory attached to the bus to allow a higher speed of data transfer for a number of copies from the computer to a number of devices. The additional memory has a number of DMA channels, each associated with an I/O device. One copy of the data required by an I/O device is transferred to the memory at normal computer FIFO speed. Thereafter, multiple copies of that data can be transferred to the I/O device from the memory at the higher data bus speed.
摘要翻译：在具有PCI总线的系统中，连接到总线的附加存储器允许从计算机到多个设备的多个副本的更高速度的数据传输。附加存储器具有多个DMA通道，每个DMA通道与I / O设备相关联。 I / O设备所需数据的一个副本以正常的计算机FIFO速度传输到存储器。此后，该数据的多个副本可以以更高的数据总线速度从存储器传送到I / O设备。

7. 发明授权

US5738917A Process for in-situ deposition of a Ti/TiN/Ti aluminum underlayer 失效
标题翻译： Ti / TiN / Ti铝底层原位沉积工艺
公开(公告)号：US5738917A
公开(公告)日：1998-04-14
申请号：US393625
申请日：1995-02-24
申请人： Paul R. Besser , Khanh Q. Tran
发明人： Paul R. Besser , Khanh Q. Tran
IPC分类号： H01L21/768 , H05H1/24
CPC分类号： H01L21/76841 , Y10T428/31678
摘要： A single chamber of a vapor deposition system is used to deposit both Ti and TiN. A Ti layer is deposited on the sample using a noncollimated process. N.sub.2 gas is then introduced in the chamber. A TiN layer is then deposited over the Ti layer. A second Ti layer is deposited over the TiN layer. A separate Ti pasting of a TiN chamber is eliminated, thereby increasing throughput. Further, only three physical vapor deposition chambers are used, thereby allowing the fourth chamber to be used for other metal deposition. Moreover, the second Ti layer eliminates the first wafer effect and reduces sheet resistance relative to a same chamber Ti/TiN underlayer. Lastly, the Al deposited on this new stack has a stronger crystallographic texture, which leads to better electromigration resistance.
摘要翻译：使用单个气相沉积系统的室来沉积Ti和TiN。使用非对准的方法将Ti层沉积在样品上。然后将N 2气体引入室中。然后在Ti层上沉积TiN层。在TiN层上沉积第二Ti层。消除TiN室的单独Ti粘贴，从而提高生产量。此外，仅使用三个物理气相沉积室，从而允许第四室用于其它金属沉积。此外，第二Ti层消除了第一晶片效应并且相对于相同的室Ti / TiN底层降低了薄层电阻。最后，沉积在该新叠层上的Al具有更强的<111>晶体结构，这导致更好的抗电迁移性。

8. 发明授权

US06319859B1 Borderless vias with HSQ gap filled metal patterns having high etching resistance 有权
标题翻译：具有高耐蚀刻性的HSQ间隙填充金属图案的无边界通孔
公开(公告)号：US06319859B1
公开(公告)日：2001-11-20
申请号：US09338516
申请日：1999-06-23
申请人： Khanh Q. Tran
发明人： Khanh Q. Tran
IPC分类号： H01L21469
CPC分类号： H01L23/5226 , H01L21/02126 , H01L21/02134 , H01L21/022 , H01L21/3124 , H01L21/76801 , H01L21/76802 , H01L21/76828 , H01L21/76834 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Spacings between metal features are gap filled with HSQ. Portions of the deposited HSQ adjoining the side surfaces and upper surface of a metal feature are selectively heated to increase the density and etch resistance of the adjoining HSQ portions, thereby enabling formation of reliable, voidless, low resistance, borderless vias. In an embodiment of the present invention, selective heating is effected by heating a metal line to indirectly heat the adjoining portions of the HSQ layer, as by infrared heating.
摘要翻译：金属特征之间的间距充满了HSQ。选择性地加热与金属特征的侧表面和上表面相邻的沉积的HSQ的部分以增加邻接的HSQ部分的密度和耐蚀刻性，从而形成可靠的无空隙低电阻的无边界通孔。在本发明的一个实施例中，通过加热金属线来间接加热HSQ层的相邻部分，如通过红外加热来进行选择性加热。

9. 发明授权

US5888911A HSQ processing for reduced dielectric constant 失效
标题翻译： HSQ处理降低介电常数
公开(公告)号：US5888911A
公开(公告)日：1999-03-30
申请号：US956590
申请日：1997-10-23
申请人： Minh V. Ngo , Khanh Q. Tran , Lu You , Jean Y. Yang , Richard J. Huang
发明人： Minh V. Ngo , Khanh Q. Tran , Lu You , Jean Y. Yang , Richard J. Huang
IPC分类号： H01L21/3105 , H01L21/314 , H01L21/316 , H01L23/522 , H01L23/532
CPC分类号： H01L21/02164 , H01L21/02134 , H01L21/022 , H01L21/02211 , H01L21/02216 , H01L21/02274 , H01L21/02337 , H01L21/31051 , H01L21/316 , H01L21/31612 , H01L23/5226 , H01L23/5329 , H01L2924/0002
摘要： Patterned metal layers are gap filled with HSQ and heat soaked in an oxidizing environment prior to oxide deposition by PECVD and planarization. Heat soaking is confined to less than about 10 seconds to minimize the dielectric constant of the HSQ layer.
摘要翻译：图案化的金属层是填充有HSQ的间隙，并且在氧化物沉积之前通过PECVD和平坦化浸泡在氧化环境中的热量。热浸泡被限制在小于约10秒钟以使HSQ层的介电常数最小化。

10. 发明授权

US5888898A HSQ baking for reduced dielectric constant 失效
标题翻译： HSQ烘烤用于降低介电常数
公开(公告)号：US5888898A
公开(公告)日：1999-03-30
申请号：US956588
申请日：1997-10-23
申请人： Minh V. Ngo , Khanh Q. Tran , Terri J. Kitson , Lu You , Simon S. Chan , Jean Y. Yang
发明人： Minh V. Ngo , Khanh Q. Tran , Terri J. Kitson , Lu You , Simon S. Chan , Jean Y. Yang
IPC分类号： H01L21/314 , H01L21/316 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/4763
CPC分类号： H01L21/02134 , H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/02282 , H01L21/02337 , H01L21/316 , H01L21/31612 , H01L21/76801 , H01L21/76826 , H01L21/76828 , H01L23/5226 , H01L23/5329 , H01L2924/0002
摘要： A patterned metal layer is gap filled with HSQ, an oxide formed thereon by PECVD, e.g., silicon dioxide derived from silane and N.sub.2 O, and planarized. The dielectric constant of the HSQ layer is minimized by baking the deposited HSQ layer in an inert atmosphere, e.g., N.sub.2, before heat soaking in an N.sub.2 O-containing atmosphere for no more than about 10 seconds and subsequent PECVD.
摘要翻译：图案化的金属层是间隙填充有HSQ，其是通过PECVD在其上形成的氧化物，例如来自硅烷和N 2 O的二氧化硅，并且被平坦化。通过在惰性气氛例如N 2中烘烤沉积的HSQ层，在含N2O的气氛中热浸泡不超过约10秒并随后的PECVD之后，使HSQ层的介电常数最小化。

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