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1. 发明授权

US06309942B1 STI punch-through defects and stress reduction by high temperature oxide reflow process 有权
标题翻译： STI穿透缺陷和通过高温氧化物回流工艺的应力降低
公开(公告)号：US06309942B1
公开(公告)日：2001-10-30
申请号：US09245161
申请日：1999-02-04
申请人： Ting Y. Tsui , Robert H. Tu , Xiao-Yu Li , Sunil D. Mehta
发明人： Ting Y. Tsui , Robert H. Tu , Xiao-Yu Li , Sunil D. Mehta
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： A method of manufacturing a semiconductor device with reduced shallow trench isolation defects and stress is disclosed. The disclosed method begins by providing a silicon substrate including a capping layer. A plurality of isolation trenches are then etched through the capping layer and into the silicon substrate to form a plurality of isolation regions in the silicon substrate. The isolation trenches are then filled with an oxide layer. The oxide layer and the capping layer are then polished back using techniques known in the art. After polishing, the semiconductor device is annealed between a temperature range of about 1150° C. to about 1200° C.
摘要翻译：公开了一种制造具有减小的浅沟槽隔离缺陷和应力的半导体器件的方法。所公开的方法开始于提供包括封盖层的硅衬底。然后通过覆盖层蚀刻多个隔离沟槽并进入硅衬底，以在硅衬底中形成多个隔离区域。然后用氧化物层填充隔离沟槽。然后使用本领域已知的技术将氧化物层和覆盖层进行抛光。在抛光之后，半导体器件在约1150℃至约1200℃的温度范围内退火

2. 发明授权

US06208030B1 Semiconductor device having a low dielectric constant material 有权
标题翻译：具有低介电常数材料的半导体器件
公开(公告)号：US06208030B1
公开(公告)日：2001-03-27
申请号：US09179410
申请日：1998-10-27
申请人： Ting Y. Tsui , Ercan Adem
发明人： Ting Y. Tsui , Ercan Adem
IPC分类号： H01L2348
CPC分类号： H01L23/5329 , H01L23/5222 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： A semiconductor device having a reduced resistance-capacitance time constant is formed by treating a dielectric layer to reduce its dielectric constant. Embodiments include exposing a deposited dielectric layer to ionic radiation, as with Helium ion implantation, to form voids within the layer, thereby reducing its dielectric constant.
摘要翻译：通过处理电介质层以减小其介电常数，形成具有降低的电阻 - 电容时间常数的半导体器件。实施例包括将沉积的介电层暴露于离子辐射，如同氦离子注入一样在层内形成空隙，由此降低其介电常数。

3. 发明授权

US6053034A Method for measuring fracture toughness of thin films 失效
$Method for measuring fracture toughness of thin films$
标题翻译：测量薄膜断裂韧性的方法
公开(公告)号：US6053034A
公开(公告)日：2000-04-25
申请号：US168570
申请日：1998-10-09
申请人： Ting Y. Tsui , Young-Chang Joo
发明人： Ting Y. Tsui , Young-Chang Joo
IPC分类号： G01N3/00 , G01N3/02 , G01N3/42 , G01Q60/24 , G01N3/48
CPC分类号： G01Q60/366 , B82Y35/00 , G01N3/42 , G01N2203/0064 , G01N2203/0067 , G01N2203/027 , G01N2203/0282 , G01N2203/0286 , Y10S977/70 , Y10S977/856 , Y10S977/90
摘要： A nanoindentation apparatus is used to measure the in-plane fracture toughness of a thin film formed on a substrate. One or more notches are formed in the thin film. An indenter is applied to the thin film near the notch or notches and a load is applied to the indenter to force it into the thin film. Because the substrate is softer than the thin film, the indenter does not penetrate the thin film, but "sinks in" to the soft substrate. The sink in effect enhances the tensile strain and stress at the notch. In one embodiment, both the penetration of the indenter into the thin film and substrate and the load on the indenter are measured. When the thin film fractures at the notch or notches, the indenter sharply sinks into the substrate. The thin film fracture toughness is then calculated based on the value of the load and penetration at the point of fracture using either finite element analysis or an analytical model. In a second embodiment, the cross-section of the notch or notches is measured after removing the indenter which has formed an indentation in the thin film. The indenter acts as a crack extension force. The thin film fracture toughness is then calculated based upon the geometry of a crack tip at the tip of the notch and using finite element analysis, or an analytical model, such as a Crack Tip Opening Displacement (CTOD) method.
摘要翻译：纳米压痕装置用于测量在基板上形成的薄膜的面内断裂韧性。在薄膜中形成一个或多个凹口。将压头施加到缺口附近的薄膜或凹口，并将负载施加到压头以将其压入薄膜中。由于衬底比薄膜柔软，所以压头不穿透薄膜，而是“沉入”到柔性衬底。水槽有效地增强了缺口处的拉伸应变和应力。在一个实施例中，测量压头到薄膜和基底的穿透以及压头上的载荷。当薄膜在切口或凹口处断裂时，压头急剧下沉到基板中。然后使用有限元分析或分析模型，基于负荷点和断裂点的穿透值计算薄膜断裂韧度。在第二实施例中，在去除在薄膜中形成凹陷的压头之后，测量切口或切口的横截面。压头作为裂纹扩展力。然后基于缺口尖端处的裂纹尖端的几何形状和使用有限元分析或诸如裂纹尖端开口位移（CTOD）方法的分析模型来计算薄膜断裂韧度。

4. 发明授权

US07678713B2 Energy beam treatment to improve packaging reliability 有权
标题翻译：能量束处理提高包装可靠性
公开(公告)号：US07678713B2
公开(公告)日：2010-03-16
申请号：US11196985
申请日：2005-08-04
申请人： Ting Y. Tsui , Andrew McKerrow , Satyavolu Srinivas Papa Rao , Robert Kraft
发明人： Ting Y. Tsui , Andrew McKerrow , Satyavolu Srinivas Papa Rao , Robert Kraft
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/76825
摘要： The present invention provides a process for improving the hardness and/or modulus of elasticity of a dielectric layer and a method for manufacturing an integrated circuit. The process for improving the hardness and/or modulus of elasticity of a dielectric layer, among other steps, includes providing a dielectric layer having a hardness and a modulus of elasticity, and subjecting the dielectric layer to an energy beam, thereby causing the hardness or modulus of elasticity to increase in value.
摘要翻译：本发明提供一种提高介电层的硬度和/或弹性模量的方法以及集成电路的制造方法。提供电介质层的硬度和/或弹性模量的方法以及其它步骤包括提供具有硬度和弹性模量的电介质层，以及使电介质层经受能量束，从而使硬度或弹性模量增加值。

5. 发明授权

US07442597B2 Systems and methods that selectively modify liner induced stress 有权
标题翻译：系统和方法选择性地修改衬垫引起的应力
公开(公告)号：US07442597B2
公开(公告)日：2008-10-28
申请号：US11049275
申请日：2005-02-02
申请人： Ting Y. Tsui , Satyavolu S. Papa Rao , Haowen Bu , Robert Kraft
发明人： Ting Y. Tsui , Satyavolu S. Papa Rao , Haowen Bu , Robert Kraft
IPC分类号： H01L21/8238
CPC分类号： H01L21/76829 , H01L21/76825 , H01L21/823807 , H01L21/823828
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).
摘要翻译：本发明通过提供选择性地将应变应用于半导体器件的多个区域的制造方法来促进半导体制造。提供具有一个或多个区域的半导体器件（102）。应变诱导衬垫形成在半导体器件（104）上。将诸如光致抗蚀剂层或UV反射涂层的选择机构施加到半导体器件以选择区域（106）。选择的区域用改变由选定区域（108）产生的应力的类型和/或大小的应力改变处理来处理。

6. 发明授权

US07682989B2 Formation of a silicon oxide interface layer during silicon carbide etch stop deposition to promote better dielectric stack adhesion 有权
标题翻译：在碳化硅蚀刻停止沉积期间形成氧化硅界面层以促进更好的介电堆叠粘附
公开(公告)号：US07682989B2
公开(公告)日：2010-03-23
申请号：US11750669
申请日：2007-05-18
申请人： Laura M. Matz , Ting Y. Tsui , Thad E. Briggs , Robert Kraft
发明人： Laura M. Matz , Ting Y. Tsui , Thad E. Briggs , Robert Kraft
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/3148 , H01L21/02126 , H01L21/02164 , H01L21/02167 , H01L21/0217 , H01L21/02274 , H01L21/31608 , H01L21/3185 , H01L21/76807 , H01L21/76832 , H01L21/76834
摘要： In accordance with the present teachings, semiconductor devices and methods of making semiconductor devices and dielectric stack in an integrated circuit are provided. The method of forming a dielectric stack in an integrated circuit can include providing a semiconductor structure including one or more copper interconnects and forming an etch stop layer over the semiconductor structure in a first processing chamber. The method can also include forming a thin silicon oxide layer over the etch stop layer in the first processing chamber and forming an ultra low-k dielectric layer over the thin silicon oxide layer in a second processing chamber, wherein forming the thin silicon oxide layer improves adhesion between the etch stop layer and the ultra low-k dielectric as compared to a dielectric stack that is devoid of the thin silicon oxide layer between the etch stop layer and the ultra low-k dielectric.
摘要翻译：根据本教导，提供半导体器件以及在集成电路中制造半导体器件和电介质叠层的方法。在集成电路中形成电介质堆叠的方法可以包括提供包括一个或多个铜互连的半导体结构，并在第一处理室中在半导体结构之上形成蚀刻停止层。该方法还可以包括在第一处理室中的蚀刻停止层之上形成薄的氧化硅层，并在第二处理室中的薄氧化硅层上形成超低k电介质层，其中形成薄氧化硅层改善与在蚀刻停止层和超低k电介质之间没有薄氧化硅层的电介质堆叠相比，蚀刻停止层和超低k电介质之间的粘附性。

7. 发明申请

US20090017588A1 SYSTEMS AND METHODS THAT SELECTIVELY MODIFY LINER INDUCED STRESS 有权
标题翻译：选择性修改衬里诱发应力的系统和方法
公开(公告)号：US20090017588A1
公开(公告)日：2009-01-15
申请号：US12235766
申请日：2008-09-23
申请人： Ting Y. Tsui , Satyavolu S. Papa Rao , Haowen Bu , Robert Kraft
发明人： Ting Y. Tsui , Satyavolu S. Papa Rao , Haowen Bu , Robert Kraft
IPC分类号： H01L21/8238
CPC分类号： H01L21/76829 , H01L21/76825 , H01L21/823807 , H01L21/823828
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).
摘要翻译：本发明通过提供选择性地将应变应用于半导体器件的多个区域的制造方法来促进半导体制造。提供具有一个或多个区域的半导体器件（102）。应变诱导衬垫形成在半导体器件（104）上。将诸如光致抗蚀剂层或UV反射涂层的选择机构施加到半导体器件以选择区域（106）。选择的区域用改变由选定区域（108）产生的应力的类型和/或大小的应力改变处理来处理。

8. 发明申请

US20080283975A1 FORMATION OF A SILICON OXIDE INTERFACE LAYER DURING SILICON CARBIDE ETCH STOP DEPOSITION TO PROMOTE BETTER DIELECTRIC STACK ADHESION 有权
标题翻译：在碳化硅蚀刻停止沉积期间形成硅氧化物界面层以促进更好的电介质粘结
公开(公告)号：US20080283975A1
公开(公告)日：2008-11-20
申请号：US11750669
申请日：2007-05-18
申请人： Laura M. Matz , Ting Y. Tsui , Thad E. Briggs , Robert Kraft
发明人： Laura M. Matz , Ting Y. Tsui , Thad E. Briggs , Robert Kraft
IPC分类号： H01L21/31 , H01L23/58
CPC分类号： H01L21/3148 , H01L21/02126 , H01L21/02164 , H01L21/02167 , H01L21/0217 , H01L21/02274 , H01L21/31608 , H01L21/3185 , H01L21/76807 , H01L21/76832 , H01L21/76834
摘要： In accordance with the present teachings, semiconductor devices and methods of making semiconductor devices and dielectric stack in an integrated circuit are provided. The method of forming a dielectric stack in an integrated circuit can include providing a semiconductor structure including one or more copper interconnects and forming an etch stop layer over the semiconductor structure in a first processing chamber. The method can also include forming a thin silicon oxide layer over the etch stop layer in the first processing chamber and forming an ultra low-k dielectric layer over the thin silicon oxide layer in a second processing chamber, wherein forming the thin silicon oxide layer improves adhesion between the etch stop layer and the ultra low-k dielectric as compared to a dielectric stack that is devoid of the thin silicon oxide layer between the etch stop layer and the ultra low-k dielectric.
摘要翻译：根据本教导，提供半导体器件以及在集成电路中制造半导体器件和电介质叠层的方法。在集成电路中形成电介质堆叠的方法可以包括提供包括一个或多个铜互连的半导体结构，并在第一处理室中在半导体结构之上形成蚀刻停止层。该方法还可以包括在第一处理室中的蚀刻停止层之上形成薄的氧化硅层，并在第二处理室中的薄氧化硅层上形成超低k电介质层，其中形成薄氧化硅层改善与在蚀刻停止层和超低k电介质之间没有薄氧化硅层的电介质堆叠相比，蚀刻停止层和超低k电介质之间的粘附性。

9. 发明授权

US06583070B1 Semiconductor device having a low dielectric constant material 有权
标题翻译：具有低介电常数材料的半导体器件
公开(公告)号：US06583070B1
公开(公告)日：2003-06-24
申请号：US09778777
申请日：2001-02-08
申请人： Ting Y. Tsui , Ercan Adem
发明人： Ting Y. Tsui , Ercan Adem
IPC分类号： H01L2131
CPC分类号： H01L23/5329 , H01L23/5222 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： A semiconductor device having a reduced resistance-capacitance time constant is formed by treating a dielectric layer to reduce its dielectric constant. Embodiments include exposing a deposited dielectric layer to ionic radiation, as with Helium ion implantation, to form voids within the layer, thereby reducing its dielectric constant.
摘要翻译：通过处理电介质层以减小其介电常数，形成具有降低的电阻 - 电容时间常数的半导体器件。实施例包括将沉积的介电层暴露于离子辐射，如同氦离子注入一样在层内形成空隙，由此降低其介电常数。

10. 发明授权

US07341941B2 Methods to facilitate etch uniformity and selectivity 有权
标题翻译：促进蚀刻均匀性和选择性的方法
公开(公告)号：US07341941B2
公开(公告)日：2008-03-11
申请号：US11207493
申请日：2005-08-19
申请人： Ting Y. Tsui , Jeannette M. Jacques , Robert Kraft , Ping Jiang
发明人： Ting Y. Tsui , Jeannette M. Jacques , Robert Kraft , Ping Jiang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76825 , H01L21/76807
摘要： A semiconductor device is fabricated with energy based process(es) that alter etch rates for dielectric layers within damascene processes. A first interconnect layer is formed over a semiconductor body. A first dielectric layer is formed over the first interconnect layer. An etch rate of the first dielectric layer is altered. A second dielectric layer is formed on the first dielectric layer. An etch rate of the second dielectric layer is then altered. A trench etch is performed to form a trench cavity within the second dielectric layer. A via etch is performed to form a via cavity within the first dielectric layer. The cavities are filled with conductive material and then planarized to remove excess fill material.
摘要翻译：用基于能量的工艺制造半导体器件，其改变镶嵌工艺内的电介质层的蚀刻速率。第一互连层形成在半导体本体上。第一介电层形成在第一互连层上。改变第一介电层的蚀刻速率。在第一电介质层上形成第二电介质层。然后改变第二电介质层的蚀刻速率。执行沟槽蚀刻以在第二介电层内形成沟槽。执行通孔蚀刻以在第一介电层内形成通孔腔。空腔填充有导电材料，然后平坦化以除去多余的填充材料。

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