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1. 发明授权

US06854040B1 Non-volatile memory device with burst mode reading and corresponding reading method 有权
标题翻译：具有突发模式读取的非易失性存储器件和相应的读取方法
公开(公告)号：US06854040B1
公开(公告)日：2005-02-08
申请号：US09717938
申请日：2000-11-21
申请人： Simone Bartoli , Antonino Geraci , Mauro Sali , Lorenzo Bedarida
发明人： Simone Bartoli , Antonino Geraci , Mauro Sali , Lorenzo Bedarida
IPC分类号： G11C7/10 , G06F12/00 , G06F13/28 , G11C8/04
CPC分类号： G11C7/1072 , G11C7/1033 , G11C7/1045
摘要： A read control circuit and a reading method for an electronic memory device integrated on a semiconductor includes a non-volatile memory matrix with associated row and column decoders connected to respective outputs of an address counter. An address transition detect (ATD) circuit detects an input transition as the memory device is being accessed, and read amplifiers and attendant registers transfer the data read from the memory matrix to the output. The read control circuit includes a detection circuit to which is input a clock signal and a logic signal to enable reading in the burst mode. A burst read mode control logic circuit is connected downstream of the detection circuit. The method includes accessing the memory matrix in a random read mode, detecting a request for access in the burst read mode, and executing the parallel reading of a plurality of memory words during a single period of time clocked by the clock signal.
摘要翻译：集成在半导体上的电子存储装置的读取控制电路和读取方法包括具有连接到地址计数器的相应输出的相关联的行和列解码器的非易失性存储器矩阵。地址转换检测（ATD）电路在正在访问存储器件时检测输入转换，并且读取放大器和伴随寄存器将从存储器矩阵读取的数据传送到输出。读取控制电路包括检测电路，在该检测电路中输入时钟信号和逻辑信号，使得能够以突发模式进行读取。突发读模式控制逻辑电路连接在检测电路的下游。该方法包括以随机读取模式访问存储器矩阵，以突发读取模式检测访问请求，以及在由时钟信号计时的单个时间段内执行多个存储器字的并行读取。

2. 发明授权

US06912598B1 Non-volatile memory with functional capability of simultaneous modification of the content and burst mode read or page mode read 有权
标题翻译：具有同时修改内容和突发模式读取或页面模式读取功能的非易失性存储器
公开(公告)号：US06912598B1
公开(公告)日：2005-06-28
申请号：US09627703
申请日：2000-07-28
申请人： Lorenzo Bedarida , Antonino Geraci , Mauro Sali , Simone Bartoli
发明人： Lorenzo Bedarida , Antonino Geraci , Mauro Sali , Simone Bartoli
IPC分类号： G11C16/10 , G11C16/26 , G06F9/28 , G06F13/16
CPC分类号： G11C16/10 , G11C16/26
摘要： An electrically alterable semiconductor memory comprises at least two substantially independent memory banks, and a first control circuit for controlling operations of electrical alteration of the content of the memory. The first control circuit permits the selective execution of an operation of electrical alteration of the content of one of the at least two memory banks. The memory also comprises second control circuit that permits, simultaneously with said operation of electrical alteration of the content of one of the at least two memory banks, a burst mode, page mode, or standard read operation for reading the content of the other memory bank.
摘要翻译：一种电可更改的半导体存储器包括至少两个基本上独立的存储体，以及第一控制电路，用于控制存储器内容的电气改变的操作。第一控制电路允许选择性地执行对至少两个存储体之一的内容的电气改变的操作。存储器还包括第二控制电路，其允许同时对所述至少两个存储器组之一的内容进行电气改变的所述操作，用于读取另一个存储体的内容的突发模式，寻呼模式或标准读取操作。

3. 发明授权

US06480436B2 Non-volatile memory with a charge pump with regulated voltage 有权
标题翻译：具有调节电压的电荷泵的非易失性存储器
公开(公告)号：US06480436B2
公开(公告)日：2002-11-12
申请号：US09909467
申请日：2001-07-19
申请人： Emanuele Confalonieri , Lorenzo Bedarida , Mauro Sali , Simone Bartoli
发明人： Emanuele Confalonieri , Lorenzo Bedarida , Mauro Sali , Simone Bartoli
IPC分类号： G11C700
CPC分类号： G11C16/30
摘要： A semiconductor memory includes a plurality of memory cells connected to one another to form a matrix of memory cells. A charge pump is connected to the matrix of memory cells. A plurality of controllable connection elements are provided, with each controllable connection element connected between an output terminal of the charge pump and a respective column line. Connected to the output of the charge pump is the series connection of a first element equivalent to a controllable connection element, and a second element equivalent to a memory cell in a predetermined biasing condition. A voltage regulator is connected between the second equivalent element and the input terminal of the charge pump for regulating the output voltage therefrom based upon a voltage present between terminals of the second equivalent element.
摘要翻译：半导体存储器包括彼此连接以形成存储器单元矩阵的多个存储单元。电荷泵连接到存储器单元的矩阵。提供多个可控制的连接元件，每个可控制的连接元件连接在电荷泵的输出端和相应的列线之间。连接到电荷泵的输出端是等效于可控制连接元件的第一元件和等同于预定偏压状态下的存储器单元的第二元件的串联连接。电压调节器连接在第二等效元件和电荷泵的输入端之间，用于基于第二等效元件的端子之间存在的电压来调节其输出电压。

4. 发明授权

US06385107B1 Architecture for handling internal voltages in a non-volatile memory, particularly in a single-voltage supply type of dual-work flash memory 有权
标题翻译：用于处理非易失性存储器内部电压的架构，特别是在单电源类型的双工作闪存中
公开(公告)号：US06385107B1
公开(公告)日：2002-05-07
申请号：US09710067
申请日：2000-11-09
申请人： Lorenzo Bedarida , Simone Bartoli , Mauro Sali , Antonio Russo
发明人： Lorenzo Bedarida , Simone Bartoli , Mauro Sali , Antonio Russo
IPC分类号： G11C702
CPC分类号： G11C16/12 , G11C5/147 , G11C8/12 , G11C16/16 , G11C16/30
摘要： An architecture handles internal voltages in a non-volatile memory array which is split into at least first and second mutually independent banks. The architecture includes first and second pluralities of generators for generating at least one of the internal voltages, which are separate from each other and connected to the first and second banks, respectively, of the nonvolatile memory array; and a control system connected to the pluralities of generators to handle the correct activation of the different generators in the different conditions of the memory array operation.
摘要翻译：架构处理非易失性存储器阵列中的内部电压，其被分成至少第一和第二相互独立的存储体。该结构包括用于产生彼此分离并分别连接到非易失性存储器阵列的第一和第二组的内部电压中的至少一个的第一和第二多个发生器; 以及连接到多个发电机的控制系统，以在存储器阵列操作的不同条件下处理不同发电机的正确激活。

5. 发明授权

US06442068B1 Non-volatile memory with functional capability of burst mode read and page mode read during suspension of an operation of electrical alteration 有权
标题翻译：在电气变更操作暂停期间读取突发模式读取和页面模式的功能性能的非易失性存储器
公开(公告)号：US06442068B1
公开(公告)日：2002-08-27
申请号：US09619589
申请日：2000-07-19
申请人： Simone Bartoli , Lorenzo Bedarida , Mauro Sali , Antonio Russo
发明人： Simone Bartoli , Lorenzo Bedarida , Mauro Sali , Antonio Russo
IPC分类号： G11C1134
CPC分类号： G11C16/26 , G11C16/10 , G11C2216/20
摘要： An electrically alterable semiconductor memory includes at least two memory sectors the content of which is individually alterable, and a control circuit for controlling operations of electrical alteration of the content of the memory, permitting the selective execution of an operation of electrical alteration of the content of one of the memory sectors with the possibility of suspending the execution to permit read access to the other of the memory sectors. The control circuit is also capable of permitting, during the suspension, an operation of burst mode or page mode reading of the content of the other memory sector.
摘要翻译：电可改变的半导体存储器包括至少两个存储器扇区，其内容是可单独改变的;以及控制电路，用于控制存储器内容的电气改变的操作，允许选择性地执行对内容的电气改变的操作其中一个存储器扇区具有暂停执行以允许对另一个存储器扇区的读取访问的可能性。控制电路还能够在暂停期间允许对其他存储器扇区的内容的突发模式或页面模式读取的操作。

6. 发明授权

US06349059B1 Method for reading data from a non-volatile memory device with autodetect burst mode reading and corresponding reading circuit 失效
标题翻译：从具有自动检测突发模式读取的非易失性存储器件读取数据的方法和相应的读取电路
公开(公告)号：US06349059B1
公开(公告)日：2002-02-19
申请号：US09716746
申请日：2000-11-20
申请人： Simone Bartoli , Antonio Geraci , Mauro Sali , Lorenzo Bedarida
发明人： Simone Bartoli , Antonio Geraci , Mauro Sali , Lorenzo Bedarida
IPC分类号： G11C1604
CPC分类号： G11C7/1033 , G11C7/1045 , G11C7/1072
摘要： A method for reading data from an integrated electronic memory device including a non-volatile memory matrix includes supplying the memory with an address of a memory location where a reading is to be effected, accessing the memory matrix in a random read mode, supplying the memory with a clock signal and an address acknowledge signal (LAN), detecting a request for burst read mode access, and starting the burst reading as the clock signal shows a rising edge. A related circuit is also provided.
摘要翻译：一种用于从包括非易失性存储器矩阵的集成电子存储器件读取数据的方法包括向存储器提供要进行读取的存储器位置的地址，以随机读取模式访问存储器矩阵，提供存储器具有时钟信号和地址确认信号（LAN），检测对突发读取模式存取的请求，以及当时钟信号显示上升沿时启动突发读取。还提供了相关的电路。

7. 发明授权

US06339551B1 Semiconductor device with selectable pads 有权
标题翻译：具有可选焊盘的半导体器件
公开(公告)号：US06339551B1
公开(公告)日：2002-01-15
申请号：US09560514
申请日：2000-04-27
申请人： Simone Bartoli , Mauro Sali , Claudio Nava , Antonio Russo
发明人： Simone Bartoli , Mauro Sali , Claudio Nava , Antonio Russo
IPC分类号： G11C700
CPC分类号： G11C7/10 , G11C5/04 , G11C5/063 , G11C2207/105
摘要： A semiconductor device includes at least two pads for the input of external signals and/or for the output of signals from said semiconductor device, at least two uncoupling buffers each connected to each one of said pads, at least one multiplexer connected to said pads by means of said uncoupling buffers and at least one memory element suitable to generate a configuration signal operating on said multiplexer and said uncoupling buffers to selectively enable one or the other of said pads.
摘要翻译：半导体器件包括用于输入外部信号和/或用于输出来自所述半导体器件的信号的至少两个焊盘，至少两个非耦合缓冲器，每个至少两个非耦合缓冲器连接到每个所述焊盘，至少一个多路复用器通过所述解耦缓冲器的装置和适于产生在所述多路复用器和所述非耦合缓冲器上操作的配置信号的至少一个存储元件，以选择性地使能所述焊盘中的一个或另一个。

8. 发明申请

US20070016735A1 Flash memory device with improved management of protection information 有权
标题翻译：闪存设备具有改进的保护信息管理功能
公开(公告)号：US20070016735A1
公开(公告)日：2007-01-18
申请号：US11432301
申请日：2006-05-10
申请人： Francesco Mastroianni , Antonino Mondello , Elena Cussotto , Massimiliano Mollichelli , Mauro Sali
发明人： Francesco Mastroianni , Antonino Mondello , Elena Cussotto , Massimiliano Mollichelli , Mauro Sali
IPC分类号： G06F12/00 , G06F13/28 , G06F13/00 , G11C16/04 , G11C11/34
CPC分类号： G11C16/22 , G06F12/1433 , G06F21/6209 , G06F21/79 , G06F2212/2022
摘要： A non-volatile memory device of flash type includes first memory cells for storing data, second memory cells for storing protection information of the first memory cells, and a circuit for updating the protection information that includes a circuit for writing a plurality of versions of the protection information in the second memory cells, and a circuit for identifying a current version of the protection information.
摘要翻译：闪存类型的非易失性存储器件包括用于存储数据的第一存储器单元，用于存储第一存储器单元的保护信息的第二存储器单元，以及用于更新保护信息的电路，其包括用于写入多个版本的电路第二存储器单元中的保护信息，以及用于识别当前版本的保护信息的电路。

9. 发明授权

US5659502A Negative word line voltage regulation circuit for electrically erasable semiconductor memory devices 失效
标题翻译：用于电可擦除半导体存储器件的负字线电压调节电路
公开(公告)号：US5659502A
公开(公告)日：1997-08-19
申请号：US665862
申请日：1996-06-19
申请人： Mauro Sali , Corrado Villa , Marcello Carrera
发明人： Mauro Sali , Corrado Villa , Marcello Carrera
IPC分类号： G11C17/00 , G11C16/06 , G11C16/30 , G11C13/00
CPC分类号： G11C16/30
摘要： A negative word line voltage regulation circuit integratable in an electrically erasable semiconductor memory device. The circuit regulates a negative word line voltage to be supplied to word lines of the memory device during an electrical erasure of the memory device. The circuit includes an operational amplifier with a first input coupled to a reference voltage, a second input coupled to the negative word line voltage, and an output controlling a voltage regulation branch connected between an external power supply and the negative word line voltage, to provide a regulation current for regulating the negative word line voltage. The output of the operational amplifier also controls a voltage sensing branch, connected between the external power supply and the negative word line voltage, to provide a sensing signal coupled to the second input of the operational amplifier.
摘要翻译：可在电可擦除半导体存储器件中集成的负字线电压调节电路。电路在存储器件的电擦除期间调节要提供给存储器件的字线的负字线电压。电路包括具有耦合到参考电压的第一输入的运算放大器，耦合到负字线电压的第二输入，以及控制连接在外部电源和负字线电压之间的电压调节支路的输出，以提供用于调节负字线电压的调节电流。运算放大器的输出还控制连接在外部电源和负字线电压之间的电压感测支路，以提供耦合到运算放大器的第二输入端的感测信号。

10. 发明授权

US06320792B1 Row decoding circuit for a semiconductor non-volatile electrically programmable memory and corresponding method 有权
标题翻译：半导体非易失性电可编程存储器的行解码电路及相应的方法
公开(公告)号：US06320792B1
公开(公告)日：2001-11-20
申请号：US09633334
申请日：2000-08-07
申请人： Fabio Tassan Caser , Mauro Sali , Marcello Cane
发明人： Fabio Tassan Caser , Mauro Sali , Marcello Cane
IPC分类号： G11C1606
CPC分类号： G11C8/10 , G11C16/08
摘要： The invention relates to a row decoding circuit for an electrically programmable and erasable semiconductor non-volatile storage device of the type which includes a matrix of memory cells laid out as cell rows and columns and is divided into sectors, said circuit being input row decode signals and supply voltages in order to drive an output stage incorporating a complementary pair of high-voltage MOS transistors of the pull-up and pull-down type, respectively, which are connected to form an output terminal connected to the rows of one sector of the matrix, characterized in that a MOS transistor of the P-channel depletion type with enhanced gate oxide is provided between the output terminal and the pull-down transistor. The control terminal of the depletion transistor forms a further input of the circuit.
摘要翻译：本发明涉及一种用于电可编程和可擦除的半导体非易失性存储装置的行解码电路，该电路可编程和可擦除半导体非易失性存储装置包括布置为单元行和列的存储单元的矩阵，并被划分为扇区，所述电路是输入行解码信号和电源电压，以分别驱动并入一对互补的上拉和下拉型高压MOS晶体管的输出级，所述高压MOS晶体管被连接以形成连接到所述上拉和下拉的一个扇区的行的输出端子矩阵，其特征在于，在输出端和下拉晶体管之间提供具有增强的栅极氧化物的P沟道耗尽型的MOS晶体管。耗尽晶体管的控制端构成电路的另一输入。

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