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1. 发明授权

US06763314B2 AC defect detection and failure avoidance power up and diagnostic system 有权
标题翻译：交流缺陷检测和故障避免上电及诊断系统
公开(公告)号：US06763314B2
公开(公告)日：2004-07-13
申请号：US09967550
申请日：2001-09-28
申请人： Phillip J. Nigh , Jody J. Van Horn
发明人： Phillip J. Nigh , Jody J. Van Horn
IPC分类号： G01R3100
CPC分类号： G01R19/2513
摘要： A system for modifying the power up and diagnostic procedure of systems such that the system voltage is lowered to a predetermined voltage level that has been shown to detect delay faults. The system conducts the normal procedure of power up/diagnostic routines at the described VLV condition and then logs failures to this VLV condition. Upon completion of the VLV power up, the system is shut down normally and then subsequently powered up again at the normal voltage conditions. Discrepancies between the VLV power up/diagnostics are noted in the system log and communicated appropriately.
摘要翻译：一种用于修改系统的上电和诊断过程的系统，使得系统电压降低到已经显示为检测延迟故障的预定电压电平。系统在上述VLV条件下执行上电/诊断例程的正常程序，然后将故障记录到该VLV条件。在VLV上电完成后，系统正常关闭，然后在正常电压条件下再次上电。在系统日志中记录VLV上电/诊断之间的差异并进行适当的通信。

2. 发明授权

US06618682B2 Method for test optimization using historical and actual fabrication test data 有权
公开(公告)号：US06618682B2
公开(公告)日：2003-09-09
申请号：US09838996
申请日：2001-04-20
申请人： Raymond J. Bulaga , Anne E. Gattiker , John L. Harris , Phillip J. Nigh , Leo A. Noel , William J. Thibault , Jody J. Van Horn , Donald L. Wheater
发明人： Raymond J. Bulaga , Anne E. Gattiker , John L. Harris , Phillip J. Nigh , Leo A. Noel , William J. Thibault , Jody J. Van Horn , Donald L. Wheater
IPC分类号： G01N3700
CPC分类号： H01L22/20
摘要： A method and system are provided that minimize wafer or package level test time without adversely impacting yields in downstream manufacturing processes or degrading outgoing quality levels. The method provides optimization by determining, a priority, the most effective set of tests for a given lot or wafer. The invention implements a method using a processor-based system involving the integration of multiple sources of data that include: historical and realtime, product specific and lot specific, from wafer fabrication data (i.e., process measurements, defect inspections, and parametric testing), product qualification test results, physical failure analysis results and manufacturing functional test results. These various forms of data are used to determine an optimal set of tests to run using a test application sequence, on a given product to optimize test time with minimum risk to yield or product quality.

3. 发明授权

US06442723B1 Logic built-in self test selective signature generation 失效
标题翻译：逻辑内置自检选择性签名生成
公开(公告)号：US06442723B1
公开(公告)日：2002-08-27
申请号：US09310445
申请日：1999-05-12
申请人： Timothy J. Koprowski , Franco Motika , Phillip J. Nigh
发明人： Timothy J. Koprowski , Franco Motika , Phillip J. Nigh
IPC分类号： G01R313185
CPC分类号： G01R31/318371
摘要： LBIST resource parameters are used to control the data inputs for the signature generation process. These resource parameters include a LBIST pattern cycle counter, a channel input selected to input the MISR, and a channel load/unload shift counter. Properly setting one or more of these resource parameters to conditionally control those latch content values that get clocked into the MISR during the unload operation generates a three dimensional signature space.
摘要翻译： LBIST资源参数用于控制签名生成过程的数据输入。这些资源参数包括LBIST模式周期计数器，选择输入MISR的通道输入和通道加载/卸载移位计数器。适当地设置这些资源参数中的一个或多个以有条件地控制在卸载操作期间被计入MISR的锁存内容值产生三维签名空间。

4. 发明授权

US08176362B2 Online multiprocessor system reliability defect testing 有权
标题翻译：在线多处理器系统可靠性缺陷测试
公开(公告)号：US08176362B2
公开(公告)日：2012-05-08
申请号：US12053642
申请日：2008-03-24
申请人： Monty M Denneau , Vikram Iyengar , Phillip J. Nigh
发明人： Monty M Denneau , Vikram Iyengar , Phillip J. Nigh
IPC分类号： G06F11/00
CPC分类号： G06F11/008 , G06F11/2025 , G06F11/2028 , G06F11/2242 , G06F11/3409
摘要： A multiprocessor system comprising a plurality of processors is disclosed. The plurality of processors includes a first processor including first monitor on-chip and a second processor including a including a second monitor on-chip. The first monitor on-chip is configured to measure load on the second processor and the second monitor on-chip is configured to measure load on the first processor. The first monitor on-chip is configured to cause the second monitor on-chip to perform a self-test on the second processor if the load on the second processor is below a second processor load threshold value and the second monitor on-chip is configured to cause the first monitor on-chip to perform a self-test on the first processor if the load on the first processor is below first processor load threshold value.
摘要翻译：公开了一种包括多个处理器的多处理器系统。多个处理器包括第一处理器，其包括片上第一监视器和第二处理器，其包括在片上包括第二监视器的第二处理器。第一个片上显示器被配置为测量第二处理器上的负载，并且片上第二个监视器被配置为测量第一处理器上的负载。如果第二处理器上的负载低于第二处理器负载阈值并且片上第二监视器被配置，片上的第一个监视器被配置为使片上的第二监视器在第二处理器上执行自检如果第一处理器上的负载低于第一处理器负载阈值，则使片上的第一个监视器在第一处理器上执行自检。

5. 发明授权

US07574644B2 Functional pattern logic diagnostic method 失效
标题翻译：功能模式逻辑诊断方法
公开(公告)号：US07574644B2
公开(公告)日：2009-08-11
申请号：US11166019
申请日：2005-06-25
申请人： Donato Forlenza , Franco Molika , Phillip J. Nigh
发明人： Donato Forlenza , Franco Molika , Phillip J. Nigh
IPC分类号： G06F11/00
CPC分类号： G01R31/318586 , G01R31/318544
摘要： A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on functional failure by determining the location of the type of error in the failing circuit. This is accomplished by identifying the failing vector during the functional test, observing the states of the failed device by unloading the values of the latches from the LSSD scan chain before the failing vector, generating a LOAD from the unloaded states of the latches, applying the generated LOAD as the first event of a newly created independent LSSD deterministic pattern, applying the primary inputs and Clocks that produced the failure to a correctly operating device, unloading the output of the correctly operating device to generate a deterministic LSSD pattern; and applying the generated deterministic LSSD pattern to the failing device to diagnose the failure using existing LSSD deterministic tools.
摘要翻译：一种诊断半导体器件功能测试故障的方法，通过组合确定性和功能测试，通过确定故障电路中错误类型的位置，基于功能故障创建新的测试模式。这是通过在功能测试期间识别故障向量来实现的，通过在故障向量之前从LSSD扫描链中卸载锁存器的值来观察故障设备的状态，从锁存器的未加载状态生成LOAD，应用生成LOAD作为新创建的独立LSSD确定性模式的第一个事件，将产生故障的主输入和时钟应用于正确操作的设备，卸载正确操作设备的输出以生成确定性LSSD模式; 以及将生成的确定性LSSD模式应用于故障设备，以使用现有的LSSD确定性工具来诊断故障。

6. 发明授权

US07194706B2 Designing scan chains with specific parameter sensitivities to identify process defects 失效
标题翻译：设计具有特定参数灵敏度的扫描链，以识别过程缺陷
公开(公告)号：US07194706B2
公开(公告)日：2007-03-20
申请号：US10710642
申请日：2004-07-27
申请人： James W. Adkisson , Greg Bazan , John M. Cohn , Matthew S. Grady , Leendert M. Huisman , Mark D. Jaffe , Phillip J. Nigh , Leah M. P. Pastel , Thomas G. Sopchak , David E. Sweenor , David P. Vallett
发明人： James W. Adkisson , Greg Bazan , John M. Cohn , Matthew S. Grady , Leendert M. Huisman , Mark D. Jaffe , Phillip J. Nigh , Leah M. P. Pastel , Thomas G. Sopchak , David E. Sweenor , David P. Vallett
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G01R31/31855 , G01R31/318586 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip. The model is provided as input parameters to a global placement and wiring program used to lay out the scan chains. Test data on the chip is then analyzed to determine and isolate systematic yield problems denoted by attributes of a statistically significant failing population of a specific type of scan chain.
摘要翻译：公开了一种用于设计具有特定参数灵敏度的集成电路芯片中的扫描链的方法，以识别导致测试失败和芯片产量损失的制造工艺缺陷。集成电路芯片中的扫描路径的组成被偏置以允许它们也用作产品过程监视器。该方法增加了分组约束，使得扫描链偏置以在可能的情况下具有共同的锁存单元使用，并且还偏置小区路由以将扫描链路由限制到用于互连的给定受限金属层。该方法组合了对过程变化或完整性敏感的锁存器设计参数列表，并且制定了扫描链设计的计划，该计划确定了扫描链的数量和长度。基于产量和过程完整性的当前状态来制定扫描链设计的模型，其中为芯片上的特定扫描链选择具有主要灵敏度的某些锁存器设计。该模型作为输入参数提供给用于布置扫描链的全局放置和布线程序。然后对芯片上的测试数据进行分析，以确定和分离由特定类型的扫描链的统计学显着失败群体的属性表示的系统产量问题。

7. 发明授权

US07127690B2 Method and system for defect evaluation using quiescent power plane current (IDDQ) voltage linearity 失效
标题翻译：使用静态功率平面电流（IDDQ）电压线性度进行缺陷评估的方法和系统
公开(公告)号：US07127690B2
公开(公告)日：2006-10-24
申请号：US10728172
申请日：2003-12-03
申请人： Anne Elizabeth Gattiker , Phillip J. Nigh
发明人： Anne Elizabeth Gattiker , Phillip J. Nigh
IPC分类号： G06F17/50 , G01R19/00 , G01R31/26
CPC分类号： G01R31/3008
摘要： A method and system for defect evaluation using IDDQ voltage linearity provides improved IDDQ testing for determining whether manufacturing defects in a VLSI device are likely to cause functional faults. IDDQ data is collected at multiple power plane voltages (VDDs) for a test vector at which a fault is activated. The IDDQ vs. VDD is then examined and a range of VDDs over which the characteristic IDDQs are non-linear with respect to VDD is determined. Peaks in the first derivative of the IDDQ vs. VDD curve indicate a particular VDD at which the onset of non-linearity in the IDDQ occurs. The VDD point below which the curve is non-linear indicates the relative resistance of a fault with respect to the driving point resistance of the node at which the fault is located. The relative resistance is directly determinative of additional circuit delay cause by the fault and/or whether the fault will cause a logic level transmission failure. Therefore, the range of VDDs for which the IDDQ curve is linear provides a pass/fail indication that can be used to reject devices in manufacturing test.
摘要翻译：使用IDDQ电压线性度进行缺陷评估的方法和系统提供了改进的IDDQ测试，用于确定VLSI设备中的制造缺陷是否可能引起功能故障。 IDDQ数据在多个电源平面电压（VDD）下收集，用于启动故障的测试矢量。然后检查IDDQ与VDD，并确定特性IDDQ相对于VDD是非线性的VDD范围。 IDDQ与VDD曲线的一阶导数中的峰值表示IDDQ中发生非线性发生的特定VDD。曲线非线性以下的VDD点表示故障相对于故障位置的节点的驱动点电阻的相对电阻。相对电阻直接决定了故障引起的附加电路延迟和/或故障是否会导致逻辑电平传输故障。因此，IDDQ曲线为线性的VDD的范围提供了可用于在制造测试中拒绝器件的通过/失败指示。

8. 发明授权

US06751765B1 Method and system for determining repeatable yield detractors of integrated circuits 失效
标题翻译：用于确定集成电路的可重复产量剔除器的方法和系统
公开(公告)号：US06751765B1
公开(公告)日：2004-06-15
申请号：US09722880
申请日：2000-11-27
申请人： Richard F. Rizzolo , Rocco E. DeStefano , Joseph E. Eckelman , Thomas G. Foote , Steven Michnowski , Franco Motika , Phillip J. Nigh , Bryan J. Robbins
发明人： Richard F. Rizzolo , Rocco E. DeStefano , Joseph E. Eckelman , Thomas G. Foote , Steven Michnowski , Franco Motika , Phillip J. Nigh , Bryan J. Robbins
IPC分类号： G01R3128
CPC分类号： G01R31/3185
摘要： An exemplary embodiment of the invention is a method for LBIST testing integrated circuit. The method includes generating a plurality of multi-bit test patterns and grouping the multi-bit test patterns by a plurality of test pattern partitions including a first test pattern partition having a first number of bits and a second test pattern partition having second number of bits greater than the first number. The first test pattern partition is applied to the integrated circuit to generate a first signature that is compared to a first reference signature to detect a failure. The second test pattern partition is applied to the integrated circuit to generate a second signature that is compared to a second reference signature to detect a failure in the integrated circuit.
摘要翻译：本发明的示例性实施例是用于LBIST测试集成电路的方法。该方法包括生成多个多位测试模式，并且通过多个测试模式分区对多位测试模式进行分组，所述多个测试模式分区包括具有第一数量位的第一测试模式分区和具有第二数量位的第二测试模式分区大于第一个数字。将第一测试模式分区应用于集成电路以生成与第一参考签名进行比较以检测故障的第一签名。将第二测试模式分区应用于集成电路以产生与第二参考签名进行比较的第二签名，以检测集成电路中的故障。

9. 发明授权

US06650768B1 Using time resolved light emission from VLSI circuit devices for navigation on complex systems 失效
标题翻译：使用VLSI电路设备的时间分辨光发射在复杂系统上进行导航
公开(公告)号：US06650768B1
公开(公告)日：2003-11-18
申请号：US09026288
申请日：1998-02-19
申请人： Richard James Evans , Jeffrey Alan Kash , Daniel Ray Knebel , Phillip J Nigh , Pia Naoko Sanda , James Chen-Hsiang Tsang , David Paul Vallett
发明人： Richard James Evans , Jeffrey Alan Kash , Daniel Ray Knebel , Phillip J Nigh , Pia Naoko Sanda , James Chen-Hsiang Tsang , David Paul Vallett
IPC分类号： G06K900
CPC分类号： G01R31/311
摘要： A system and method for determining the location of a particular device on an integrated circuit chip is described. The system and method utilize apparatus for detecting the emission of light during switching events of devices in the circuit during the circuit's processing of an input calculated to actuate the device whose location is desired. Light emissions from the circuit can be temporally and spatially indexed so as to allow deduction, in combination with the a priori knowledge of the logical operation of the circuit, of the location of the desired element. In another embodiment of the invention, a series of images of the circuit can be accumulated, representing the circuit's response to a series of different input signals, each input signal being designed to result in the switching of the desired element. The series of images can be compared to determine the location of the desired element. Also in accordance with the invention, the elements to be located can be either actual functional circuit elements, or fiducials added to the chip for test purposes.
摘要翻译：描述用于确定集成电路芯片上的特定装置的位置的系统和方法。该系统和方法利用在电路处理计算出的驱动所需位置的装置的输入的处理期间检测电路中装置的切换事件期间发光的装置。来自电路的光发射可以在时间上和空间上被索引，以便结合对电路的逻辑操作的先验知识来扣除所需元件的位置。在本发明的另一个实施例中，可以累积电路的一系列图像，表示电路对一系列不同输入信号的响应，每个输入信号被设计成导致期望元件的切换。可以比较一系列图像以确定所需元素的位置。同样根据本发明，待设置的元件可以是实际的功能电路元件，或者为了测试目的添加到芯片的基准。

10. 发明授权

US06516432B1 AC scan diagnostic method 失效
标题翻译： AC扫描诊断方法
公开(公告)号：US06516432B1
公开(公告)日：2003-02-04
申请号：US09469699
申请日：1999-12-22
申请人： Franco Motika , Phillip J. Nigh , Peilin Song , Howard B. Druckerman
发明人： Franco Motika , Phillip J. Nigh , Peilin Song , Howard B. Druckerman
IPC分类号： G01R3128
CPC分类号： G01R31/318577
摘要： Disclosed is an alternating current (AC) scan diagnostic system in which one or a plurality of scan chains are tested by serially propagating predetermined bit patterns through the scan chain and comparing the output against an expected result. The system comprises identification phase, verifications and localization, and a characterization phases. The system is adaptable for use with on-board diagnostics and is adaptable for use with on-product clock generation systems.
摘要翻译：公开了一种交流（AC）扫描诊断系统，其中一个或多个扫描链通过通过扫描链串行传播预定位图案并将输出与预期结果进行比较来测试。该系统包括识别阶段，验证和定位以及特征化阶段。该系统适用于车载诊断，适用于产品上的时钟发生系统。

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