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1. 发明申请

US20180364305A1 SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS 审中-公开
公开(公告)号：US20180364305A1
公开(公告)日：2018-12-20
申请号：US16108761
申请日：2018-08-22
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177 , G01R31/317 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/3172 , G01R31/31723 , G01R31/31725 , G01R31/31727 , G01R31/318536 , G01R31/318572 , G01R31/318577
摘要： Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

2. 发明授权

US09684033B2 Low power scan path cells with hold state multiplexer circuitry 有权
公开(公告)号：US09684033B2
公开(公告)日：2017-06-20
申请号：US15270746
申请日：2016-09-20
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Lee D. Whetsel
IPC分类号： G01R31/317 , G01R31/3185 , G01R31/3177
CPC分类号： G01R31/318536 , G01R31/31721 , G01R31/31723 , G01R31/3177 , G01R31/318575 , G01R31/318577
摘要： Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

3. 发明授权

US09383403B2 TSVs connected to ground and combined stimulus and testing leads 有权
标题翻译：连接到地面的TSV和组合的刺激和测试线索
公开(公告)号：US09383403B2
公开(公告)日：2016-07-05
申请号：US13785284
申请日：2013-03-05
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel , Baher S. Haroun
IPC分类号： G01R31/26 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/26 , G01R31/31723 , G01R31/318505 , G01R31/318577
摘要： This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.
摘要翻译：本公开描述了一种用于测试半导体器件内的TSV的新颖方法和装置。根据本公开中所示和描述的实施例，可以通过刺激和测量来自TSV的第一端的响应来测试TSV，同时TSV的第二端保持在地电位。根据本公开，可以并行测试半导体器件内的多个TSV以减少TSV测试时间。

4. 发明授权

US09134374B2 Circuit and method for measuring delays between edges of signals of a circuit 有权
标题翻译：用于测量电路信号边缘之间的延迟的电路和方法
公开(公告)号：US09134374B2
公开(公告)日：2015-09-15
申请号：US14222362
申请日：2014-03-21
申请人： Mentor Graphics Corporation
发明人： Stephen Kenneth Sunter
IPC分类号： G01R31/3177 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/318577
摘要： Various aspects of the present invention relate to techniques of measuring delays between edges of signals of a circuit. Alternating signals, synchronous to a first clock, are supplied to a plurality of nodes of the circuit. First samples of a plurality of signals associated with the alternating signals are captured using a first capture clock, of which sampling instants are synchronous to a second clock. Second samples of the first samples are then captured using a second capture clock, of which sampling instants are also synchronous to the second clock. The captured second samples are conveyed via a shift register to a plurality of modulo counters. The measured signal delay includes a timing skew associated with the first clock and a timing skew of the first capture clock but not a timing skew of the second capture clock.
摘要翻译：本发明的各个方面涉及测量电路的信号边缘之间的延迟的技术。与第一时钟同步的交替信号被提供给电路的多个节点。使用第一捕获时钟捕获与交替信号相关联的多个信号的第一样本，其中采样时刻与第二时钟同步。然后使用第二捕获时钟捕获第一采样的第二采样，其中采样时刻也与第二时钟同步。捕获的第二样本经由移位寄存器传送到多个模计数器。测量的信号延迟包括与第一时钟相关联的定时偏移和第一捕获时钟的定时偏移，但不包括第二捕获时钟的定时偏移。

5. 发明申请

US20140250342A1 AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL 审中-公开
标题翻译：使用外部控制的低功率自动扫描分区
公开(公告)号：US20140250342A1
公开(公告)日：2014-09-04
申请号：US14279989
申请日：2014-05-16
申请人： Texas Instruments Incorporated
发明人： Jayashree Saxena , Lee D. Whetsel
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/31721 , G01R31/318563 , G01R31/318575 , G01R31/318577 , G06F1/3234
摘要： Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.
摘要翻译：扫描架构通常用于测试集成电路中的数字电路。本发明描述了一种使常规扫描架构适应于低功率扫描架构的方法。低功耗扫描架构保持常规扫描架构的测试时间，同时要求比传统扫描架构明显更低的运行能力。低功耗扫描架构对于IC /模具制造商是有利的，因为它允许并行测试嵌入在IC /管芯中的更多数量的电路（例如DSP或CPU核心电路），而不会消耗IC /管芯内的太多功率。由于低功耗扫描架构降低了测试功耗，因此可以使用传统的扫描架构在以前可能的同时测试晶片上的更多裸片。这允许减少晶片测试时间，这降低了晶片上每个芯片的制造成本。

6. 发明申请

US20140195196A1 CHIP PERFORMANCE MONITORING SYSTEM AND METHOD 有权
标题翻译：芯片性能监控系统和方法
公开(公告)号：US20140195196A1
公开(公告)日：2014-07-10
申请号：US13737168
申请日：2013-01-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Margaret R. Charlebois , Christopher D. Hanudel , Robert D. Herzl , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Tad J. Wilder
IPC分类号： G06F11/30 , G06F1/08
CPC分类号： G01R31/3177 , G01R31/31727 , G01R31/318577 , G06F1/08 , G06F11/348
摘要： Disclosed are a chip performance monitoring system, method and a computer program product, wherein a performance monitor output signal is propagated through an adjacent scan chain to avoid signal degradation incident to across-chip transmission of high frequency signals. Since the clock signal frequency used to control signal propagation through the scan chain will typically be less than twice the performance monitor output signal frequency, frequency sub-sampling with aliasing occurs. To compensate, signal propagation through the scan chain can be controlled during different time periods using different clock signals having different clock signal frequencies and, during these different time periods, different data outputs can be captured at an output node of the scan chain. The data output frequencies of these different data outputs can be measured and the performance monitor output signal frequency can be determined based on the different data output frequencies given the different clock signal frequencies.
摘要翻译：公开了一种芯片性能监视系统，方法和计算机程序产品，其中性能监视器输出信号通过相邻扫描链传播，以避免信号降级入射到高频信号的跨芯片传输。由于用于控制通过扫描链的信号传播的时钟信号频率通常将小于性能监视器输出信号频率的两倍，因此会发生具有混叠的频率子采样。为了补偿，可以在不同的时间周期期间使用具有不同时钟信号频率的不同时钟信号来控制通过扫描链的信号传播，并且在这些不同的时间周期期间，可以在扫描链的输出节点捕获不同的数据输出。可以测量这些不同数据输出的数据输出频率，并且可以基于给定不同时钟信号频率的不同数据输出频率来确定性能监视器输出信号频率。

7. 发明申请

US20130339773A1 AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL 有权
标题翻译：使用外部控制的低功率自动扫描分区
公开(公告)号：US20130339773A1
公开(公告)日：2013-12-19
申请号：US13969063
申请日：2013-08-16
申请人： Texas Instruments Incorporated
发明人： Jayashree Saxena , Lee D. Whetsel
IPC分类号： G06F1/32
CPC分类号： G01R31/3177 , G01R31/31721 , G01R31/318563 , G01R31/318575 , G01R31/318577 , G06F1/3234
摘要： Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.
摘要翻译：扫描架构通常用于测试集成电路中的数字电路。本发明描述了一种使常规扫描架构适应于低功率扫描架构的方法。低功耗扫描架构保持常规扫描架构的测试时间，同时要求比传统扫描架构明显更低的运行能力。低功耗扫描架构对于IC /模具制造商是有利的，因为它允许并行测试嵌入在IC /管芯中的更多数量的电路（例如DSP或CPU核心电路），而不会消耗IC /管芯内的太多功率。由于低功耗扫描架构降低了测试功耗，因此可以使用传统的扫描架构在以前可能的同时测试晶片上的更多裸片。这允许减少晶片测试时间，这降低了晶片上每个芯片的制造成本。

8. 发明授权

US08539294B2 Decode logic driving segmented scan cells with clocks and enables 有权
标题翻译：解码逻辑驱动具有时钟的分段扫描单元并启用
公开(公告)号：US08539294B2
公开(公告)日：2013-09-17
申请号：US13657082
申请日：2012-10-22
申请人： Texas Instruments Incorporated
发明人： Jayashree Saxena , Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/31721 , G01R31/318563 , G01R31/318575 , G01R31/318577 , G06F1/3234
摘要： Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.
摘要翻译：扫描架构通常用于测试集成电路中的数字电路。本发明描述了一种使常规扫描架构适应于低功率扫描架构的方法。低功耗扫描架构保持常规扫描架构的测试时间，同时要求比传统扫描架构明显更少的运行能力。低功耗扫描架构对于IC /模具制造商是有利的，因为它允许并行测试嵌入在IC /管芯中的更多数量的电路（例如DSP或CPU核心电路），而不会消耗IC /管芯内的太多功率。由于低功耗扫描架构降低了测试功耗，因此可以使用传统的扫描架构在以前可能的同时测试晶片上的更多裸片。这允许减少晶片测试时间，这降低了晶片上每个芯片的制造成本。

9. 发明授权

US08453098B2 Scan chain modification for reduced leakage 有权
公开(公告)号：US08453098B2
公开(公告)日：2013-05-28
申请号：US12383902
申请日：2009-03-30
申请人： Razak Hossain
发明人： Razak Hossain
IPC分类号： G06F17/50
CPC分类号： G01R31/3177 , G01R31/318575 , G01R31/318577
摘要： A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is designed to configure the circuit elements into states in which leakage currents are reduced. A multiplexer selects the power control vector for loading into the scan chain elements, and a clock generator clocks the configuration vector into the scan chain elements. A sleep mode detector may be provided to configure the multiplexer to select the power control vector and to operate the clock generator to clock the power control vector into the scan chain elements when a sleep mode of the circuit is detected.

10. 发明授权

US08407539B2 Semiconductor device test circuit, semiconductor device, and its manufacturing method 失效
标题翻译：半导体器件测试电路，半导体器件及其制造方法
公开(公告)号：US08407539B2
公开(公告)日：2013-03-26
申请号：US12656974
申请日：2010-02-22
申请人： Satoshi Ishizuka
发明人： Satoshi Ishizuka
IPC分类号： G01R31/28
CPC分类号： G01R31/318577
摘要： The test circuit can apply a stress to each node of each object combinational circuit in the semiconductor device and suppress the semiconductor circuit overhead when in burn-in or leak test operations for the semiconductor device while it has been impossible to apply such a stress to any of such nodes only with use of an F/F circuit in any conventional environments. The test circuit is disposed in the semiconductor and combined with first and second combinational circuits therein. In the semiconductor device, a transfer gate switch is connected between first and second nodes and a first transistor is connected between the second node and a power supply. The second transistor is connected between the second node and a ground. Each of the transfer gate switch and the first and second transistors operates according to at least one of the control signals supplied from outside the semiconductor device.
摘要翻译：测试电路可以对半导体器件中的每个物体组合电路的每个节点施加应力，并且当在半导体器件的老化或泄漏测试操作中抑制半导体电路的开销，而不可能将这样的应力施加到任何的这种节点仅在任何常规环境中使用F / F电路。测试电路设置在半导体中并与其中的第一和第二组合电路组合。在半导体器件中，传输栅极开关连接在第一和第二节点之间，第一晶体管连接在第二节点和电源之间。第二晶体管连接在第二节点和地之间。传输门开关和第一和第二晶体管中的每一个根据从半导体器件的外部提供的至少一个控制信号进行工作。

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