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1. 发明申请

US20180321307A1 WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE 审中-公开
公开(公告)号：US20180321307A1
公开(公告)日：2018-11-08
申请号：US16026721
申请日：2018-07-03
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177 , G01R31/317 , G01R31/3185 , G01R31/3187 , G06F1/32 , G01R31/28
CPC分类号： G01R31/3177 , G01R31/2884 , G01R31/31721 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/318511 , G01R31/318533 , G01R31/318544 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318572 , G01R31/318575 , G01R31/318577 , G01R31/318583 , G01R31/3187 , G06F1/3234
摘要： Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

2. 发明申请

US20180128875A1 WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE 审中-公开
公开(公告)号：US20180128875A1
公开(公告)日：2018-05-10
申请号：US15863147
申请日：2018-01-05
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177 , G01R31/317 , G01R31/3185 , G01R31/3187 , G01R31/28 , G06F1/32
CPC分类号： G01R31/3177 , G01R31/2884 , G01R31/31721 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/318511 , G01R31/318533 , G01R31/318544 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318572 , G01R31/318575 , G01R31/318577 , G01R31/318583 , G01R31/3187 , G06F1/3234
摘要： Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuity, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

3. 发明申请

US20170139005A1 WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE 审中-公开
公开(公告)号：US20170139005A1
公开(公告)日：2017-05-18
申请号：US15419379
申请日：2017-01-30
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177 , G01R31/317
CPC分类号： G01R31/3177 , G01R31/2884 , G01R31/31721 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/318511 , G01R31/318533 , G01R31/318544 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318572 , G01R31/318575 , G01R31/318577 , G01R31/318583 , G01R31/3187 , G06F1/3234
摘要： Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

4. 发明授权

US09638742B2 Method and apparatus for testing electrical connections on a printed circuit board 有权
公开(公告)号：US09638742B2
公开(公告)日：2017-05-02
申请号：US13122347
申请日：2009-11-13
申请人： Anthony J. Suto
发明人： Anthony J. Suto
IPC分类号： G01R31/20 , G01R31/28 , G01R31/312 , G01R31/304 , G01R31/3185
CPC分类号： G01R31/2815 , G01R31/304 , G01R31/312 , G01R31/318577 , Y10T29/49124
摘要： A test system and method for identifying open and shorted connections on a printed circuit board (PCB). An integrated circuit (IC) unit on the PCB is configured to generate a test signal on an output pin connected to a test pin on a second device, connector, or socket on the PCB. For a connection, the test signal is capacitively coupled to a detector plate proximal the second device. Based on the signal coupled to the detector, time domain analysis is performed on the coupled signal to determine if the test pin has a good connection to the PCB or if the pin is open or shorted. Analysis may include cross-correlating the coupled signal with a learned signal obtained from a known “good” PCB. The test pin may pass the test if the cross-correlation is within a specified threshold window. If the test fails, additional tests may be performed to troubleshoot the cause of the testing failure.

5. 发明授权

US09482717B2 Wafer scale testing using a 2 signal JTAG interface 有权
公开(公告)号：US09482717B2
公开(公告)日：2016-11-01
申请号：US14934451
申请日：2015-11-06
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/3187 , G01R31/3177 , G01R31/317 , G06F1/32
CPC分类号： G01R31/3177 , G01R31/2884 , G01R31/31721 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/318511 , G01R31/318533 , G01R31/318544 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318572 , G01R31/318575 , G01R31/318577 , G01R31/318583 , G01R31/3187 , G06F1/3234
摘要： Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

6. 发明申请

US20150355276A1 ADAPTING SCAN ARCHITECTURES FOR LOW POWER OPERATION 审中-公开
标题翻译：适应低功耗操作的扫描架构
公开(公告)号：US20150355276A1
公开(公告)日：2015-12-10
申请号：US14822328
申请日：2015-08-10
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177
CPC分类号： G01R31/318536 , G01R31/31721 , G01R31/31723 , G01R31/3177 , G01R31/318575 , G01R31/318577
摘要： Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.
摘要翻译：扫描架构通常用于测试集成电路中的数字电路。本公开描述了将常规扫描架构适应成低功耗扫描架构的方法。低功耗扫描架构保持常规扫描架构的测试时间，同时要求比传统扫描架构明显更低的运行能力。低功耗扫描架构对于IC /模具制造商是有利的，因为它允许并行测试嵌入在IC /管芯中的更多数量的电路（例如DSP或CPU核心电路），而不会消耗IC /管芯内的太多功率。由于低功耗扫描架构降低了测试功耗，因此可以使用传统的扫描架构在先前可能的同时在晶圆上测试更多的裸片。这允许减少晶片测试时间，这降低了晶片上每个芯片的制造成本。

7. 发明授权

US08855962B2 System for testing electronic circuits 有权
标题翻译：电子电路测试系统
公开(公告)号：US08855962B2
公开(公告)日：2014-10-07
申请号：US13401847
申请日：2012-02-22
申请人： Deepak Jindal
发明人： Deepak Jindal
IPC分类号： G06F19/00 , G01R31/3185 , G01R31/317 , G01R31/3177 , G05B1/00 , G01R31/3163 , G01R31/30 , G01R31/28
CPC分类号： G05B1/00 , G01R31/28 , G01R31/30 , G01R31/3163 , G01R31/31721 , G01R31/3177 , G01R31/318536 , G01R31/318575 , G01R31/318577 , G05B2219/14075
摘要： A system for testing electronic circuits includes first, second, and third standard interfaces. A test port master and a test port slave are connected to an external testing apparatus. The first, second, and third standard interfaces are tested in first, second, and third test modes, respectively. The tests are initiated by asserting a test mode activate and first, second, and third test mode enable signals, respectively, which enable reuse of test patterns across different electronic circuits.
摘要翻译：用于测试电子电路的系统包括第一，第二和第三标准接口。测试端口主机和测试端口从站连接到外部测试设备。分别在第一，第二和第三测试模式中测试第一，第二和第三标准接口。测试通过分别确定测试模式激活和第一，第二和第三测试模式使能信号来启动，这使得能够跨越不同的电子电路重复使用测试模式。

8. 发明授权

US08826091B2 Die with DIO path, clock input, TLM, and TAP domains 有权
标题翻译： DIO路径，时钟输入，TLM和TAP域
公开(公告)号：US08826091B2
公开(公告)日：2014-09-02
申请号：US13175484
申请日：2011-07-01
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/28 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/2884 , G01R31/31721 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/318511 , G01R31/318533 , G01R31/318544 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318572 , G01R31/318575 , G01R31/318577 , G01R31/318583 , G01R31/3187 , G06F1/3234
摘要： Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.
摘要翻译：晶片上晶片的测试是通过以下方式实现的：（1）向测试人员提供使用同时双向收发器电路外部传送JTAG测试信号的能力;（2）使用同时双向收发器电路在晶片上提供外部传送JTAG测试信号的能力，以及（3）提供连接测试器的双向收发器电路与晶片上所选择的组或晶片上的所有芯片之间的机制，用于通信JTAG信号。

9. 发明授权

US08812918B2 Method and apparatus for evaluating and optimizing a signaling system 有权
标题翻译：用于评估和优化信号系统的方法和装置
公开(公告)号：US08812918B2
公开(公告)日：2014-08-19
申请号：US13290926
申请日：2011-11-07
申请人： Jared Zerbe , Pak Shing Chau , William Franklin Stonecypher
发明人： Jared Zerbe , Pak Shing Chau , William Franklin Stonecypher
IPC分类号： G01R31/28 , H04B17/00 , H04L1/24 , H04L1/00 , H04L5/14 , G01R31/3183 , G06F11/22 , G11C29/02 , G11C29/40 , H04B3/32 , G01R31/3185 , G01R31/3187 , G01R31/317
CPC分类号： H04L1/244 , G01R31/31703 , G01R31/31713 , G01R31/31716 , G01R31/31717 , G01R31/3183 , G01R31/31855 , G01R31/318577 , G01R31/3187 , G06F11/221 , G06F11/26 , G06F13/423 , G11C29/02 , G11C29/022 , G11C29/025 , G11C29/40 , H04B1/04 , H04B1/16 , H04B3/32 , H04B17/0085 , H04L1/0001 , H04L1/242 , H04L1/243 , H04L5/1438 , H04L25/03885
摘要： A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.
摘要翻译：描述了用于评估和优化信令系统的方法和装置。在系统的发送电路中产生测试信息的模式，并将其发送到接收电路。在接收电路中产生类似的信息模式并用作参考。接收电路比较图案。模式之间的任何差异是可观察的。在一个实施例中，实现线性反馈移位寄存器（LFSR）以产生模式。本公开的实施例可以用各种类型的信令系统来实施，包括具有单端信号和具有差分信号的信令系统。本公开的实施例可以应用于在给定时间在单个导体上传送单个信息位的系统以及同时在单个导体上传送多个信息位的系统。

10. 发明授权

US08769358B2 Decoder providing separate clock and enable for scan path segments 有权
标题翻译：解码器为扫描路径段提供单独的时钟和启用
公开(公告)号：US08769358B2
公开(公告)日：2014-07-01
申请号：US13969063
申请日：2013-08-16
申请人： Texas Instruments Incorporated
发明人： Jayashree Saxena , Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/31721 , G01R31/318563 , G01R31/318575 , G01R31/318577 , G06F1/3234
摘要： Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.
摘要翻译：扫描架构通常用于测试集成电路中的数字电路。本发明描述了一种使常规扫描架构适应于低功率扫描架构的方法。低功耗扫描架构保持常规扫描架构的测试时间，同时要求比传统扫描架构明显更低的运行能力。低功耗扫描架构对于IC /模具制造商是有利的，因为它允许并行测试嵌入在IC /管芯中的更多数量的电路（例如DSP或CPU核心电路），而不会消耗IC /管芯内的太多功率。由于低功耗扫描架构降低了测试功耗，因此可以使用传统的扫描架构在先前可能的同时在晶圆上测试更多的裸片。这允许减少晶片测试时间，这降低了晶片上每个芯片的制造成本。

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