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1. 发明授权

US06618682B2 Method for test optimization using historical and actual fabrication test data 有权
公开(公告)号：US06618682B2
公开(公告)日：2003-09-09
申请号：US09838996
申请日：2001-04-20
申请人： Raymond J. Bulaga , Anne E. Gattiker , John L. Harris , Phillip J. Nigh , Leo A. Noel , William J. Thibault , Jody J. Van Horn , Donald L. Wheater
发明人： Raymond J. Bulaga , Anne E. Gattiker , John L. Harris , Phillip J. Nigh , Leo A. Noel , William J. Thibault , Jody J. Van Horn , Donald L. Wheater
IPC分类号： G01N3700
CPC分类号： H01L22/20
摘要： A method and system are provided that minimize wafer or package level test time without adversely impacting yields in downstream manufacturing processes or degrading outgoing quality levels. The method provides optimization by determining, a priority, the most effective set of tests for a given lot or wafer. The invention implements a method using a processor-based system involving the integration of multiple sources of data that include: historical and realtime, product specific and lot specific, from wafer fabrication data (i.e., process measurements, defect inspections, and parametric testing), product qualification test results, physical failure analysis results and manufacturing functional test results. These various forms of data are used to determine an optimal set of tests to run using a test application sequence, on a given product to optimize test time with minimum risk to yield or product quality.

2. 发明授权

US06763314B2 AC defect detection and failure avoidance power up and diagnostic system 有权
标题翻译：交流缺陷检测和故障避免上电及诊断系统
公开(公告)号：US06763314B2
公开(公告)日：2004-07-13
申请号：US09967550
申请日：2001-09-28
申请人： Phillip J. Nigh , Jody J. Van Horn
发明人： Phillip J. Nigh , Jody J. Van Horn
IPC分类号： G01R3100
CPC分类号： G01R19/2513
摘要： A system for modifying the power up and diagnostic procedure of systems such that the system voltage is lowered to a predetermined voltage level that has been shown to detect delay faults. The system conducts the normal procedure of power up/diagnostic routines at the described VLV condition and then logs failures to this VLV condition. Upon completion of the VLV power up, the system is shut down normally and then subsequently powered up again at the normal voltage conditions. Discrepancies between the VLV power up/diagnostics are noted in the system log and communicated appropriately.
摘要翻译：一种用于修改系统的上电和诊断过程的系统，使得系统电压降低到已经显示为检测延迟故障的预定电压电平。系统在上述VLV条件下执行上电/诊断例程的正常程序，然后将故障记录到该VLV条件。在VLV上电完成后，系统正常关闭，然后在正常电压条件下再次上电。在系统日志中记录VLV上电/诊断之间的差异并进行适当的通信。

3. 发明授权

US06442723B1 Logic built-in self test selective signature generation 失效
标题翻译：逻辑内置自检选择性签名生成
公开(公告)号：US06442723B1
公开(公告)日：2002-08-27
申请号：US09310445
申请日：1999-05-12
申请人： Timothy J. Koprowski , Franco Motika , Phillip J. Nigh
发明人： Timothy J. Koprowski , Franco Motika , Phillip J. Nigh
IPC分类号： G01R313185
CPC分类号： G01R31/318371
摘要： LBIST resource parameters are used to control the data inputs for the signature generation process. These resource parameters include a LBIST pattern cycle counter, a channel input selected to input the MISR, and a channel load/unload shift counter. Properly setting one or more of these resource parameters to conditionally control those latch content values that get clocked into the MISR during the unload operation generates a three dimensional signature space.
摘要翻译： LBIST资源参数用于控制签名生成过程的数据输入。这些资源参数包括LBIST模式周期计数器，选择输入MISR的通道输入和通道加载/卸载移位计数器。适当地设置这些资源参数中的一个或多个以有条件地控制在卸载操作期间被计入MISR的锁存内容值产生三维签名空间。

4. 发明授权

US06998866B1 Circuit and method for monitoring defects 失效
标题翻译：电路和缺陷监测方法
公开(公告)号：US06998866B1
公开(公告)日：2006-02-14
申请号：US10710640
申请日：2004-07-27
申请人： Greg Bazan , John M. Cohn , Matthew S. Grady , Phillip J. Nigh , Leah M. P. Pastel , Thomas G. Sopchak
发明人： Greg Bazan , John M. Cohn , Matthew S. Grady , Phillip J. Nigh , Leah M. P. Pastel , Thomas G. Sopchak
IPC分类号： G01R31/26
CPC分类号： H01L22/34 , G01R31/31855 , H01L2924/0002 , H01L2924/00
摘要： A circuit and a method for monitoring defects in an integrated circuit chip. The circuit including a defect monitor portion and a sense element portion, the defect monitor portion either coupled to inputs of sense elements arranged in a chain or coupled between sense elements and forming portions of the chain.
摘要翻译：用于监测集成电路芯片中的缺陷的电路和方法。所述电路包括缺陷监测部分和感测元件部分，所述缺陷监测部分耦合到布置在链中的感测元件的输入或耦合在感测元件和链的形成部分之间。

5. 发明授权

US06961886B2 Diagnostic method for structural scan chain designs 失效
标题翻译：结构扫描链设计的诊断方法
公开(公告)号：US06961886B2
公开(公告)日：2005-11-01
申请号：US10249513
申请日：2003-04-16
申请人： Franco Motika , Phillip J. Nigh , Phong T. Tran
发明人： Franco Motika , Phillip J. Nigh , Phong T. Tran
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318566 , G01R31/318569
摘要： A method for testing and diagnosing shift register latch chains coupled to logic circuits in an integrated circuit, the method including: (a) determining which of the shift register latch chains are failing by propagating a test pattern of zeros and ones through the shift register latch chains while gating which of the shift register latch chains contents are propagated into the means for generating a test signature; and (b) for each failing shift register latch chain: (b1) propagating a test pattern through the shift register latch chains while gating a selected sequential group of latches in a failing shift register latch to propagate into the means for generating a test signature; (b2) reducing the number of latches in the sequential group of latches; and (b3) repeating steps (b1) and (b2) until all failing latches of the failing shift register latch chain have been determined.
摘要翻译：一种用于测试和诊断耦合到集成电路中的逻辑电路的移位寄存器锁存链的方法，所述方法包括：（a）通过通过移位寄存器锁存器传播零和一个测试模式来确定移位寄存器锁存链中的哪一个失败同时选通移位寄存器锁链内容中的哪一个内容被传播到用于生成测试签名的装置中; 和（b）对于每个失败的移位寄存器锁存链：（b 1）通过移位寄存器锁存链传播测试模式，同时选通故障移位寄存器锁存器中的所选顺序锁存器组，以传播到生成测试签名的装置 ; （b 2）减少锁存器序列组中的锁存器数量; 和（b 3）重复步骤（b 1）和（b 2），直到确定了故障移位寄存器锁存链的所有故障锁存器。

6. 发明授权

US5930270A Logic built in self-test diagnostic method 失效
标题翻译：逻辑内置自检诊断方法
公开(公告)号：US5930270A
公开(公告)日：1999-07-27
申请号：US898942
申请日：1997-07-23
申请人： Donato O. Forlenza , Franco Motika , John J. Shushereba , Phillip J. Nigh
发明人： Donato O. Forlenza , Franco Motika , John J. Shushereba , Phillip J. Nigh
IPC分类号： G01R31/3177 , G01R31/3185 , G06F11/22 , G01R31/28 , G06F11/00
CPC分类号： G06F11/2268 , G01R31/3177 , G01R31/318566 , G01R31/31816
摘要： A system and method for diagnosing the faults of an electronic device by running a series of tests, identifying the tests where the electronic device failed, without having to check the results of each test, storing information generated during only the tests where the electronic device failed, and using the information to diagnose the faults in the electronic device. The test results are accumulated into a Multiple Input Shift Register (MISR) which need not be examined after each test to determine which tests the device failed. The problem of a failure during one test manifesting into the MISR during subsequent tests is handled by predicting the effect of the failure on the MISR during subsequent tests.
摘要翻译：一种用于通过运行一系列测试来识别电子设备失败的测试的电子设备的故障的系统和方法，而不必检查每个测试的结果，仅存储在电子设备失败的测试期间产生的信息，并使用该信息来诊断电子设备中的故障。测试结果累积到多输入移位寄存器（MISR）中，每次测试后不需要检查，以确定器件出现哪些测试失败。在后续测试期间在一次测试中出现故障的问题是通过在随后的测试期间预测故障对MISR的影响来处理的。

7. 发明申请

US20090241124A1 ONLINE MULTIPROCESSOR SYSTEM RELIABILITY DEFECT TESTING 有权
标题翻译：在线多处理器系统可靠性缺陷测试
公开(公告)号：US20090241124A1
公开(公告)日：2009-09-24
申请号：US12053642
申请日：2008-03-24
申请人： Monty M. Denneau , Vikram Iyengar , Phillip J. Nigh
发明人： Monty M. Denneau , Vikram Iyengar , Phillip J. Nigh
IPC分类号： G06F9/46
CPC分类号： G06F11/008 , G06F11/2025 , G06F11/2028 , G06F11/2242 , G06F11/3409
摘要： A multiprocessor system comprising a plurality of processors is disclosed. The plurality of processors includes a first processor including first monitor on-chip and a second processor including a including a second monitor on-chip. The first monitor on-chip is configured to measure load on the second processor and the second monitor on-chip is configured to measure load on the first processor. The first monitor on-chip is configured to cause the second monitor on-chip to perform a self-test on the second processor if the load on the second processor is below a second processor load threshold value and the second monitor on-chip is configured to cause the first monitor on-chip to perform a self-test on the first processor if the load on the first processor is below first processor load threshold value.
摘要翻译：公开了一种包括多个处理器的多处理器系统。多个处理器包括第一处理器，其包括片上第一监视器和第二处理器，其包括在片上包括第二监视器的第二处理器。第一个片上显示器被配置为测量第二处理器上的负载，并且片上第二个监视器被配置为测量第一处理器上的负载。如果第二处理器上的负载低于第二处理器负载阈值并且片上第二监视器被配置，片上的第一个监视器被配置为使片上的第二监视器在第二处理器上执行自检如果第一处理器上的负载低于第一处理器负载阈值，则使片上的第一个监视器在第一处理器上执行自检。

8. 发明授权

US07089514B2 Defect diagnosis for semiconductor integrated circuits 失效
标题翻译：半导体集成电路缺陷诊断
公开(公告)号：US07089514B2
公开(公告)日：2006-08-08
申请号：US10710879
申请日：2004-08-10
申请人： James W. Adkisson , Greg Bazan , John M. Cohn , Francis Gravel , Leendert M. Huisman , Phillip J. Nigh , Leah M. P. Pastel , Kenneth Rowe , Thomas G. Sopchak , David E. Sweenor
发明人： James W. Adkisson , Greg Bazan , John M. Cohn , Francis Gravel , Leendert M. Huisman , Phillip J. Nigh , Leah M. P. Pastel , Kenneth Rowe , Thomas G. Sopchak , David E. Sweenor
IPC分类号： G06F17/50
CPC分类号： G01R31/31718 , G01R31/318342
摘要： A method for defect diagnosis of semiconductor chip. The method comprises the steps of (a) identifying M design structures and N physical characteristics of the circuit design, wherein M and N are positive integers, wherein each design structure of the M design structures is testable as to pass or fail, and wherein each physical characteristic of the N physical characteristics is present in at least one design structure of the M design structures; (b) for each design structure of the M design structures of the circuit design, determining a fail rate and determining whether the fail rate is high or low; and (c) if every design structure of the M design structures in which a physical characteristic of the N physical characteristics is present has a high fail rate, then flagging the physical characteristic as being likely to contain at least a defect.
摘要翻译：一种半导体芯片缺陷诊断方法。该方法包括以下步骤：（a）识别电路设计的M个设计结构和N个物理特性，其中M和N是正整数，其中M个设计结构的每个设计结构可以通过或失败，并且其中每个 N物理特性的物理特性存在于M设计结构的至少一个设计结构中; （b）对于电路设计的M设计结构的每个设计结构，确定故障率并确定故障率是高还是低; 和（c）如果存在N个物理特性的物理特性的M设计结构的每个设计结构具有高故障率，则将物理特性标记为可能至少包含缺陷。

9. 发明授权

US07017095B2 Functional pattern logic diagnostic method 失效
标题翻译：功能模式逻辑诊断方法
公开(公告)号：US07017095B2
公开(公告)日：2006-03-21
申请号：US10064398
申请日：2002-07-10
申请人： Donato Forlenza , Franco Motika , Phillip J. Nigh
发明人： Donato Forlenza , Franco Motika , Phillip J. Nigh
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318586 , G01R31/318544
摘要： A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on the functional failure by determining the location of and type of error in the failing circuit. This is accomplished by identifying the failing vector during the functional test, observing the states of the failed device by unloading the values of the latches from the LSSD scan chain before the failing vector, generating a LOAD from the unloaded states of the latches, applying the generated LOAD as the first event of a newly created independent LSSD deterministic pattern, applying the primary inputs and Clocks that produced the failure to a correctly operating device, unloading the output of the correctly operating device to generate a deterministic LSSD pattern; and applying the generated deterministic LSSD pattern to the failing device to diagnose the failure using existing LSSD deterministic tools.
摘要翻译：通过组合确定性和功能测试，通过确定故障电路中的错误的位置和类型，基于功能故障来创建新的测试模式来诊断半导体器件功能测试故障的方法。这是通过在功能测试期间识别故障向量来实现的，通过在故障向量之前从LSSD扫描链中卸载锁存器的值来观察故障设备的状态，从锁存器的未加载状态生成LOAD，应用生成LOAD作为新创建的独立LSSD确定性模式的第一个事件，将产生故障的主输入和时钟应用于正确操作的设备，卸载正确操作设备的输出以生成确定性LSSD模式; 以及将生成的确定性LSSD模式应用于故障设备，以使用现有的LSSD确定性工具来诊断故障。

10. 发明授权

US06650130B1 Integrated circuit device defect detection method and apparatus employing light emission imaging 有权
标题翻译：采用发光成像的集成电路器件缺陷检测方法和装置
公开(公告)号：US06650130B1
公开(公告)日：2003-11-18
申请号：US09386572
申请日：1999-08-31
申请人： Jeffrey A. Kash , Phillip J. Nigh , David P. Vallet
发明人： Jeffrey A. Kash , Phillip J. Nigh , David P. Vallet
IPC分类号： G01R31303
CPC分类号： G01R31/311
摘要： A method of and apparatus (10) for detecting one or more defects (130) in a plurality of chips (110) on a wafer (40). The method comprises a first step of simultaneously providing electrical power to the plurality of chips, thereby generating one or more light signals (120) corresponding to the one or more defects in the plurality of chips. The second step is simultaneously forming an image (150) of the plurality of chips so as to simultaneously detect the one or more light signals. The apparatus (10) for carrying out the method comprises electrical probes (30) for providing electrical power to the plurality of chips, a detector (60) to detect the one or more light signals emitted by the chips as a result of electrical power interacting with the one or more defects, and an imaging system (50) arranged so as to form an image of the plurality of chips, including the light signals, onto the detection surface (64).
摘要翻译：一种用于检测晶片（40）上的多个芯片（110）中的一个或多个缺陷（130）的方法和装置（10）。该方法包括同时向多个芯片提供电力的第一步骤，从而产生对应于多个芯片中的一个或多个缺陷的一个或多个光信号（120）。第二步骤同时形成多个芯片的图像（150），以便同时检测一个或多个光信号。用于执行该方法的装置（10）包括用于向多个芯片提供电力的电探测器（30），检测器（60），用于检测由于电力相互作用而由芯片发射的一个或多个光信号具有一个或多个缺陷，以及成像系统（50），被布置成在检测表面（64）上形成包括光信号的多个芯片的图像。

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