专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07777265B2 Semiconductor device having contact barrier and method of manufacturing the same 有权
标题翻译：具有接触屏障的半导体器件及其制造方法
公开(公告)号：US07777265B2
公开(公告)日：2010-08-17
申请号：US11933039
申请日：2007-10-31
申请人： Hyeong-Sun Hong , Jae-Goo Lee , Dong-Hyun Kim , Sung-Un Kwon , Sang-Joon Park , Nam-Jung Kang
发明人： Hyeong-Sun Hong , Jae-Goo Lee , Dong-Hyun Kim , Sung-Un Kwon , Sang-Joon Park , Nam-Jung Kang
IPC分类号： H01L27/108
CPC分类号： H01L27/0207 , H01L21/76802 , H01L27/10808 , H01L27/10855 , H01L27/10885 , Y10S257/905
摘要： A semiconductor device having a contact barrier for insulating contacts with a large aspect ratio and having a fine pitch between adjacent conductive lines and a method of manufacturing the same are provided. The semiconductor device includes a buried contact formed in a region between two adjacent first conductive lines and two adjacent second conductive lines. Insulating lines define a width of the buried contact. To form the contact barrier, an interlayer dielectric layer formed on the second conductive lines is patterned to form a space and an insulating line having an etching ratio different from the interlayer dielectric layer is formed in the space. The interlayer dielectric layer is selectively wet etched relative to an insulating layer covering the second conductive line and the first insulating line to form buried contact hole. The buried contact hole is filled with conductive material to form a buried contact.
摘要翻译：提供一种半导体器件，其具有用于具有大纵横比的绝缘触点的接触屏障，并且在相邻的导线之间具有微细的间距及其制造方法。半导体器件包括形成在两个相邻的第一导电线和两个相邻的第二导电线之间的区域中的掩埋接触。绝缘线限定埋入触点的宽度。为了形成接触屏障，形成在第二导线上的层间电介质层形成空间，并且在该空间中形成具有与层间电介质层不同的蚀刻比的绝缘线。相对于覆盖第二导线和第一绝缘线的绝缘层选择性地湿蚀刻层间电介质层以形成掩埋接触孔。埋入的接触孔填充有导电材料以形成掩埋接触。

2. 发明申请

US20090203204A1 Methods of manufacturing semiconductor device having recess channel array transistor 失效
标题翻译：制造具有凹槽通道阵列晶体管的半导体器件的方法
公开(公告)号：US20090203204A1
公开(公告)日：2009-08-13
申请号：US12213230
申请日：2008-06-17
申请人： Gil-sub Kim , Yong-il Kim , Jong-seop Lee , Jai-kyun Park , Yun-sung Lee , Nam-jung Kang
发明人： Gil-sub Kim , Yong-il Kim , Jong-seop Lee , Jai-kyun Park , Yun-sung Lee , Nam-jung Kang
IPC分类号： H01L21/28
CPC分类号： H01L21/28061 , H01L29/1037 , H01L29/4236 , H01L29/4941 , H01L29/66621
摘要： Methods of manufacturing a semiconductor device having an RCAT are provided. The method includes forming a first recess having a first depth formed in an active region of a semiconductor substrate, and a second recess having a second depth that is less than the first depth formed in an isolation layer. The depth of the second recess is decreased by removing the isolation layer from the upper surface of the isolation layer by a desired thickness. A gate dielectric layer is formed on an inner wall of the first recess and a gate is formed on the gate dielectric layer.
摘要翻译：提供了具有RCAT的半导体器件的制造方法。该方法包括形成具有形成在半导体衬底的有源区中的第一深度的第一凹部和具有小于在隔离层中形成的第一深度的第二深度的第二凹部。通过将隔离层从隔离层的上表面移除希望的厚度来减小第二凹部的深度。栅电介质层形成在第一凹槽的内壁上，栅极形成在栅介质层上。

3. 发明申请

US20100237394A1 Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20100237394A1
公开(公告)日：2010-09-23
申请号：US12659735
申请日：2010-03-19
申请人： Jai-Kyun Park , Hyeong-Sun Hong , Jong-Seop Lee , Yong-Il Kim , Yun-Sung Lee , Nam-Jung Kang , Jae-Hoon Song , Gil-Sub Kim
发明人： Jai-Kyun Park , Hyeong-Sun Hong , Jong-Seop Lee , Yong-Il Kim , Yun-Sung Lee , Nam-Jung Kang , Jae-Hoon Song , Gil-Sub Kim
IPC分类号： H01L27/108
CPC分类号： H01L27/0207 , H01L27/10855
摘要： A semiconductor memory device includes unit active regions, word lines extending in a first direction over the unit active region, bit lines extending on the word lines in a second direction substantially perpendicularly to the first direction, first pad contacts in contact with central portions of the unit active regions, the first pad contacts being arranged between the word lines, direct contacts electrically connected between the first pad contacts and the bit lines, second pad contacts in contact with edge portions of the unit active regions, the second pad contacts being arranged between the word lines and between the bit lines, buried contacts electrically connected to the second pad contacts, and capacitors electrically connected to the buried contacts.
摘要翻译：半导体存储器件包括单元有源区域，在单元有源区域上沿第一方向延伸的字线，沿着基本垂直于第一方向的第二方向在字线上延伸的位线，与第一方向的中心部分接触的第一焊盘触点所述第一焊盘触点布置在所述字线之间，直接触点电连接在所述第一焊盘触点和所述位线之间，所述第二焊盘触点与所述单元有源区域的边缘部分接触，所述第二焊盘触点布置在字线和位线之间，电连接到第二焊盘触点的埋入触点，以及电连接到埋入触点的电容器。

4. 发明申请

US20090181529A1 Method of forming a contact hole and method of manufacturing a semiconductor device having the same 失效
标题翻译：形成接触孔的方法和制造具有该接触孔的半导体器件的方法
公开(公告)号：US20090181529A1
公开(公告)日：2009-07-16
申请号：US12319406
申请日：2009-01-07
申请人： Nam-Jung Kang , Jae-Hoon Song , So-Hyun Ryu , Dong-Kwan Yang
发明人： Nam-Jung Kang , Jae-Hoon Song , So-Hyun Ryu , Dong-Kwan Yang
IPC分类号： H01L21/4763 , H01L21/3205
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76897 , H01L27/10855 , H01L27/10876 , H01L27/10888 , H01L27/10891 , H01L27/10894 , Y10S438/95
摘要： In a method of forming a contact hole and a method of manufacturing a semiconductor device having the same, a first insulation interlayer is formed on a substrate. A dummy pattern is formed on the first insulation interlayer. A second insulation interlayer is formed to cover the dummy pattern. A photoresist pattern is formed on the second insulation interlayer. The photoresist pattern has an exposed portion. The dummy pattern under the photoresist pattern is arranged to cross over the exposed portion of the photoresist pattern. The first and second insulation interlayers are etched using the photoresist pattern and the dummy pattern as an etching mask, to form a plurality of contact holes on both sides of the dummy pattern. Accordingly, the contact holes may be formed to have a smaller width.
摘要翻译：在形成接触孔的方法和制造具有该接触孔的半导体器件的方法中，在衬底上形成第一绝缘中间层。在第一绝缘中间层上形成虚拟图案。形成第二绝缘中间层以覆盖虚设图案。在第二绝缘中间层上形成光致抗蚀剂图案。光致抗蚀剂图案具有暴露部分。光致抗蚀剂图案下面的虚设图案被布置成与光致抗蚀剂图案的暴露部分交叉。使用光致抗蚀剂图案和伪图案作为蚀刻掩模来蚀刻第一和第二绝缘夹层，以在虚设图案的两侧上形成多个接触孔。因此，接触孔可以形成为具有较小的宽度。

5. 发明申请

US20060263985A1 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20060263985A1
公开(公告)日：2006-11-23
申请号：US11383722
申请日：2006-05-16
申请人： Nam-Jung KANG , Ji-Young KIM
发明人： Nam-Jung KANG , Ji-Young KIM
IPC分类号： H01L21/8234
CPC分类号： H01L21/823878 , H01L21/823814 , H01L27/10888 , H01L27/10894
摘要： A method of fabricating a semiconductor device to prevent the profiles of source/drain regions from being deformed due to the thermal budget. The method can simplify the overall process of fabricating a semiconductor device by reducing the number of processing steps of forming a photoresist pattern as an ion implantation mask, and can reduce the variations of the transistor characteristics.
摘要翻译：制造半导体器件以防止源极/漏极区域的轮廓由于热量预算而变形的方法。该方法可以通过减少形成作为离子注入掩模的光致抗蚀剂图案的处理步骤的数量来简化制造半导体器件的整个过程，并且可以减小晶体管特性的变化。

6. 发明申请

US20100240179A1 Methods of manufacturing capacitor structures and methods of manufacturing semiconductor devices using the same 有权
标题翻译：制造电容器结构的方法和使用其制造半导体器件的方法
公开(公告)号：US20100240179A1
公开(公告)日：2010-09-23
申请号：US12659769
申请日：2010-03-19
申请人： Yong-Il Kim , Dae-Ik Kim , Yun-Sung Lee , Nam-Jung Kang
发明人： Yong-Il Kim , Dae-Ik Kim , Yun-Sung Lee , Nam-Jung Kang
IPC分类号： H01L21/8242 , H01G9/00
CPC分类号： H01L27/0207 , H01G4/01 , H01G4/228 , H01G4/33 , H01L27/10852 , H01L28/91 , Y10T29/417
摘要： A capacitor structure includes a plurality of lower electrodes on a substrate, the lower electrodes having planar top surfaces and being arranged in a first direction to define a lower electrode column, a plurality of lower electrode columns being arranged in a second direction perpendicular to the first direction to define a lower electrode matrix, a plurality of supports on upper sidewalls of at least two adjacent lower electrodes, a dielectric layer on the lower electrodes and the supports, and an upper electrode on the dielectric layer.
摘要翻译：电容器结构包括在基板上的多个下电极，下电极具有平面顶表面并且沿第一方向布置以限定下电极柱，多个下电极柱沿垂直于第一限定下电极矩阵的方向，在至少两个相邻的下电极的上侧壁上的多个支撑件，下电极和支撑件上的电介质层，以及介电层上的上电极。

7. 发明授权

US07799643B2 Method of fabricating semiconductor device having self-aligned contact plug 失效
标题翻译：制造具有自对准接触插头的半导体器件的方法
公开(公告)号：US07799643B2
公开(公告)日：2010-09-21
申请号：US12112438
申请日：2008-04-30
申请人： Nam-Jung Kang , Dong-Soo Woo , Hyeong-Sun Hong , Dong-Hyun Kim
发明人： Nam-Jung Kang , Dong-Soo Woo , Hyeong-Sun Hong , Dong-Hyun Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10855
摘要： Methods of fabricating a semiconductor device having a self-aligned contact plug are provided. Methods include forming a lower insulating layer on a semiconductor substrate, forming a plurality of interconnection patterns parallel to each other on the lower insulating layer; forming an upper insulating layer that is configured to fill between the interconnection patterns, and forming a plurality of first mask patterns crossing the plurality of interconnection patterns, ones of the plurality of first mask patterns parallel to each other on the semiconductor substrate having the upper insulating layer. Methods may include forming a second mask pattern that is self-aligned to the plurality of first mask patterns and that is between ones of the plurality of first mask patterns, etching the upper insulating layer and the lower insulating layer using the first and second mask patterns and the plurality of interconnection patterns as etch masks to form a plurality of contact holes exposing the semiconductor substrate, and forming a plurality of contact plugs in respective ones of the plurality of contact holes. Semiconductor devices are also provided.
摘要翻译：提供制造具有自对准接触插头的半导体器件的方法。方法包括在半导体衬底上形成下绝缘层，在下绝缘层上形成彼此平行的多个互连图案; 形成上部绝缘层，其被构造成填充在所述互连图案之间，并且形成与所述多个互连图案交叉的多个第一掩模图案，所述多个第一掩模图案中的所述第一掩模图案在所述半导体衬底上彼此平行，层。方法可以包括形成第二掩模图案，该第二掩模图案与多个第一掩模图案自对准，并且在多个第一掩模图案中的一个之间，使用第一和第二掩模图案蚀刻上绝缘层和下绝缘层以及所述多个互连图案作为蚀刻掩模，以形成暴露所述半导体衬底的多个接触孔，以及在所述多个接触孔中的相应接触孔中形成多个接触插塞。还提供了半导体器件。

8. 发明授权

US07713873B2 Methods of forming contact structures semiconductor devices 有权
标题翻译：形成接触结构半导体器件的方法
公开(公告)号：US07713873B2
公开(公告)日：2010-05-11
申请号：US12151997
申请日：2008-05-12
申请人： Seong-Goo Kim , Hyeong-Sun Hong , Dong-Hyun Kim , Nam-Jung Kang
发明人： Seong-Goo Kim , Hyeong-Sun Hong , Dong-Hyun Kim , Nam-Jung Kang
IPC分类号： H01L21/44
CPC分类号： H01L29/4236 , H01L21/76829 , H01L21/76897 , H01L27/0207 , H01L27/10855 , H01L27/10876
摘要： Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures. The second and first interlayer dielectric layers are etched using the mask patterns, the barrier patterns and the bit line structures as an etching mask to form buried contact holes and buried contact plugs are formed in the buried contact holes.
摘要翻译：在半导体器件中形成接触结构的方法包括提供包括有源区和跨越有源区的字线的半导体衬底。在半导体衬底上形成第一层间电介质层。形成延伸穿过第一层间电介质层的直接接触插塞以接触所选择的有源区域。位线结构形成在第一层间电介质层上并且通过直接接触插塞与被选择的有源区域耦合的字线交叉。在包括位线结构的半导体衬底上形成第二层间电介质层。阻挡层图案形成为与位线结构平行延伸并进入第二层间电介质层。掩模图形形成在第二层间介质层上的直接接触插塞的整个顶表面和位线结构上。使用掩模图案蚀刻第二和第一层间电介质层，将掩模图案和位线结构作为蚀刻掩模形成埋入的接触孔，并且在埋入的接触孔中形成掩埋的接触插塞。

9. 发明申请

US20080088029A1 SEMICONDUCTOR DEVICE HAVING CONTACT BARRIER AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有接触障碍物的半导体器件及其制造方法
公开(公告)号：US20080088029A1
公开(公告)日：2008-04-17
申请号：US11933039
申请日：2007-10-31
申请人： Hyeong-Sun HONG , Jae-Goo LEE , Dong-Hyun KIM , Sung-Un KWON , Sang-Joon PARK , Nam-Jung KANG
发明人： Hyeong-Sun HONG , Jae-Goo LEE , Dong-Hyun KIM , Sung-Un KWON , Sang-Joon PARK , Nam-Jung KANG
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L27/0207 , H01L21/76802 , H01L27/10808 , H01L27/10855 , H01L27/10885 , Y10S257/905
摘要： A semiconductor device having a contact barrier for insulating contacts with a large aspect ratio and having a fine pitch between adjacent conductive lines and a method of manufacturing the same are provided. The semiconductor device includes a buried contact formed in a region between two adjacent first conductive lines and two adjacent second conductive lines. Insulating lines define a width of the buried contact. To form the contact barrier, an interlayer dielectric layer formed on the second conductive lines is patterned to form a space and an insulating line having an etching ratio different from the interlayer dielectric layer is formed in the space. The interlayer dielectric layer is selectively wet etched relative to an insulating layer covering the second conductive line and the first insulating line to form buried contact hole. The buried contact hole is filled with conductive material to form a buried contact.
摘要翻译：提供一种半导体器件，其具有用于具有大纵横比的绝缘触点的接触屏障，并且在相邻的导线之间具有微细的间距及其制造方法。半导体器件包括形成在两个相邻的第一导电线和两个相邻的第二导电线之间的区域中的掩埋接触。绝缘线限定埋入触点的宽度。为了形成接触屏障，形成在第二导线上的层间电介质层形成空间，并且在该空间中形成具有与层间电介质层不同的蚀刻比的绝缘线。相对于覆盖第二导线和第一绝缘线的绝缘层选择性地湿蚀刻层间电介质层以形成掩埋接触孔。埋入的接触孔填充有导电材料以形成掩埋接触。

10. 发明授权

US08343845B2 Methods of manufacturing capacitor structures and methods of manufacturing semiconductor devices using the same 有权
标题翻译：制造电容器结构的方法和使用其制造半导体器件的方法
公开(公告)号：US08343845B2
公开(公告)日：2013-01-01
申请号：US12659769
申请日：2010-03-19
申请人： Yong-Il Kim , Dae-Ik Kim , Yun-Sung Lee , Nam-Jung Kang
发明人： Yong-Il Kim , Dae-Ik Kim , Yun-Sung Lee , Nam-Jung Kang
IPC分类号： H01L21/30
CPC分类号： H01L27/0207 , H01G4/01 , H01G4/228 , H01G4/33 , H01L27/10852 , H01L28/91 , Y10T29/417
摘要： A capacitor structure includes a plurality of lower electrodes on a substrate, the lower electrodes having planar top surfaces and being arranged in a first direction to define a lower electrode column, a plurality of lower electrode columns being arranged in a second direction perpendicular to the first direction to define a lower electrode matrix, a plurality of supports on upper sidewalls of at least two adjacent lower electrodes, a dielectric layer on the lower electrodes and the supports, and an upper electrode on the dielectric layer.
摘要翻译：电容器结构包括在基板上的多个下电极，下电极具有平面顶表面并且沿第一方向布置以限定下电极柱，多个下电极柱沿垂直于第一限定下电极矩阵的方向，在至少两个相邻的下电极的上侧壁上的多个支撑件，下电极和支撑件上的电介质层，以及介电层上的上电极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式