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    • 1. 发明授权
    • Semiconductor devices including buried gate electrodes
    • 包括掩埋栅电极的半导体器件
    • US08450786B2
    • 2013-05-28
    • US13241716
    • 2011-09-23
    • Dae-Ik KimYong-Il Kim
    • Dae-Ik KimYong-Il Kim
    • H01L27/108
    • H01L27/088H01L21/82345H01L21/823456H01L21/823462H01L27/105H01L27/1052H01L27/10876H01L27/10894H01L29/4236H01L29/66621
    • A semiconductor device capable of reducing a thickness, an electronic product employing the same, and a method of fabricating the same are provided. The method of fabricating a semiconductor device includes preparing a semiconductor substrate having first and second active regions. A first transistor in the first active region includes a first gate pattern and first impurity regions. A second transistor the second active region includes a second gate pattern and second impurity regions. A first conductive pattern is on the first transistor, wherein at least a part of the first conductive pattern is disposed at a same distance from an upper surface of the semiconductor substrate as at least a part of the second gate pattern. The first conductive pattern may be formed on the first transistor while the second transistor is formed.
    • 提供了能够减小厚度的半导体器件,采用该半导体器件的电子产品及其制造方法。 制造半导体器件的方法包括制备具有第一和第二有源区的半导体衬底。 第一有源区中的第一晶体管包括第一栅极图案和第一杂质区域。 第二晶体管,第二有源区包括第二栅极图案和第二杂质区域。 第一导电图案在第一晶体管上,其中第一导电图案的至少一部分设置在与半导体衬底的上表面相同的距离处,作为第二栅极图案的至少一部分。 第一导电图案可以形成在第一晶体管上,而形成第二晶体管。
    • 7. 发明申请
    • CIRCUIT STRUCTURES AND METHODS WITH BEOL LAYER(S) CONFIGURED TO BLOCK ELECTROMAGNETIC INTERFERENCE
    • 具有配置为阻塞电磁干扰的波形层的电路结构和方法
    • US20080277773A1
    • 2008-11-13
    • US11747342
    • 2007-05-11
    • Dae Ik KIMJonghae KIMMoon Ju KIMChoongyeun (Chuck) CHO
    • Dae Ik KIMJonghae KIMMoon Ju KIMChoongyeun (Chuck) CHO
    • H01L23/48H01L21/00
    • H01L23/552H01L2924/0002H01L2924/00
    • Back end of line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic interference. One such BEOL circuit structure includes one or more semiconductor substrates supporting one or more integrated circuits, and one or more BEOL layers disposed over the semiconductor substrate(s). At least one BEOL layer includes a conductive pattern defined at least partially by a plurality of elements arrayed in a first direction and a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in at least one of the first and second directions to block electromagnetic interference of a particular wavelength from passing therethrough. In one implementation, a first conductive pattern of a first BEOL layer polarizes electromagnetic interference, and a second conductive pattern of a second BEOL layer blocks the polarized electromagnetic interference.
    • 提供后端(BEOL)电路结构和方法来阻止外部来源或内部产生的电磁干扰。 一种这样的BEOL电路结构包括支撑一个或多个集成电路的一个或多个半导体衬底以及设置在半导体衬底之上的一个或多个BEOL层。 至少一个BEOL层包括至少部分地由在第一方向和第二方向排列的多个元件至少部分地限定的导电图案。 多个元件的大小和位置在第一和第二方向中的至少一个方向上,以阻止特定波长的电磁干扰通过。 在一个实施方案中,第一BEOL层的第一导电图案使电磁干扰偏振,并且第二BEOL层的第二导电图案阻挡极化的电磁干扰。
    • 8. 发明申请
    • METHOD AND SYSTEM FOR RANDOM NUMBER GENERATOR WITH RANDOM SAMPLING
    • 随机采样随机数发生器的方法与系统
    • US20080136697A1
    • 2008-06-12
    • US11608264
    • 2006-12-08
    • Choongyeun ChoDae Ik KimJonghae KimMoon J. Kim
    • Choongyeun ChoDae Ik KimJonghae KimMoon J. Kim
    • G06F7/58
    • G06F7/588
    • In a random number generator, a first converter converts a first analog noise signal into a random digital clock signal and a second converter samples a second analog noise signal asynchronous to the first analog noise signal in response to the random digital clock signal and generates a random digital number stream. In one aspect, a random number generator output block samples the second converter random digital number stream in response to the random digital clock signal and generates a random number generator block output. In another aspect a pseudo noise source state machine generates the random digital clock signal in response to a first seed generated from the first analog noise signal, a second seed from process variation digital amplifier, and a past machine state.
    • 在随机数发生器中,第一转换器将第一模拟噪声信号转换成随机数字时钟信号,并且第二转换器响应于随机数字时钟信号对与第一模拟噪声信号异步的第二模拟噪声信号进行采样,并产生随机数 数字数字流。 一方面,随机数发生器输出块响应于随机数字时钟信号对第二转换器随机数字数字流进行采样,并产生随机数发生器块输出。 在另一方面,伪噪声源状态机响应于从第一模拟噪声信号产生的第一种子,来自过程变化数字放大器的第二种子和过去的机器状态,产生随机数字时钟信号。