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1. 发明授权

US07799643B2 Method of fabricating semiconductor device having self-aligned contact plug 失效
标题翻译：制造具有自对准接触插头的半导体器件的方法
公开(公告)号：US07799643B2
公开(公告)日：2010-09-21
申请号：US12112438
申请日：2008-04-30
申请人： Nam-Jung Kang , Dong-Soo Woo , Hyeong-Sun Hong , Dong-Hyun Kim
发明人： Nam-Jung Kang , Dong-Soo Woo , Hyeong-Sun Hong , Dong-Hyun Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10855
摘要： Methods of fabricating a semiconductor device having a self-aligned contact plug are provided. Methods include forming a lower insulating layer on a semiconductor substrate, forming a plurality of interconnection patterns parallel to each other on the lower insulating layer; forming an upper insulating layer that is configured to fill between the interconnection patterns, and forming a plurality of first mask patterns crossing the plurality of interconnection patterns, ones of the plurality of first mask patterns parallel to each other on the semiconductor substrate having the upper insulating layer. Methods may include forming a second mask pattern that is self-aligned to the plurality of first mask patterns and that is between ones of the plurality of first mask patterns, etching the upper insulating layer and the lower insulating layer using the first and second mask patterns and the plurality of interconnection patterns as etch masks to form a plurality of contact holes exposing the semiconductor substrate, and forming a plurality of contact plugs in respective ones of the plurality of contact holes. Semiconductor devices are also provided.
摘要翻译：提供制造具有自对准接触插头的半导体器件的方法。方法包括在半导体衬底上形成下绝缘层，在下绝缘层上形成彼此平行的多个互连图案; 形成上部绝缘层，其被构造成填充在所述互连图案之间，并且形成与所述多个互连图案交叉的多个第一掩模图案，所述多个第一掩模图案中的所述第一掩模图案在所述半导体衬底上彼此平行，层。方法可以包括形成第二掩模图案，该第二掩模图案与多个第一掩模图案自对准，并且在多个第一掩模图案中的一个之间，使用第一和第二掩模图案蚀刻上绝缘层和下绝缘层以及所述多个互连图案作为蚀刻掩模，以形成暴露所述半导体衬底的多个接触孔，以及在所述多个接触孔中的相应接触孔中形成多个接触插塞。还提供了半导体器件。

2. 发明申请

US20080283957A1 Method of Fabricating Semiconductor Device Having Self-Aligned Contact Plug and Related Device 失效
标题翻译：具有自对准接触插头及相关器件的半导体器件制造方法
公开(公告)号：US20080283957A1
公开(公告)日：2008-11-20
申请号：US12112438
申请日：2008-04-30
申请人： Nam-Jung Kang , Dong-Soo Woo , Hyeong-Sun Hong , Dong-Hyun Kim
发明人： Nam-Jung Kang , Dong-Soo Woo , Hyeong-Sun Hong , Dong-Hyun Kim
IPC分类号： H01L29/00 , H01L21/4763
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10855
摘要： Methods of fabricating a semiconductor device having a self-aligned contact plug are provided. Methods include forming a lower insulating layer on a semiconductor substrate, forming a plurality of interconnection patterns parallel to each other on the lower insulating layer; forming an upper insulating layer that is configured to fill between the interconnection patterns, and forming a plurality of first mask patterns crossing the plurality of interconnection patterns, ones of the plurality of first mask patterns parallel to each other on the semiconductor substrate having the upper insulating layer. Methods may include forming a second mask pattern that is self-aligned to the plurality of first mask patterns and that is between ones of the plurality of first mask patterns, etching the upper insulating layer and the lower insulating layer using the first and second mask patterns and the plurality of interconnection patterns as etch masks to form a plurality of contact holes exposing the semiconductor substrate, and forming a plurality of contact plugs in respective ones of the plurality of contact holes. Semiconductor devices are also provided.
摘要翻译：提供制造具有自对准接触插头的半导体器件的方法。方法包括在半导体衬底上形成下绝缘层，在下绝缘层上形成彼此平行的多个互连图案; 形成上部绝缘层，其被构造成填充在所述互连图案之间，并且形成与所述多个互连图案交叉的多个第一掩模图案，所述多个第一掩模图案中的所述第一掩模图案在具有所述上绝缘体的半导体衬底上彼此平行层。方法可以包括形成第二掩模图案，该第二掩模图案与多个第一掩模图案自对准，并且位于多个第一掩模图案之间，使用第一和第二掩模图案蚀刻上绝缘层和下绝缘层以及所述多个互连图案作为蚀刻掩模，以形成暴露所述半导体衬底的多个接触孔，以及在所述多个接触孔中的相应接触孔中形成多个接触插塞。还提供了半导体器件。

3. 发明申请

US20120299090A1 Semiconductor Devices Including Dual Gate Electrode Structures And Related Methods 有权
标题翻译：包括双栅电极结构的半导体器件及相关方法
公开(公告)号：US20120299090A1
公开(公告)日：2012-11-29
申请号：US13298644
申请日：2011-11-17
申请人： Ji-Young Kim , Gyo-Young Jin , Hyeong-Sun Hong , Yong-Chul Oh , Yoo-Sang Hwang , Sung-Kwan Choi , Dong-Soo Woo , Hyun-Woo Chung
发明人： Ji-Young Kim , Gyo-Young Jin , Hyeong-Sun Hong , Yong-Chul Oh , Yoo-Sang Hwang , Sung-Kwan Choi , Dong-Soo Woo , Hyun-Woo Chung
IPC分类号： H01L29/78
CPC分类号： G11C11/4096 , G11C11/404 , G11C11/4085 , H01L21/823437 , H01L27/10823 , H01L27/10873 , H01L27/10876 , H01L27/10891 , H01L27/10894 , H01L29/41741 , H01L29/4236 , H01L29/66484 , H01L29/66613 , H01L29/66666 , H01L29/7827 , H01L29/7831
摘要： A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.
摘要翻译：半导体器件可以包括具有限定其间的沟道区的第一和第二间隔开的源极/漏极区的半导体衬底，以及在第一和第二间隔开的源极/漏极区之间的沟道区上的控制栅极结构。更具体地，控制栅极结构可以包括在与第一源极/漏极区域相邻的沟道区域上的第一栅极电极以及与第二源极/漏极区域相邻的沟道区域上的第二栅极电极。此外，第一和第二栅电极可以是电隔离的。还讨论了相关设备，结构，操作方法和制造方法。

4. 发明授权

US08884340B2 Semiconductor devices including dual gate electrode structures and related methods 有权
标题翻译：包括双栅电极结构和相关方法的半导体器件
公开(公告)号：US08884340B2
公开(公告)日：2014-11-11
申请号：US13298644
申请日：2011-11-17
申请人： Ji-Young Kim , Gyo-Young Jin , Hyeong-Sun Hong , Yong-Chul Oh , Yoo-Sang Hwang , Sung-Kwan Choi , Dong-Soo Woo , Hyun-Woo Chung
发明人： Ji-Young Kim , Gyo-Young Jin , Hyeong-Sun Hong , Yong-Chul Oh , Yoo-Sang Hwang , Sung-Kwan Choi , Dong-Soo Woo , Hyun-Woo Chung
IPC分类号： H01L21/336 , H01L29/772 , G11C11/404 , H01L27/108 , H01L29/66 , H01L29/78 , G11C11/408 , H01L29/417 , H01L29/423 , H01L21/8234
CPC分类号： G11C11/4096 , G11C11/404 , G11C11/4085 , H01L21/823437 , H01L27/10823 , H01L27/10873 , H01L27/10876 , H01L27/10891 , H01L27/10894 , H01L29/41741 , H01L29/4236 , H01L29/66484 , H01L29/66613 , H01L29/66666 , H01L29/7827 , H01L29/7831
摘要： A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.
摘要翻译：半导体器件可以包括具有限定其间的沟道区的第一和第二间隔开的源极/漏极区的半导体衬底，以及在第一和第二间隔开的源极/漏极区之间的沟道区上的控制栅极结构。更具体地，控制栅极结构可以包括在与第一源极/漏极区域相邻的沟道区域上的第一栅极电极以及与第二源极/漏极区域相邻的沟道区域上的第二栅极电极。此外，第一和第二栅电极可以是电隔离的。还讨论了相关设备，结构，操作方法和制造方法。

5. 发明授权

US08610191B2 Semiconductor devices and dynamic random access memory devices including buried gate pattern with high-k capping layer 有权
标题翻译：半导体器件和动态随机存取存储器件，包括具有高k覆盖层的掩埋栅极图案
公开(公告)号：US08610191B2
公开(公告)日：2013-12-17
申请号：US12958601
申请日：2010-12-02
申请人： Joon-Seok Moon , Dong-Soo Woo , Jaerok Kahng , Jinwoo Lee , Keeshik Park
发明人： Joon-Seok Moon , Dong-Soo Woo , Jaerok Kahng , Jinwoo Lee , Keeshik Park
IPC分类号： H01L29/78 , H01L27/108
CPC分类号： H01L27/10876 , H01L29/4236
摘要： Semiconductor devices and dynamic random access memory devices including a buried gate electrode are provided, the semiconductor devices include a substrate with a gate trench, a buried gate electrode partially filling the inside of the gate trench, a capping layer pattern in the gate trench and over the buried gate electrode, source/drain regions below an upper surface of the substrate and adjacent to both sides of the buried gate electrode, and a gate insulation layer interposed between the trench and the buried gate electrode. The capping layer pattern includes a high-k material layer that directly contacts an upper surface of the buried gate electrode.
摘要翻译：提供了包括掩埋栅电极的半导体器件和动态随机存取存储器件，半导体器件包括具有栅极沟槽的衬底，部分填充栅极沟槽内部的掩埋栅电极，栅极沟槽中的覆盖层图案掩埋栅电极，在衬底的上表面下方并且与掩埋栅电极的两侧相邻的源极/漏极区以及介于沟槽和掩埋栅极之间的栅极绝缘层。覆盖层图案包括直接接触掩埋栅电极的上表面的高k材料层。

6. 发明申请

US20100081395A1 DRAM HAVING STACKED CAPACITORS OF DIFFERENT CAPACITANCES 失效
标题翻译：具有不同电容堆叠电容器的DRAM
公开(公告)号：US20100081395A1
公开(公告)日：2010-04-01
申请号：US12416722
申请日：2009-04-01
申请人： Dong-Soo Woo , Jong-Soo Kim
发明人： Dong-Soo Woo , Jong-Soo Kim
IPC分类号： H04B1/38 , G11C11/24 , H01L21/8242
CPC分类号： G11C11/24 , H01L27/0207 , H01L27/10814 , H01L27/10852 , H01L28/60
摘要： A DRAM device having a plurality of memory blocks, including edge-located memory blocks and adjacent central memory blocks. An edge-located memory block shares a sense amplifier with an adjacent central memory block. The memory cells in the edge-located memory block include data storage capacitors having a greater capacitance value than data storage capacitors in the memory cells in the adjacent central memory block. The data storage capacitors in edge-located memory cells may have greater surface area than data storage capacitors in the central memory cells. The data storage capacitors in edge-located memory cells may be formed by connecting in parallel two data storage capacitors of the shape and size of data storage capacitors used in each of the memory cells of the adjacent central memory block.
摘要翻译：具有多个存储块的DRAM装置，包括边缘定位的存储块和相邻的中央存储块。边缘位置的存储块与相邻的中央存储块共享读出放大器。位于边缘的存储器块中的存储器单元包括具有比相邻中央存储器块中的存储器单元中的数据存储电容器更大的电容值的数据存储电容器。位于边缘的存储单元中的数据存储电容器可以具有比中央存储单元中的数据存储电容器更大的表面积。边缘定位的存储单元中的数据存储电容器可以通过并联两个数据存储电容器形成，这两个数据存储电容器在相邻的中央存储块的每个存储单元中使用的数据存储电容器的形状和尺寸。

7. 发明授权

US08184471B2 DRAM having stacked capacitors of different capacitances 失效
标题翻译： DRAM具有不同电容的堆叠电容器
公开(公告)号：US08184471B2
公开(公告)日：2012-05-22
申请号：US12416722
申请日：2009-04-01
申请人： Dong-Soo Woo , Jong-Soo Kim
发明人： Dong-Soo Woo , Jong-Soo Kim
IPC分类号： G11C11/24
CPC分类号： G11C11/24 , H01L27/0207 , H01L27/10814 , H01L27/10852 , H01L28/60
摘要： A DRAM device having a plurality of memory blocks, including edge-located memory blocks and adjacent central memory blocks. An edge-located memory block shares a sense amplifier with an adjacent central memory block. The memory cells in the edge-located memory block include data storage capacitors having a greater capacitance value than data storage capacitors in the memory cells in the adjacent central memory block. The data storage capacitors in edge-located memory cells may have greater surface area than data storage capacitors in the central memory cells. The data storage capacitors in edge-located memory cells may be formed by connecting in parallel two data storage capacitors of the shape and size of data storage capacitors used in each of the memory cells of the adjacent central memory block.
摘要翻译：具有多个存储块的DRAM装置，包括边缘定位的存储块和相邻的中央存储块。边缘位置的存储块与相邻的中央存储块共享读出放大器。位于边缘的存储器块中的存储器单元包括具有比相邻中央存储器块中的存储器单元中的数据存储电容器更大的电容值的数据存储电容器。位于边缘的存储单元中的数据存储电容器可以具有比中央存储单元中的数据存储电容器更大的表面积。边缘定位的存储单元中的数据存储电容器可以通过并联两个数据存储电容器形成，这两个数据存储电容器在相邻的中央存储块的每个存储单元中使用的数据存储电容器的形状和尺寸。

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