专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07777466B2 Voltage regulator or non-volatile memories implemented with low-voltage transistors 有权
标题翻译：用低压晶体管实现的稳压器或非易失性存储器
公开(公告)号：US07777466B2
公开(公告)日：2010-08-17
申请号：US11844470
申请日：2007-08-24
申请人： Luca Crippa , Giancarlo Ragone , Miriam Sangalli , Giovanni Campardo , Rino Micheloni
发明人： Luca Crippa , Giancarlo Ragone , Miriam Sangalli , Giovanni Campardo , Rino Micheloni
IPC分类号： G05F1/40
CPC分类号： G11C5/147 , G05F1/565 , G11C16/30
摘要： A voltage regulator integrated in a chip of semiconductor material is provided. The regulator has a first input terminal for receiving a first voltage and an output terminal for providing a regulated voltage being obtained from the first voltage, the regulator including: a differential amplifier for receiving a comparison voltage and a feedback signal being a function of the regulated voltage, and for proving a regulation signal according to a comparison between the comparison voltage and the feedback signal, the differential amplifier having a first supply terminal being coupled with a reference terminal for receiving a reference voltage and a second supply terminal, a regulation transistor having a control terminal for receiving the regulation signal, and a conduction first terminal and a conduction second terminal being coupled through loading means between the reference terminal and the first input terminal of the regulator, the second terminal of the regulation transistor being coupled with the output terminal of the regulator, wherein the second supply terminal of the differential amplifier is coupled with a second input terminal of the regulator for receiving a second voltage being lower than the first voltage in absolute value, and wherein the regulator further includes a set of auxiliary transistors being connected in series between the second terminal of the regulation transistor and the output terminal of the regulator, and control means for controlling the auxiliary transistors according to the regulated voltage.
摘要翻译：提供集成在半导体材料芯片中的电压调节器。所述调节器具有用于接收第一电压的第一输入端子和用于提供从所述第一电压获得的调节电压的输出端子，所述调节器包括：用于接收比较电压的差分放大器和作为所述第一电压的函数的反馈信号电压，并且为了根据比较电压和反馈信号之间的比较来证明调节信号，差分放大器具有与用于接收参考电压的参考端子耦合的第一电源端子和第二电源端子，调节晶体管具有用于接收所述调节信号的控制端子，以及通过所述参考端子和所述调节器的所述第一输入端子之间的负载装置耦合的导通第一端子和导通第二端子，所述调节晶体管的所述第二端子与所述输出端子的调节器，其中第二电源差分放大器的nal与调节器的第二输入端耦合，用于接收低于绝对值中的第一电压的第二电压，并且其中调节器还包括一组辅助晶体管，串联连接在第二端调节器的调节晶体管和输出端子，以及用于根据调节电压控制辅助晶体管的控制装置。

2. 发明申请

US20060291322A1 Circuit and method for retrieving data stored in semiconductor memory cells 有权
公开(公告)号：US20060291322A1
公开(公告)日：2006-12-28
申请号：US11444892
申请日：2006-05-31
申请人： Luca Crippa , Giancarlo Ragone , Miriam Sangalli , Rino Micheloni
发明人： Luca Crippa , Giancarlo Ragone , Miriam Sangalli , Rino Micheloni
IPC分类号： G11C8/00
CPC分类号： G11C11/5642 , G11C7/04 , G11C16/30
摘要： A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one memory cell for retrieving the data stored therein, the voltage generator including first means adapted to cause the generated voltage take a value in a set of target values including at least one target value, corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element having said electrical characteristic.

3. 发明授权

US07889586B2 Circuit and method for retrieving data stored in semiconductor memory cells 有权
标题翻译：用于检索存储在半导体存储单元中的数据的电路和方法
公开(公告)号：US07889586B2
公开(公告)日：2011-02-15
申请号：US12248843
申请日：2008-10-09
申请人： Luca Crippa , Giancarlo Ragone , Miriam Sangalli , Rino Micheloni
发明人： Luca Crippa , Giancarlo Ragone , Miriam Sangalli , Rino Micheloni
IPC分类号： G11C7/04
CPC分类号： G11C11/5642 , G11C7/04 , G11C16/30
摘要： A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one memory cell for retrieving the data stored therein, the voltage generator including first means adapted to cause the generated voltage take a value in a set of target values including at least one target value, corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element having said electrical characteristic.
摘要翻译：电路包括至少一个存储单元，适于根据其电特性的值存储数据，其根据第一变化规律表现出与温度的变化性; 提供电压发生器，用于产生要提供给所述至少一个存储单元的电压以检索存储在其中的数据，所述电压发生器包括适于使所产生的电压取值至少包括至少一组目标值的值的第一装置一个目标值，对应于要在存储器单元上执行的操作。电压发生器包括第二装置，用于使得所产生的电压所采取的值根据规定的第二变化规律随温度变化，利用具有所述电特性的补偿电路元件。

4. 发明授权

US07260005B2 Data bus architecture for a semiconductor memory 有权
标题翻译：半导体存储器的数据总线架构
公开(公告)号：US07260005B2
公开(公告)日：2007-08-21
申请号：US11281932
申请日：2005-11-17
申请人： Luca Crippa , Miriam Sangalli , Rino Micheloni
发明人： Luca Crippa , Miriam Sangalli , Rino Micheloni
IPC分类号： G11C7/00
CPC分类号： G11C7/10 , G11C7/08 , G11C7/1048
摘要： A semiconductor memory device is provided that includes memory cells, sense amplifiers, signal lines, isolating circuits, and a precharging circuit. Each signal line is coupled to an output of at least one of the sense amplifiers and each of the isolating circuits isolates an associated signal line from the output of the corresponding sense amplifier at least during an evaluating phase of the datum stored in the memory cell. The signal lines include at least two groups of signal lines, arranged such that coupling capacitances between the lines of the first group and the lines of the second group are substantially negligible. The precharging circuit precharges the first group of signal lines to a first voltage level and the second group of signal lines to a second voltage level.
摘要翻译：提供了包括存储单元，读出放大器，信号线，隔离电路和预充电电路的半导体存储器件。每个信号线耦合到读出放大器中的至少一个的输出，并且每个隔离电路至少在存储在存储单元中的数据的评估阶段期间将相关联的信号线与对应的读出放大器的输出隔离。信号线包括至少两组信号线，其布置成使得第一组的线和第二组的线之间的耦合电容基本上可忽略。预充电电路将第一组信号线预充电到第一电压电平，将第二组信号线预充电到第二电压电平。

5. 发明申请

US20070164811A1 MULTISTAGE REGULATOR FOR CHARGE-PUMP BOOSTED VOLTAGE APPLICATIONS, NOT REQUIRING INTEGRATION OF DEDICATED HIGH VOLTAGE HIGH SIDE TRANSISTORS 有权
标题翻译：用于充电泵升压电压应用的多级稳压器，不需要集成高压高压侧晶体管
公开(公告)号：US20070164811A1
公开(公告)日：2007-07-19
申请号：US11460370
申请日：2006-07-27
申请人： Luca Crippa , Miriam Sangalli , Giancarlo Ragone , Rino Micheloni
发明人： Luca Crippa , Miriam Sangalli , Giancarlo Ragone , Rino Micheloni
IPC分类号： G05F1/10
CPC分类号： G11C5/145 , G11C16/30
摘要： A multistage circuit for regulating the charge voltage or the discharge current of a capacitance of an integrated device at a certain charge-pump generated boosted voltage is implemented without integrating high voltage transistor structures having a type of conductivity corresponding to the same sign of the boosted voltage (high-side transistors). The multistage circuit current includes at least a first stage, and an output stage in cascade to the first stage and coupled to the capacitance. The first stage is supplied at an unboosted power supply voltage of the integrated device, and the output stage is supplied at an unregulated charge-pump generated boosted voltage. The first stage includes a transistor having a type of conductivity corresponding to an opposite sign of the boosted voltage and of the power supply voltage. The drain of the output stage transistor is coupled to the boosted voltage either through a resistive pull-up or a voltage limiter.
摘要翻译：在一定的电荷泵产生的升压电压下，用于调节集成器件的电容的充电电压或放电电流的多级电路被实现，而不需要集成具有对应于升压电压相同符号的导电类型的高压晶体管结构（高侧晶体管）。多级电路电流包括至少第一级和级联到第一级并耦合到电容的输出级。第一级是在集成器件的未升压的电源电压下提供的，并且输出级以未调节的电荷泵产生的升压电压供电。第一级包括具有对应于升压电压和电源电压的相反符号的导电类型的晶体管。输出级晶体管的漏极通过电阻上拉或电压限制器耦合到升压电压。

6. 发明申请

US20060164155A1 Low-ripple boosted voltage generator 审中-公开
标题翻译：低纹波升压电压发生器
公开(公告)号：US20060164155A1
公开(公告)日：2006-07-27
申请号：US11323937
申请日：2005-12-30
申请人： Giancarlo Ragone , Miriam Sangalli , Rino Micheloni
发明人： Giancarlo Ragone , Miriam Sangalli , Rino Micheloni
IPC分类号： G05F1/10
CPC分类号： G11C5/145
摘要： The output voltage ripple of a single stage or a multi-stage charge pump may be significantly reduced by introducing in the voltage generator a cascode connected output transistor. In operation, this output transistor may be in a conduction state and may be controlled with a voltage having a smaller ripple than the voltage output by the charge pump.
摘要翻译：通过在电压发生器中引入共源共栅输出晶体管，可以显着降低单级或多级电荷泵的输出电压纹波。在操作中，该输出晶体管可以处于导通状态，并且可以通过具有比电荷泵输出的电压更小的纹波的电压来控制。

7. 发明授权

US07863967B2 Multistage regulator for charge-pump boosted voltage applications 有权
标题翻译：用于电荷泵升压电压应用的多级调节器
公开(公告)号：US07863967B2
公开(公告)日：2011-01-04
申请号：US11460370
申请日：2006-07-27
申请人： Luca Crippa , Miriam Sangalli , Giancarlo Ragone , Rino Micheloni
发明人： Luca Crippa , Miriam Sangalli , Giancarlo Ragone , Rino Micheloni
IPC分类号： G05F1/46 , G11C16/30
CPC分类号： G11C5/145 , G11C16/30
摘要： A multistage circuit for regulating the charge voltage or the discharge current of a capacitance of an integrated device at a certain charge-pump generated boosted voltage is implemented without integrating high voltage transistor structures having a type of conductivity corresponding to the same sign of the boosted voltage (high-side transistors). The multistage circuit current includes at least a first stage, and an output stage in cascade to the first stage and coupled to the capacitance. The first stage is supplied at an unboosted power supply voltage of the integrated device, and the output stage is supplied at an unregulated charge-pump generated boosted voltage. The first stage includes a transistor having a type of conductivity corresponding to an opposite sign of the boosted voltage and of the power supply voltage. The drain of the output stage transistor is coupled to the boosted voltage either through a resistive pull-up or a voltage limiter.
摘要翻译：在一定的电荷泵产生的升压电压下，用于调节集成器件的电容的充电电压或放电电流的多级电路不需要集成具有对应于升压电压相同符号的电导率类型的高压晶体管结构，（高侧晶体管）。多级电路电流包括至少第一级和级联到第一级并耦合到电容的输出级。第一级是在集成器件的未升压的电源电压下提供的，并且输出级以未调节的电荷泵产生的升压电压供电。第一级包括具有对应于升压电压和电源电压的相反符号的导电类型的晶体管。输出级晶体管的漏极通过电阻上拉或电压限制器耦合到升压电压。

8. 发明授权

US07521983B2 High-voltage switch with low output ripple for non-volatile floating-gate memories 有权
标题翻译：非挥发性浮栅存储器具有低输出纹波的高压开关
公开(公告)号：US07521983B2
公开(公告)日：2009-04-21
申请号：US11437405
申请日：2006-05-19
申请人： Giancarlo Ragone , Luca Crippa , Miriam Sangalli , Rino Micheloni
发明人： Giancarlo Ragone , Luca Crippa , Miriam Sangalli , Rino Micheloni
IPC分类号： H03K17/687
CPC分类号： H02M3/073 , G11C5/145 , G11C8/08 , G11C16/08 , G11C16/12 , H02M2003/077 , H03K3/356104 , H03K17/063 , H03K17/6872 , H03K17/6874
摘要： A high-voltage switch has a high-voltage input terminal, receiving a high voltage, and an output terminal. A pass transistor, having a control terminal, is connected between the high-voltage input terminal and the output terminal. The output of a voltage-multiplying circuit of the charge-pump type is connected to the control terminal. The voltage-multiplying circuit is of a symmetrical type, has first and second charge-storage means, receiving a clock signal of a periodic type, and has a first circuit branch and a second circuit branch, which are symmetrical to one another and operate in phase opposition with respect to the clock signal.
摘要翻译：高压开关具有高电压输入端子，接收高电压和输出端子。具有控制端子的传输晶体管连接在高电压输入端子和输出端子之间。电荷泵型的倍压电路的输出端与控制端子连接。电压倍增电路是对称型的，具有第一和第二电荷存储装置，接收周期型的时钟信号，并且具有第一电路支路和第二电路支路，它们彼此对称并在相对于时钟信号的相位相反。

9. 发明授权

US07221212B2 Trimming functional parameters in integrated circuits 有权
标题翻译：在集成电路中修剪功能参数
公开(公告)号：US07221212B2
公开(公告)日：2007-05-22
申请号：US11113818
申请日：2005-04-25
申请人： Luca Crippa , Miriam Sangalli , Salvatrice Scommegna , Rino Micheloni
发明人： Luca Crippa , Miriam Sangalli , Salvatrice Scommegna , Rino Micheloni
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G11C5/147 , G11C29/02 , G11C29/021 , G11C29/028
摘要： A trimming structure for trimming functional parameters of an Integrated Circuit—IC—(100) includes a first (115a) and at least one second functional blocks (115b, . . . ,115n) with which a first (Vrg,a) and at least one second IC functional parameters (Vrg,b, . . . ,Vrg,n) are respectively associated. The trimming structure includes respective trimmable circuit structures (205a,210a, . . . ,205n,210n) included in the first and at least one second functional blocks, and trimming configuration storage (110) for storing trimming configurations for the trimmable circuit structures. A change in the trimming configuration of the first functional block causes a corresponding change in the trimming configuration of the second functional block. Further, a change in the second IC functional parameter in response to the corresponding change in the trimming configuration of the second functional block is proportional to the change in the first IC functional parameter consequent to the change in the trimming configuration of the first functional block.
摘要翻译：用于修整集成电路IC-（100）的功能参数的修整结构包括第一（115a）和至少一个第二功能块（115b，...，115n），第一（Vr1，...，115n））和至少一个第二IC功能参数（Vrg，b，...，Vrg，n）分别相关联。修剪结构包括包括在第一和至少一个第二功能块中的相应可调节电路结构（205a，210a，...，205n，210n），以及修剪配置存储（110），用于存储用于可调节电路结构。第一功能块的修整配置的变化导致第二功能块的修整配置的相应变化。此外，响应于第二功能块的修整配置的相应变化，第二IC功能参数的变化与第一功能块的修整配置的改变所引起的第一IC功能参数的变化成比例。

10. 发明授权

US06493268B1 Circuit device for performing hierarchic row decoding in non-volatile memory devices 有权
标题翻译：用于在非易失性存储器件中执行分级行解码的电路装置
公开(公告)号：US06493268B1
公开(公告)日：2002-12-10
申请号：US09905163
申请日：2001-07-12
申请人： Osama Khouri , Andrea Pierin , Rino Micheloni , Stefano Gregori , Guido Torelli , Miriam Sangalli
发明人： Osama Khouri , Andrea Pierin , Rino Micheloni , Stefano Gregori , Guido Torelli , Miriam Sangalli
IPC分类号： G11C1600
CPC分类号： G11C16/08
摘要： A circuit device for performing hierarchic row decoding in semiconductor memory devices of the non-volatile type, which memory devices include an array of memory cells with column-ordered sectors, wherein each sector has a respective group of local wordlines linked to a main wordline. The circuit device includes a main wordline driver provided at each main wordline, and a local decoder provided at each local wordline. This circuit device further comprises, for each main wordline, a dedicated path connected between the main wordline and the local decoders of the associated local wordlines and connected to an external terminal arranged to receive a read/program voltage, the dedicated path enabling transfer of the read/program voltage to the local decoders.
摘要翻译：一种用于在非易失性类型的半导体存储器件中执行分级行解码的电路装置，该存储器件包括具有列排列扇区的存储器单元阵列，其中每个扇区具有链接到主字线的相应组的本地字线。电路装置包括在每个主字线处提供的主字线驱动器和在每个本地字线处提供的本地解码器。该电路装置还包括对于每个主字线，连接在相关联的本地字线的主字线和本地解码器之间的专用路径，并连接到布置成接收读/写电压的外部端子，该专用路径使得能够传送读/编程电压到本地解码器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式